Convert CONFIG_SYS_SPI_U_BOOT_OFFS to Kconfig

This converts the following to Kconfig:
   CONFIG_SYS_SPI_U_BOOT_OFFS

Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
[trini: Expose this for SPL_SPI_SUNXI for now]
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Hannes Schmelzer
2019-08-22 15:41:46 +02:00
committed by Tom Rini
parent f8584bbe72
commit 1ee774d209
159 changed files with 103 additions and 119 deletions

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@@ -45,7 +45,6 @@
/* SPL support */
#define CONFIG_SPL_STACK 0xe6340000
#define CONFIG_SPL_MAX_SIZE 0x4000
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_CONS_SCIF2
#define CONFIG_SH_SCIF_CLK_FREQ 65000000

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@@ -274,7 +274,6 @@
*/
#if defined(CONFIG_SPI_BOOT)
/* SPL related */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */

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@@ -90,6 +90,5 @@
#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
/* SPI SPL */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
#endif /* __CONFIG_AM57XX_EVM_H */

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@@ -151,11 +151,6 @@
#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#elif CONFIG_SYS_USE_NANDFLASH
#elif CONFIG_SPI_BOOT && CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
#elif CONFIG_NAND_BOOT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE

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@@ -124,10 +124,6 @@
#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#elif CONFIG_SPI_BOOT && CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
#elif CONFIG_NAND_BOOT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE

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@@ -443,7 +443,6 @@ DEFAULT_LINUX_BOOT_ENV \
*/
#if defined(CONFIG_SPI_BOOT)
/* SPL related */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */

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@@ -181,7 +181,6 @@ NANDTGTS \
#if defined(CONFIG_SPI)
/* SPI Flash */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
/* Environment */
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \

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@@ -72,7 +72,6 @@ BUR_COMMON_ENV \
#define CONFIG_INITRD_TAG
/* SPI Flash */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
/* Environment */
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT

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@@ -17,7 +17,6 @@
#define CONFIG_MACH_TYPE 4122
#ifdef CONFIG_SPL
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
#include "imx6_spl.h"
#endif

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@@ -165,8 +165,5 @@
/* SPL */
#include "imx7_spl.h"
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
#endif /* CONFIG_SPL_BUILD */
#endif /* __CONFIG_H */

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@@ -83,7 +83,6 @@
#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI)
/* SPL related SPI defines */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#elif defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC) || defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA)
/* SPL related MMC defines */

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@@ -207,7 +207,6 @@
/* SPL */
#include "imx6_spl.h"
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
/* Display */
#define CONFIG_IMX_HDMI

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@@ -114,7 +114,6 @@
/* SPL defines. */
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20))
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
/* EEPROM */

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@@ -97,7 +97,6 @@
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
/* SPL related SPI defines */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x30000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif

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@@ -110,7 +110,6 @@
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
#ifdef CONFIG_USE_SPIFLASH
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
#endif

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@@ -73,7 +73,6 @@
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* SPL related SPI defines */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif /* _CONFIG_DB_88F6720_H */

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@@ -68,7 +68,6 @@
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
/* SPL related SPI defines */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif

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@@ -85,7 +85,6 @@
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
/* SPL related SPI defines */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif

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@@ -82,7 +82,6 @@
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* SPL related SPI defines */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */

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@@ -23,7 +23,6 @@
/* SPL */
#include "imx6_spl.h" /* common IMX6 SPL configuration */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x11400
#define CONFIG_SPL_TARGET "u-boot-with-spl.imx"
/* Miscellaneous configurable options */

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@@ -45,7 +45,6 @@
#define CONFIG_SYS_SPI_ARGS_SIZE 0x10000
#include "imx6_spl.h"
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS

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@@ -92,7 +92,6 @@
#endif
/* SPI SPL */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
/* USB xHCI HOST */
#define CONFIG_USB_XHCI_OMAP

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@@ -91,7 +91,6 @@
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* SPL related SPI defines */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
/* DS414 bus width is 32bits */
#define CONFIG_DDR_32BIT

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@@ -20,7 +20,6 @@
#define CONFIG_MXC_UART
#ifdef CONFIG_SPL
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
#include "imx6_spl.h"
#endif

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@@ -40,7 +40,6 @@
/* SPL support */
#define CONFIG_SPL_STACK 0xe6340000
#define CONFIG_SPL_MAX_SIZE 0x4000
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_CONS_SCIF0
#define CONFIG_SH_SCIF_CLK_FREQ 65000000

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@@ -104,7 +104,6 @@
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x30000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif

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@@ -22,7 +22,6 @@
#ifdef CONFIG_TARGET_J721E_A72_EVM
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x280000
#else
/*
* Maximum size in memory allocated to the SPL BSS. Keep it as tight as
@@ -45,7 +44,6 @@
/* Configure R5 SPL post-relocation malloc pool in DDR */
#define CONFIG_SYS_SPL_MALLOC_START 0x84000000
#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x80000
#endif
#ifdef CONFIG_SYS_K3_SPL_ATF

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@@ -40,7 +40,6 @@
/* SPL support */
#define CONFIG_SPL_STACK 0xe6340000
#define CONFIG_SPL_MAX_SIZE 0x4000
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_CONS_SCIF0
#define CONFIG_SH_SCIF_CLK_FREQ 65000000

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@@ -41,7 +41,6 @@
/* SPL support */
#define CONFIG_SPL_STACK 0xe6340000
#define CONFIG_SPL_MAX_SIZE 0x4000
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_CONS_SCIF0
#define CONFIG_SH_SCIF_CLK_FREQ 65000000

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@@ -71,7 +71,6 @@
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* SPL related SPI defines */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */

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@@ -38,9 +38,6 @@
#define CONFIG_SPL_PAD_TO 0x10000
#define CONFIG_SPI_ADDR 0x30000000
#ifdef CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
#endif
#define CONFIG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO)
/* SPL -> Uboot */

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@@ -116,7 +116,6 @@
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
#ifdef CONFIG_USE_SPIFLASH
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000
#endif

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@@ -59,7 +59,6 @@
/* SPL */
#ifdef CONFIG_SPL
#include "imx6_spl.h"
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
#endif
#define CONFIG_FEC_MXC

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@@ -117,7 +117,6 @@
/* CPU */
#ifdef CONFIG_SPI_BOOT
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
#endif

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@@ -8,7 +8,6 @@
#define __PCM058_CONFIG_H
#ifdef CONFIG_SPL
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
#include "imx6_spl.h"
#endif

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@@ -8,7 +8,6 @@
#define __PCM058_CONFIG_H
#ifdef CONFIG_SPL
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
#include "imx6_spl.h"
#endif

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@@ -119,7 +119,6 @@
/* CPU */
#ifdef CONFIG_SPI_BOOT
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
#elif defined(CONFIG_ENV_IS_IN_NAND)
#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE

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@@ -45,7 +45,6 @@
/* SPL support */
#define CONFIG_SPL_STACK 0xe6340000
#define CONFIG_SPL_MAX_SIZE 0x4000
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_CONS_SCIF0
#define CONFIG_SH_SCIF_CLK_FREQ 65000000

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@@ -26,9 +26,6 @@
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
/* RAW SD card / eMMC locations. */
#ifdef CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#endif
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_SDRAM_BASE 0x60000000

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@@ -29,9 +29,6 @@
#define CONFIG_IRAM_BASE 0xff700000
/* RAW SD card / eMMC locations. */
#ifdef CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#endif
/* FAT sd card locations. */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1

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@@ -24,10 +24,6 @@
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
#ifdef CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#endif
/* FAT sd card locations. */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_SDRAM_BASE 0

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@@ -38,9 +38,6 @@
#define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000
/* RAW SD card / eMMC locations. */
#ifdef CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#endif
/* FAT sd card locations. */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1

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@@ -62,8 +62,4 @@
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
#if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL_SPI_LOAD)
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
#endif
#endif

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@@ -69,10 +69,6 @@
#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#elif CONFIG_SPI_BOOT
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
#endif
#endif

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@@ -83,10 +83,6 @@
#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#elif CONFIG_SPI_BOOT && CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
#elif CONFIG_NAND_BOOT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE

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@@ -47,11 +47,6 @@
#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#elif CONFIG_SYS_USE_NANDFLASH
#elif CONFIG_SPI_BOOT
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
#elif CONFIG_NAND_BOOT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE

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@@ -47,10 +47,6 @@
#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#elif CONFIG_SPI_BOOT
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
#elif CONFIG_NAND_BOOT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE

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@@ -94,8 +94,6 @@
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC

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@@ -45,7 +45,6 @@
/* SPL support */
#define CONFIG_SPL_STACK 0xe6340000
#define CONFIG_SPL_MAX_SIZE 0x4000
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_CONS_SCIF2
#define CONFIG_SH_SCIF_CLK_FREQ 65000000

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@@ -213,13 +213,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#endif
/* SPL QSPI boot support */
#ifdef CONFIG_SPL_SPI_SUPPORT
#if defined(CONFIG_TARGET_SOCFPGA_GEN5) && defined(CONFIG_SPL_SPI_LOAD)
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) && defined(CONFIG_SPL_SPI_LOAD)
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000
#endif
#endif
/* SPL NAND boot support */
#ifdef CONFIG_SPL_NAND_SUPPORT

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@@ -201,7 +201,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
#define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \
- CONFIG_SYS_SPL_MALLOC_SIZE)
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x3C00000
/* SPL SDMMC boot support */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1

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@@ -49,7 +49,6 @@
/* SPL support */
#define CONFIG_SPL_STACK 0xe6340000
#define CONFIG_SPL_MAX_SIZE 0x4000
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_CONS_SCIFA0
#define CONFIG_SH_SCIF_CLK_FREQ 52000000

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@@ -118,10 +118,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 8
#endif
#if defined(CONFIG_SPL_SPI_SUNXI) && defined(CONFIG_SPL_SPI_LOAD)
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
#endif
/* mmc config */
#ifdef CONFIG_MMC
#define CONFIG_MMC_SUNXI_SLOT 0

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@@ -102,7 +102,6 @@
#if defined(CONFIG_SPL_BUILD)
/* SPL related */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#endif
/* load address */

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@@ -106,7 +106,6 @@
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* SPL related SPI defines */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */

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@@ -129,9 +129,6 @@
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#ifdef CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#endif
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
/*

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@@ -43,9 +43,6 @@
CONFIG_SYS_SPL_MALLOC_SIZE + \
SPL_MALLOC_F_SIZE + \
KEYSTONE_SPL_STACK_SIZE - 4)
#ifdef CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
#endif
/* SRAM scratch space entries */
#define SRAM_SCRATCH_SPACE_ADDR CONFIG_SPL_STACK + 0x8

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@@ -22,8 +22,6 @@
/* SPL settings */
#undef CONFIG_SPL_ETH_SUPPORT
#undef CONFIG_SYS_SPI_U_BOOT_OFFS
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#undef CONFIG_SPL_MAX_FOOTPRINT
#define CONFIG_SPL_MAX_FOOTPRINT CONFIG_SYS_SPI_U_BOOT_OFFS
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"

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@@ -50,7 +50,6 @@
#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI
/* SPL related SPI defines */
# define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
# define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif

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@@ -117,7 +117,6 @@
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* SPL related SPI defines */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif /* _CONFIG_X530_H */

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@@ -217,9 +217,6 @@
# define CONFIG_SYS_SPI_KERNEL_OFFS 0x80000
# define CONFIG_SYS_SPI_ARGS_OFFS 0xa0000
# define CONFIG_SYS_SPI_ARGS_SIZE 0xa0000
#ifdef CONFIG_SPL_SPI_LOAD
# define CONFIG_SYS_SPI_U_BOOT_OFFS 0x170000
#endif
#endif
/* u-boot is like dtb */

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@@ -293,9 +293,6 @@
/* qspi mode is working fine */
#ifdef CONFIG_ZYNQ_QSPI
#ifdef CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000
#endif
#define CONFIG_SYS_SPI_ARGS_OFFS 0x200000
#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
#define CONFIG_SYS_SPI_KERNEL_OFFS (CONFIG_SYS_SPI_ARGS_OFFS + \