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Fix new found CFG_

Browse Source 
Also fix some minor typos.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Jean-Christophe PLAGNIOL-VILLARD
2008-12-14 10:29:39 +01:00
committed by Wolfgang Denk
parent 0e0c862efe
commit 3aed3aa2c1
10 changed files with 14 additions and 14 deletions
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8
include/configs/PMC440.h
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@@ -219,8 +219,8 @@
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
#endif
#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
/* 440EPx errata CHIP 11 */
#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
/* 440EPx errata CHIP 11 */
/*-----------------------------------------------------------------------
* I2C
@@ -490,8 +490,8 @@
#endif
/* Memory Bank 1 (RESET) initialization */
#define CFG_EBC_PB1AP 0x7f817200 //0x03017200
#define CFG_EBC_PB1CR (CFG_RESET_BASE | 0x1c000)
#define CONFIG_SYS_EBC_PB1AP 0x7f817200 //0x03017200
#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_RESET_BASE | 0x1c000)
/* Memory Bank 4 (FPGA / 32Bit) initialization */
#define CONFIG_SYS_EBC_PB4AP 0x03840f40 /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */

4
include/configs/afeb9260.h
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@@ -29,7 +29,7 @@
/* ARM asynchronous clock */
#define AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */
#define AT91_MASTER_CLOCK 89999598 /* peripheral = main / 2 */
#define CFG_AT91_PLLB 0x107c3e18 /* PLLB settings for USB */
#define CONFIG_SYS_AT91_PLLB 0x107c3e18 /* PLLB settings for USB */
#define CONFIG_SYS_HZ 1000000 /* 1us resolution */
#define AT91_SLOW_CLOCK 32768 /* slow clock */
@@ -150,7 +150,7 @@
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CFG_LONGHELP 1
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))

2
include/configs/at91cap9adk.h
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@@ -32,7 +32,7 @@
#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
#define AT91_MASTER_CLOCK 100000000 /* peripheral */
#define AT91_CPU_CLOCK 200000000 /* cpu */
#define CFG_AT91_PLLB 0x10073e01 /* PLLB settings for USB */
#define CONFUG_SYS_AT91_PLLB 0x10073e01 /* PLLB settings for USB */
#define CONFIG_SYS_HZ 1000000 /* 1us resolution */
#define AT91_SLOW_CLOCK 32768 /* slow clock */

2
include/configs/at91sam9260ek.h
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@@ -32,7 +32,7 @@
#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
#define AT91_MASTER_CLOCK 100000000 /* peripheral */
#define AT91_CPU_CLOCK 200000000 /* cpu */
#define CFG_AT91_PLLB 0x107c3e18 /* PLLB settings for USB */
#define CONFIG_SYS_AT91_PLLB 0x107c3e18 /* PLLB settings for USB */
#define CONFIG_SYS_HZ 1000000 /* 1us resolution */
#define AT91_SLOW_CLOCK 32768 /* slow clock */

2
include/configs/at91sam9263ek.h
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@@ -32,7 +32,7 @@
#define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
#define AT91_MASTER_CLOCK 100000000 /* peripheral */
#define AT91_CPU_CLOCK 200000000 /* cpu */
#define CFG_AT91_PLLB 0x133a3e8d /* PLLB settings for USB */
#define CONFIG_SYS_AT91_PLLB 0x133a3e8d /* PLLB settings for USB */
#define CONFIG_SYS_HZ 1000000 /* 1us resolution */
#define AT91_SLOW_CLOCK 32768 /* slow clock */