mirror of
https://github.com/frank-w/u-boot.git
synced 2026-01-21 07:52:31 +08:00
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
This commit is contained in:
Tom Rini
@@ -34,6 +34,29 @@
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#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
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#endif
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#define CONFIG_NAND_FSL_ELBC
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#ifdef CONFIG_NAND
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#define CONFIG_SPL
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#define CONFIG_SPL_INIT_MINIMAL
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_NAND_MINIMAL
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SYS_TEXT_BASE 0x00201000
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#define CONFIG_SPL_TEXT_BASE 0xfffff000
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#define CONFIG_SPL_MAX_SIZE (4 * 1024)
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#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
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#define CONFIG_SPL_RELOC_STACK 0x00100000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SPL_MAX_SIZE)
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#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
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#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
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#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
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#endif
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/* High Level Configuration Options */
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#define CONFIG_BOOKE /* BOOKE */
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#define CONFIG_E500 /* BOOKE e500 family */
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@@ -84,6 +107,13 @@
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#define CONFIG_SYS_CCSRBAR 0xffe00000
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#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
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/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
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SPL code*/
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
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#endif
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/* DDR Setup */
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#define CONFIG_DDR_SPD
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#define CONFIG_VERY_BIG_RAM
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@@ -105,6 +135,30 @@
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#define CONFIG_SYS_SPD_BUS_NUM 1
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#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
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/* These are used when DDR doesn't use SPD. */
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#define CONFIG_SYS_SDRAM_SIZE 2048
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#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
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#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
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#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
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#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
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#define CONFIG_SYS_DDR_TIMING_3 0x00010000
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#define CONFIG_SYS_DDR_TIMING_0 0x40110104
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#define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
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#define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
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#define CONFIG_SYS_DDR_MODE_1 0x00441221
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#define CONFIG_SYS_DDR_MODE_2 0x00000000
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#define CONFIG_SYS_DDR_INTERVAL 0x0a280100
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#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
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#define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
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#define CONFIG_SYS_DDR_CONTROL 0xc7000008
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#define CONFIG_SYS_DDR_CONTROL_2 0x24401041
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#define CONFIG_SYS_DDR_TIMING_4 0x00220001
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#define CONFIG_SYS_DDR_TIMING_5 0x02401400
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#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
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#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
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/*
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* Memory map
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*
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@@ -118,6 +172,7 @@
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* Localbus non-cacheable
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* 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
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* 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
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* 0xff80_0000 0xff80_7fff NAND 32K non-cacheable
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* 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
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* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
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* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
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@@ -126,38 +181,84 @@
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/*
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* Local Bus Definitions
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*/
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#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
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#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
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#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
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#else
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#endif
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#define CONFIG_FLASH_BR_PRELIM \
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(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
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(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
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#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
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#ifdef CONFIG_NAND
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#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
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#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
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#else
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#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
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#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
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#endif
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#define CONFIG_SYS_BR1_PRELIM \
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(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
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#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM
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#define CONFIG_SYS_FLASH_BANKS_LIST \
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{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
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#define CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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#define CONFIG_SYS_MAX_FLASH_BANKS 2
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 1024
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#ifndef CONFIG_SYS_MONITOR_BASE
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
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#else
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#endif
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#endif
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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/* Nand Flash */
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#if defined(CONFIG_NAND_FSL_ELBC)
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#define CONFIG_SYS_NAND_BASE 0xff800000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
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#else
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#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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#endif
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_MTD_NAND_VERIFY_WRITE
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#define CONFIG_CMD_NAND 1
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#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
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#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
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/* NAND flash config */
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#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
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| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
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| BR_PS_8 /* Port Size = 8 bit */ \
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| BR_MS_FCM /* MSEL = FCM */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \
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| OR_FCM_PGS /* Large Page*/ \
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| OR_FCM_CSCT \
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| OR_FCM_CST \
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| OR_FCM_CHT \
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| OR_FCM_SCY_1 \
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| OR_FCM_TRLX \
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| OR_FCM_EHTR)
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#ifdef CONFIG_NAND
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#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
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#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
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#else
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#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
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#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
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#endif
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#endif /* CONFIG_NAND_FSL_ELBC */
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_BOARD_EARLY_INIT_R
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#define CONFIG_MISC_INIT_R
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@@ -177,6 +278,8 @@
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#define PIXIS_LBMAP_SWITCH 7
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#define PIXIS_LBMAP_MASK 0xF0
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#define PIXIS_LBMAP_ALTBANK 0x20
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#define PIXIS_SPD 0x07
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#define PIXIS_SPD_SYSCLK_MASK 0x07
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#define PIXIS_ELBC_SPI_MASK 0xc0
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#define PIXIS_SPI 0x80
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@@ -199,6 +302,9 @@
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_NS16550_MIN_FUNCTIONS
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#endif
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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@@ -419,7 +525,6 @@
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/*
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* Environment
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*/
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#ifdef CONFIG_SYS_RAMBOOT
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#ifdef CONFIG_RAMBOOT_SPIFLASH
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_SPI_BUS 0
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@@ -433,16 +538,15 @@
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#elif defined(CONFIG_NAND_U_BOOT)
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#elif defined(CONFIG_NAND)
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
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#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
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#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
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#else
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#elif defined(CONFIG_SYS_RAMBOOT)
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#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
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#define CONFIG_ENV_SIZE 0x2000
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#endif
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#else
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#define CONFIG_ENV_IS_IN_FLASH
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#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
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@@ -714,6 +714,7 @@
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
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"bank_intlv=cs0_cs1;" \
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"usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
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"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
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"netdev=eth0\0" \
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"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
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