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OneNAND support (take #2)
[PATCH 3/3] OneNAND support (take #2) OneNAND support at U-Boot Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
This commit is contained in:
Kyungmin Park
committed by
Stefan Roese
Stefan Roese
parent
17aa280045
commit
d7e8ce101a
127
include/linux/mtd/bbm.h
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127
include/linux/mtd/bbm.h
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@@ -0,0 +1,127 @@
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/*
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* linux/include/linux/mtd/bbm.h
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*
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* NAND family Bad Block Management (BBM) header file
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* - Bad Block Table (BBT) implementation
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*
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* Copyright (c) 2005-2007 Samsung Electronics
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* Kyungmin Park <kyungmin.park@samsung.com>
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*
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* Copyright (c) 2000-2005
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* Thomas Gleixner <tglx@linuxtronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __LINUX_MTD_BBM_H
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#define __LINUX_MTD_BBM_H
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/* The maximum number of NAND chips in an array */
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#ifndef NAND_MAX_CHIPS
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#define NAND_MAX_CHIPS 8
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#endif
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/**
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* struct nand_bbt_descr - bad block table descriptor
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* @param options options for this descriptor
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* @param pages the page(s) where we find the bbt, used with
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* option BBT_ABSPAGE when bbt is searched,
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* then we store the found bbts pages here.
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* Its an array and supports up to 8 chips now
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* @param offs offset of the pattern in the oob area of the page
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* @param veroffs offset of the bbt version counter in the oob are of the page
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* @param version version read from the bbt page during scan
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* @param len length of the pattern, if 0 no pattern check is performed
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* @param maxblocks maximum number of blocks to search for a bbt. This number of
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* blocks is reserved at the end of the device
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* where the tables are written.
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* @param reserved_block_code if non-0, this pattern denotes a reserved
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* (rather than bad) block in the stored bbt
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* @param pattern pattern to identify bad block table or factory marked
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* good / bad blocks, can be NULL, if len = 0
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*
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* Descriptor for the bad block table marker and the descriptor for the
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* pattern which identifies good and bad blocks. The assumption is made
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* that the pattern and the version count are always located in the oob area
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* of the first block.
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*/
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struct nand_bbt_descr {
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int options;
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int pages[NAND_MAX_CHIPS];
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int offs;
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int veroffs;
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uint8_t version[NAND_MAX_CHIPS];
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int len;
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int maxblocks;
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int reserved_block_code;
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uint8_t *pattern;
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};
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/* Options for the bad block table descriptors */
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/* The number of bits used per block in the bbt on the device */
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#define NAND_BBT_NRBITS_MSK 0x0000000F
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#define NAND_BBT_1BIT 0x00000001
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#define NAND_BBT_2BIT 0x00000002
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#define NAND_BBT_4BIT 0x00000004
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#define NAND_BBT_8BIT 0x00000008
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/* The bad block table is in the last good block of the device */
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#define NAND_BBT_LASTBLOCK 0x00000010
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/* The bbt is at the given page, else we must scan for the bbt */
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#define NAND_BBT_ABSPAGE 0x00000020
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/* The bbt is at the given page, else we must scan for the bbt */
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#define NAND_BBT_SEARCH 0x00000040
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/* bbt is stored per chip on multichip devices */
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#define NAND_BBT_PERCHIP 0x00000080
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/* bbt has a version counter at offset veroffs */
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#define NAND_BBT_VERSION 0x00000100
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/* Create a bbt if none axists */
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#define NAND_BBT_CREATE 0x00000200
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/* Search good / bad pattern through all pages of a block */
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#define NAND_BBT_SCANALLPAGES 0x00000400
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/* Scan block empty during good / bad block scan */
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#define NAND_BBT_SCANEMPTY 0x00000800
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/* Write bbt if neccecary */
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#define NAND_BBT_WRITE 0x00001000
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/* Read and write back block contents when writing bbt */
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#define NAND_BBT_SAVECONTENT 0x00002000
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/* Search good / bad pattern on the first and the second page */
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#define NAND_BBT_SCAN2NDPAGE 0x00004000
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/* The maximum number of blocks to scan for a bbt */
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#define NAND_BBT_SCAN_MAXBLOCKS 4
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/*
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* Constants for oob configuration
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*/
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#define ONENAND_BADBLOCK_POS 0
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/**
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* struct bbt_info - [GENERIC] Bad Block Table data structure
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* @param bbt_erase_shift [INTERN] number of address bits in a bbt entry
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* @param badblockpos [INTERN] position of the bad block marker in the oob area
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* @param bbt [INTERN] bad block table pointer
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* @param badblock_pattern [REPLACEABLE] bad block scan pattern used for initial bad block scan
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* @param priv [OPTIONAL] pointer to private bbm date
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*/
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struct bbm_info {
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int bbt_erase_shift;
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int badblockpos;
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int options;
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uint8_t *bbt;
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int (*isbad_bbt) (struct mtd_info * mtd, loff_t ofs, int allowbbt);
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/* TODO Add more NAND specific fileds */
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struct nand_bbt_descr *badblock_pattern;
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void *priv;
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};
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/* OneNAND BBT interface */
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extern int onenand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd);
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extern int onenand_default_bbt (struct mtd_info *mtd);
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#endif /* __LINUX_MTD_BBM_H */
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143
include/linux/mtd/onenand.h
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143
include/linux/mtd/onenand.h
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@@ -0,0 +1,143 @@
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/*
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* linux/include/linux/mtd/onenand.h
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*
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* Copyright (C) 2005-2007 Samsung Electronics
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* Kyungmin Park <kyungmin.park@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __LINUX_MTD_ONENAND_H
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#define __LINUX_MTD_ONENAND_H
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#include <linux/mtd/onenand_regs.h>
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/* Note: The header order is impoertant */
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#include <onenand_uboot.h>
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#include <linux/mtd/bbm.h>
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#define MAX_BUFFERRAM 2
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#define MAX_ONENAND_PAGESIZE (2048 + 64)
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/* Scan and identify a OneNAND device */
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extern int onenand_scan (struct mtd_info *mtd, int max_chips);
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/* Free resources held by the OneNAND device */
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extern void onenand_release (struct mtd_info *mtd);
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/**
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* onenand_state_t - chip states
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* Enumeration for OneNAND flash chip state
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*/
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typedef enum {
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FL_READY,
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FL_READING,
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FL_WRITING,
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FL_ERASING,
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FL_SYNCING,
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FL_UNLOCKING,
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FL_LOCKING,
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} onenand_state_t;
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/**
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* struct onenand_bufferram - OneNAND BufferRAM Data
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* @param block block address in BufferRAM
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* @param page page address in BufferRAM
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* @param valid valid flag
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*/
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struct onenand_bufferram {
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int block;
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int page;
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int valid;
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};
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/**
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* struct onenand_chip - OneNAND Private Flash Chip Data
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* @param base [BOARDSPECIFIC] address to access OneNAND
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* @param chipsize [INTERN] the size of one chip for multichip arrays
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* @param device_id [INTERN] device ID
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* @param verstion_id [INTERN] version ID
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* @param options [BOARDSPECIFIC] various chip options. They can partly be set to inform onenand_scan about
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* @param erase_shift [INTERN] number of address bits in a block
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* @param page_shift [INTERN] number of address bits in a page
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* @param ppb_shift [INTERN] number of address bits in a pages per block
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* @param page_mask [INTERN] a page per block mask
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* @param bufferam_index [INTERN] BufferRAM index
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* @param bufferam [INTERN] BufferRAM info
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* @param readw [REPLACEABLE] hardware specific function for read short
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* @param writew [REPLACEABLE] hardware specific function for write short
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* @param command [REPLACEABLE] hardware specific function for writing commands to the chip
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* @param wait [REPLACEABLE] hardware specific function for wait on ready
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* @param read_bufferram [REPLACEABLE] hardware specific function for BufferRAM Area
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* @param write_bufferram [REPLACEABLE] hardware specific function for BufferRAM Area
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* @param chip_lock [INTERN] spinlock used to protect access to this structure and the chip
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* @param wq [INTERN] wait queue to sleep on if a OneNAND operation is in progress
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* @param state [INTERN] the current state of the OneNAND device
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* @param autooob [REPLACEABLE] the default (auto)placement scheme
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* @param priv [OPTIONAL] pointer to private chip date
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*/
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struct onenand_chip {
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void __iomem *base;
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unsigned int chipsize;
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unsigned int device_id;
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unsigned int options;
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unsigned int erase_shift;
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unsigned int page_shift;
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unsigned int ppb_shift; /* Pages per block shift */
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unsigned int page_mask;
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unsigned int bufferram_index;
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struct onenand_bufferram bufferram[MAX_BUFFERRAM];
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int (*command) (struct mtd_info * mtd, int cmd, loff_t address,
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size_t len);
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int (*wait) (struct mtd_info * mtd, int state);
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int (*read_bufferram) (struct mtd_info * mtd, int area,
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unsigned char *buffer, int offset, size_t count);
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int (*write_bufferram) (struct mtd_info * mtd, int area,
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const unsigned char *buffer, int offset,
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size_t count);
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unsigned short (*read_word) (void __iomem * addr);
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void (*write_word) (unsigned short value, void __iomem * addr);
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void (*mmcontrol) (struct mtd_info * mtd, int sync_read);
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spinlock_t chip_lock;
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wait_queue_head_t wq;
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onenand_state_t state;
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struct nand_oobinfo *autooob;
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void *bbm;
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void *priv;
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};
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#define ONENAND_CURRENT_BUFFERRAM(this) (this->bufferram_index)
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#define ONENAND_NEXT_BUFFERRAM(this) (this->bufferram_index ^ 1)
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#define ONENAND_SET_NEXT_BUFFERRAM(this) (this->bufferram_index ^= 1)
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/*
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* Options bits
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*/
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#define ONENAND_CONT_LOCK (0x0001)
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/*
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* OneNAND Flash Manufacturer ID Codes
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*/
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#define ONENAND_MFR_SAMSUNG 0xec
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#define ONENAND_MFR_UNKNOWN 0x00
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/**
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* struct nand_manufacturers - NAND Flash Manufacturer ID Structure
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* @param name: Manufacturer name
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* @param id: manufacturer ID code of device.
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*/
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struct onenand_manufacturers {
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int id;
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char *name;
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};
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#endif /* __LINUX_MTD_ONENAND_H */
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181
include/linux/mtd/onenand_regs.h
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181
include/linux/mtd/onenand_regs.h
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@@ -0,0 +1,181 @@
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/*
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* linux/include/linux/mtd/onenand_regs.h
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*
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* OneNAND Register header file
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*
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* Copyright (C) 2005-2007 Samsung Electronics
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* Kyungmin Park <kyungmin.park@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ONENAND_REG_H
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#define __ONENAND_REG_H
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/* Memory Address Map Translation (Word order) */
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#define ONENAND_MEMORY_MAP(x) ((x) << 1)
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/*
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* External BufferRAM area
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*/
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#define ONENAND_BOOTRAM ONENAND_MEMORY_MAP(0x0000)
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#define ONENAND_DATARAM ONENAND_MEMORY_MAP(0x0200)
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#define ONENAND_SPARERAM ONENAND_MEMORY_MAP(0x8010)
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/*
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* OneNAND Registers
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*/
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#define ONENAND_REG_MANUFACTURER_ID ONENAND_MEMORY_MAP(0xF000)
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#define ONENAND_REG_DEVICE_ID ONENAND_MEMORY_MAP(0xF001)
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#define ONENAND_REG_VERSION_ID ONENAND_MEMORY_MAP(0xF002)
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#define ONENAND_REG_DATA_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF003)
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#define ONENAND_REG_BOOT_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF004)
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#define ONENAND_REG_NUM_BUFFERS ONENAND_MEMORY_MAP(0xF005)
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#define ONENAND_REG_TECHNOLOGY ONENAND_MEMORY_MAP(0xF006)
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#define ONENAND_REG_START_ADDRESS1 ONENAND_MEMORY_MAP(0xF100)
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#define ONENAND_REG_START_ADDRESS2 ONENAND_MEMORY_MAP(0xF101)
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#define ONENAND_REG_START_ADDRESS3 ONENAND_MEMORY_MAP(0xF102)
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#define ONENAND_REG_START_ADDRESS4 ONENAND_MEMORY_MAP(0xF103)
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#define ONENAND_REG_START_ADDRESS5 ONENAND_MEMORY_MAP(0xF104)
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#define ONENAND_REG_START_ADDRESS6 ONENAND_MEMORY_MAP(0xF105)
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#define ONENAND_REG_START_ADDRESS7 ONENAND_MEMORY_MAP(0xF106)
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#define ONENAND_REG_START_ADDRESS8 ONENAND_MEMORY_MAP(0xF107)
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#define ONENAND_REG_START_BUFFER ONENAND_MEMORY_MAP(0xF200)
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#define ONENAND_REG_COMMAND ONENAND_MEMORY_MAP(0xF220)
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#define ONENAND_REG_SYS_CFG1 ONENAND_MEMORY_MAP(0xF221)
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#define ONENAND_REG_SYS_CFG2 ONENAND_MEMORY_MAP(0xF222)
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#define ONENAND_REG_CTRL_STATUS ONENAND_MEMORY_MAP(0xF240)
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#define ONENAND_REG_INTERRUPT ONENAND_MEMORY_MAP(0xF241)
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#define ONENAND_REG_START_BLOCK_ADDRESS ONENAND_MEMORY_MAP(0xF24C)
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#define ONENAND_REG_END_BLOCK_ADDRESS ONENAND_MEMORY_MAP(0xF24D)
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#define ONENAND_REG_WP_STATUS ONENAND_MEMORY_MAP(0xF24E)
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#define ONENAND_REG_ECC_STATUS ONENAND_MEMORY_MAP(0xFF00)
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#define ONENAND_REG_ECC_M0 ONENAND_MEMORY_MAP(0xFF01)
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#define ONENAND_REG_ECC_S0 ONENAND_MEMORY_MAP(0xFF02)
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#define ONENAND_REG_ECC_M1 ONENAND_MEMORY_MAP(0xFF03)
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#define ONENAND_REG_ECC_S1 ONENAND_MEMORY_MAP(0xFF04)
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#define ONENAND_REG_ECC_M2 ONENAND_MEMORY_MAP(0xFF05)
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#define ONENAND_REG_ECC_S2 ONENAND_MEMORY_MAP(0xFF06)
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#define ONENAND_REG_ECC_M3 ONENAND_MEMORY_MAP(0xFF07)
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#define ONENAND_REG_ECC_S3 ONENAND_MEMORY_MAP(0xFF08)
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/*
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* Device ID Register F001h (R)
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*/
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#define ONENAND_DEVICE_DENSITY_SHIFT (4)
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#define ONENAND_DEVICE_IS_DDP (1 << 3)
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#define ONENAND_DEVICE_IS_DEMUX (1 << 2)
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#define ONENAND_DEVICE_VCC_MASK (0x3)
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#define ONENAND_DEVICE_DENSITY_512Mb (0x002)
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/*
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* Version ID Register F002h (R)
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*/
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#define ONENAND_VERSION_PROCESS_SHIFT (8)
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/*
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* Start Address 1 F100h (R/W)
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*/
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#define ONENAND_DDP_SHIFT (15)
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/*
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* Start Address 8 F107h (R/W)
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*/
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#define ONENAND_FPA_MASK (0x3f)
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#define ONENAND_FPA_SHIFT (2)
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#define ONENAND_FSA_MASK (0x03)
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/*
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* Start Buffer Register F200h (R/W)
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*/
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#define ONENAND_BSA_MASK (0x03)
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#define ONENAND_BSA_SHIFT (8)
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#define ONENAND_BSA_BOOTRAM (0 << 2)
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#define ONENAND_BSA_DATARAM0 (2 << 2)
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#define ONENAND_BSA_DATARAM1 (3 << 2)
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#define ONENAND_BSC_MASK (0x03)
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/*
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* Command Register F220h (R/W)
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*/
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#define ONENAND_CMD_READ (0x00)
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#define ONENAND_CMD_READOOB (0x13)
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#define ONENAND_CMD_PROG (0x80)
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#define ONENAND_CMD_PROGOOB (0x1A)
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#define ONENAND_CMD_UNLOCK (0x23)
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#define ONENAND_CMD_LOCK (0x2A)
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#define ONENAND_CMD_LOCK_TIGHT (0x2C)
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#define ONENAND_CMD_ERASE (0x94)
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#define ONENAND_CMD_RESET (0xF0)
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#define ONENAND_CMD_READID (0x90)
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/* NOTE: Those are not *REAL* commands */
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#define ONENAND_CMD_BUFFERRAM (0x1978)
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/*
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* System Configuration 1 Register F221h (R, R/W)
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*/
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#define ONENAND_SYS_CFG1_SYNC_READ (1 << 15)
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#define ONENAND_SYS_CFG1_BRL_7 (7 << 12)
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#define ONENAND_SYS_CFG1_BRL_6 (6 << 12)
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#define ONENAND_SYS_CFG1_BRL_5 (5 << 12)
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#define ONENAND_SYS_CFG1_BRL_4 (4 << 12)
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#define ONENAND_SYS_CFG1_BRL_3 (3 << 12)
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#define ONENAND_SYS_CFG1_BRL_10 (2 << 12)
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#define ONENAND_SYS_CFG1_BRL_9 (1 << 12)
|
||||
#define ONENAND_SYS_CFG1_BRL_8 (0 << 12)
|
||||
#define ONENAND_SYS_CFG1_BRL_SHIFT (12)
|
||||
#define ONENAND_SYS_CFG1_BL_32 (4 << 9)
|
||||
#define ONENAND_SYS_CFG1_BL_16 (3 << 9)
|
||||
#define ONENAND_SYS_CFG1_BL_8 (2 << 9)
|
||||
#define ONENAND_SYS_CFG1_BL_4 (1 << 9)
|
||||
#define ONENAND_SYS_CFG1_BL_CONT (0 << 9)
|
||||
#define ONENAND_SYS_CFG1_BL_SHIFT (9)
|
||||
#define ONENAND_SYS_CFG1_NO_ECC (1 << 8)
|
||||
#define ONENAND_SYS_CFG1_RDY (1 << 7)
|
||||
#define ONENAND_SYS_CFG1_INT (1 << 6)
|
||||
#define ONENAND_SYS_CFG1_IOBE (1 << 5)
|
||||
#define ONENAND_SYS_CFG1_RDY_CONF (1 << 4)
|
||||
|
||||
/*
|
||||
* Controller Status Register F240h (R)
|
||||
*/
|
||||
#define ONENAND_CTRL_ONGO (1 << 15)
|
||||
#define ONENAND_CTRL_LOCK (1 << 14)
|
||||
#define ONENAND_CTRL_LOAD (1 << 13)
|
||||
#define ONENAND_CTRL_PROGRAM (1 << 12)
|
||||
#define ONENAND_CTRL_ERASE (1 << 11)
|
||||
#define ONENAND_CTRL_ERROR (1 << 10)
|
||||
#define ONENAND_CTRL_RSTB (1 << 7)
|
||||
|
||||
/*
|
||||
* Interrupt Status Register F241h (R)
|
||||
*/
|
||||
#define ONENAND_INT_MASTER (1 << 15)
|
||||
#define ONENAND_INT_READ (1 << 7)
|
||||
#define ONENAND_INT_WRITE (1 << 6)
|
||||
#define ONENAND_INT_ERASE (1 << 5)
|
||||
#define ONENAND_INT_RESET (1 << 4)
|
||||
#define ONENAND_INT_CLEAR (0 << 0)
|
||||
|
||||
/*
|
||||
* NAND Flash Write Protection Status Register F24Eh (R)
|
||||
*/
|
||||
#define ONENAND_WP_US (1 << 2)
|
||||
#define ONENAND_WP_LS (1 << 1)
|
||||
#define ONENAND_WP_LTS (1 << 0)
|
||||
|
||||
/*
|
||||
* ECC Status Reigser FF00h (R)
|
||||
*/
|
||||
#define ONENAND_ECC_1BIT (1 << 0)
|
||||
#define ONENAND_ECC_2BIT (1 << 1)
|
||||
#define ONENAND_ECC_2BIT_ALL (0xAAAA)
|
||||
|
||||
#endif /* __ONENAND_REG_H */
|
||||
Reference in New Issue
Block a user