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https://github.com/frank-w/u-boot.git
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armv7: rename cache related CONFIG flags
Replace the cache related CONFIG flags with more meaningful names. Following are the changes: CONFIG_L2_OFF -> CONFIG_SYS_L2CACHE_OFF CONFIG_SYS_NO_ICACHE -> CONFIG_SYS_ICACHE_OFF CONFIG_SYS_NO_DCACHE -> CONFIG_SYS_DCACHE_OFF Signed-off-by: Aneesh V <aneesh@ti.com> V2: * Changed CONFIG_L2_OFF -> CONFIG_SYS_NO_L2CACHE V4: * Changed all three flags to the final names suggested as above and accordingly changed the commit message
This commit is contained in:
@@ -38,7 +38,8 @@
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#define CONFIG_B2 1 /* on an B2 Board */
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#define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */
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#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
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#define CONFIG_SYS_NO_CP15_CACHE
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#define CONFIG_SYS_ICACHE_OFF
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#define CONFIG_SYS_DCACHE_OFF
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_S3C44B0_CLOCK_SPEED 75 /* we have a 75Mhz S3C44B0*/
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@@ -38,7 +38,7 @@
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#undef CONFIG_USE_IRQ
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_NO_DCACHE
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#define CONFIG_SYS_DCACHE_OFF
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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@@ -41,7 +41,7 @@
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_L2_OFF 1
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#define CONFIG_SYS_L2CACHE_OFF 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_OF_LIBFDT 1
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@@ -43,7 +43,7 @@
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_NO_DCACHE
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#define CONFIG_SYS_DCACHE_OFF
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/*
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* Size of malloc() pool
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@@ -38,7 +38,7 @@
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_NO_DCACHE
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#define CONFIG_SYS_DCACHE_OFF
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#define CONFIG_SYS_TEXT_BASE 0x0
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/*
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* Size of malloc() pool
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@@ -44,7 +44,7 @@
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/* for timer/console/ethernet */
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_NO_DCACHE
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#define CONFIG_SYS_DCACHE_OFF
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#define CONFIG_SYS_TEXT_BASE 0x0
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/*
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* Hardware drivers
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@@ -42,7 +42,7 @@
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_NO_DCACHE
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#define CONFIG_SYS_DCACHE_OFF
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/*
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* Size of malloc() pool
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@@ -38,7 +38,7 @@
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_L2_OFF
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#define CONFIG_SYS_L2CACHE_OFF
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/*
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* Bootloader Components Configuration
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@@ -43,7 +43,8 @@
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#define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */
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#define CONFIG_S3C4510B 1 /* it's a S3C4510B chip */
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#define CONFIG_EVB4510 1 /* on an EVB4510 Board */
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#define CONFIG_SYS_NO_CP15_CACHE
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#define CONFIG_SYS_ICACHE_OFF
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#define CONFIG_SYS_DCACHE_OFF
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#define CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4*1024)
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@@ -49,7 +49,7 @@
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_NO_DCACHE
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#define CONFIG_SYS_DCACHE_OFF
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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@@ -43,7 +43,7 @@
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#define CONFIG_SYS_TEXT_BASE 0x0
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_NO_DCACHE
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#define CONFIG_SYS_DCACHE_OFF
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/*
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* Hardware drivers
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@@ -32,7 +32,7 @@
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#define CONFIG_SYS_TEXT_BASE 0xC1F00000
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_NO_DCACHE
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#define CONFIG_SYS_DCACHE_OFF
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#undef CONFIG_USE_IRQ
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/* Console setting */
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@@ -36,7 +36,7 @@
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_NO_DCACHE
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#define CONFIG_SYS_DCACHE_OFF
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/*
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* Size of malloc() pool
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@@ -47,7 +47,7 @@
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_NO_DCACHE
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#define CONFIG_SYS_DCACHE_OFF
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/*
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* Size of malloc() pool
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@@ -35,7 +35,7 @@
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#define CONFIG_SYS_TEXT_BASE 0x97800000
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#define CONFIG_L2_OFF
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#define CONFIG_SYS_L2CACHE_OFF
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#include <asm/arch/imx-regs.h>
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/*
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@@ -29,7 +29,7 @@
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_L2_OFF
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#define CONFIG_SYS_L2CACHE_OFF
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#include <asm/arch/imx-regs.h>
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@@ -46,7 +46,7 @@
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#define CONFIG_DISPLAY_BOARDINFO 1
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/* Keep L2 Cache Disabled */
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#define CONFIG_L2_OFF 1
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#define CONFIG_SYS_L2CACHE_OFF 1
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/* Clock Defines */
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#define V_OSCK 38400000 /* Clock output from T2 */
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@@ -47,7 +47,7 @@
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#define CONFIG_DISPLAY_BOARDINFO 1
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/* Keep L2 Cache Disabled */
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#define CONFIG_L2_OFF 1
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#define CONFIG_SYS_L2CACHE_OFF 1
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/* Clock Defines */
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#define V_OSCK 38400000 /* Clock output from T2 */
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@@ -44,7 +44,7 @@
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_NO_DCACHE
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#define CONFIG_SYS_DCACHE_OFF
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/*
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* Size of malloc() pool
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@@ -69,7 +69,7 @@
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_NO_DCACHE
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#define CONFIG_SYS_DCACHE_OFF
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/*
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* Size of malloc() pool
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@@ -43,7 +43,7 @@
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#define CONFIG_DISPLAY_BOARDINFO
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/* Keep L2 Cache Disabled */
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#define CONFIG_L2_OFF 1
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#define CONFIG_SYS_L2CACHE_OFF 1
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define CONFIG_SYS_TEXT_BASE 0x44800000
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@@ -44,7 +44,7 @@
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_NO_DCACHE
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#define CONFIG_SYS_DCACHE_OFF
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/*
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* Size of malloc() pool
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@@ -31,7 +31,7 @@
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#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
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#define CONFIG_TEGRA2 /* in a NVidia Tegra2 core */
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#define CONFIG_MACH_TEGRA_GENERIC /* which is a Tegra generic machine */
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#define CONFIG_L2_OFF /* No L2 cache */
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#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
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#define CONFIG_ENABLE_CORTEXA9 /* enable CPU (A9 complex) */
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@@ -49,7 +49,7 @@
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_NO_DCACHE
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#define CONFIG_SYS_DCACHE_OFF
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#define RTC
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@@ -26,7 +26,7 @@
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#define CONFIG_MX51 /* in a mx51 */
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#define CONFIG_L2_OFF
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#define CONFIG_SYS_L2CACHE_OFF
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#define CONFIG_SYS_TEXT_BASE 0x97800000
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#include <asm/arch/imx-regs.h>
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@@ -51,7 +51,7 @@
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_NO_DCACHE
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#define CONFIG_SYS_DCACHE_OFF
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/*
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* select serial console configuration
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@@ -38,7 +38,7 @@
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#define CONFIG_SYS_TEXT_BASE 0x0
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_NO_DCACHE
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#define CONFIG_SYS_DCACHE_OFF
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/*
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* Size of malloc() pool; this lives below the uppermost 128 KiB which are
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@@ -48,7 +48,7 @@
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_NO_DCACHE
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#define CONFIG_SYS_DCACHE_OFF
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/*
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* Size of malloc() pool
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