armv7: rename cache related CONFIG flags

Replace the cache related CONFIG flags with more meaningful
names. Following are the changes:

CONFIG_L2_OFF	     -> CONFIG_SYS_L2CACHE_OFF
CONFIG_SYS_NO_ICACHE -> CONFIG_SYS_ICACHE_OFF
CONFIG_SYS_NO_DCACHE -> CONFIG_SYS_DCACHE_OFF

Signed-off-by: Aneesh V <aneesh@ti.com>
V2:
 * Changed CONFIG_L2_OFF -> CONFIG_SYS_NO_L2CACHE
V4:
 * Changed all three flags to the final names suggested as above
   and accordingly changed the commit message
This commit is contained in:
Aneesh V
2011-06-16 23:30:48 +00:00
committed by Albert ARIBAUD
parent 2c451f7831
commit e47f2db537
36 changed files with 42 additions and 45 deletions

View File

@@ -38,7 +38,8 @@
#define CONFIG_B2 1 /* on an B2 Board */
#define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */
#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
#define CONFIG_SYS_NO_CP15_CACHE
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_S3C44B0_CLOCK_SPEED 75 /* we have a 75Mhz S3C44B0*/

View File

@@ -38,7 +38,7 @@
#undef CONFIG_USE_IRQ
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1

View File

@@ -41,7 +41,7 @@
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_L2_OFF 1
#define CONFIG_SYS_L2CACHE_OFF 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_OF_LIBFDT 1

View File

@@ -43,7 +43,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool

View File

@@ -38,7 +38,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_TEXT_BASE 0x0
/*
* Size of malloc() pool

View File

@@ -44,7 +44,7 @@
/* for timer/console/ethernet */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_TEXT_BASE 0x0
/*
* Hardware drivers

View File

@@ -42,7 +42,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool

View File

@@ -38,7 +38,7 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_L2_OFF
#define CONFIG_SYS_L2CACHE_OFF
/*
* Bootloader Components Configuration

View File

@@ -43,7 +43,8 @@
#define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */
#define CONFIG_S3C4510B 1 /* it's a S3C4510B chip */
#define CONFIG_EVB4510 1 /* on an EVB4510 Board */
#define CONFIG_SYS_NO_CP15_CACHE
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024)

View File

@@ -49,7 +49,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1

View File

@@ -43,7 +43,7 @@
#define CONFIG_SYS_TEXT_BASE 0x0
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
/*
* Hardware drivers

View File

@@ -32,7 +32,7 @@
#define CONFIG_SYS_TEXT_BASE 0xC1F00000
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
#undef CONFIG_USE_IRQ
/* Console setting */

View File

@@ -36,7 +36,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool

View File

@@ -47,7 +47,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool

View File

@@ -35,7 +35,7 @@
#define CONFIG_SYS_TEXT_BASE 0x97800000
#define CONFIG_L2_OFF
#define CONFIG_SYS_L2CACHE_OFF
#include <asm/arch/imx-regs.h>
/*

View File

@@ -29,7 +29,7 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_L2_OFF
#define CONFIG_SYS_L2CACHE_OFF
#include <asm/arch/imx-regs.h>

View File

@@ -46,7 +46,7 @@
#define CONFIG_DISPLAY_BOARDINFO 1
/* Keep L2 Cache Disabled */
#define CONFIG_L2_OFF 1
#define CONFIG_SYS_L2CACHE_OFF 1
/* Clock Defines */
#define V_OSCK 38400000 /* Clock output from T2 */

View File

@@ -47,7 +47,7 @@
#define CONFIG_DISPLAY_BOARDINFO 1
/* Keep L2 Cache Disabled */
#define CONFIG_L2_OFF 1
#define CONFIG_SYS_L2CACHE_OFF 1
/* Clock Defines */
#define V_OSCK 38400000 /* Clock output from T2 */

View File

@@ -44,7 +44,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool

View File

@@ -69,7 +69,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool

View File

@@ -43,7 +43,7 @@
#define CONFIG_DISPLAY_BOARDINFO
/* Keep L2 Cache Disabled */
#define CONFIG_L2_OFF 1
#define CONFIG_SYS_L2CACHE_OFF 1
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_TEXT_BASE 0x44800000

View File

@@ -44,7 +44,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool

View File

@@ -31,7 +31,7 @@
#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
#define CONFIG_TEGRA2 /* in a NVidia Tegra2 core */
#define CONFIG_MACH_TEGRA_GENERIC /* which is a Tegra generic machine */
#define CONFIG_L2_OFF /* No L2 cache */
#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
#define CONFIG_ENABLE_CORTEXA9 /* enable CPU (A9 complex) */

View File

@@ -49,7 +49,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
#define RTC

View File

@@ -26,7 +26,7 @@
#define CONFIG_MX51 /* in a mx51 */
#define CONFIG_L2_OFF
#define CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_TEXT_BASE 0x97800000
#include <asm/arch/imx-regs.h>

View File

@@ -51,7 +51,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
/*
* select serial console configuration

View File

@@ -38,7 +38,7 @@
#define CONFIG_SYS_TEXT_BASE 0x0
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool; this lives below the uppermost 128 KiB which are

View File

@@ -48,7 +48,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool