2017-12-21 07:45:38 +08:00
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/*
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2019-01-29 01:12:39 +08:00
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* Copyright (C) 2017-2019 Intel Corporation
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2017-12-21 07:45:38 +08:00
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*
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2018-09-18 15:11:08 +08:00
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* SPDX-License-Identifier: MIT
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2017-12-21 07:45:38 +08:00
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*
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*/
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#pragma once
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#include <cstddef>
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2019-02-27 18:39:32 +08:00
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#include <cstdint>
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2018-09-29 05:36:11 +08:00
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#include <limits>
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2017-12-21 07:45:38 +08:00
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2018-09-27 21:08:57 +08:00
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constexpr bool is32bit = (sizeof(void *) == 4);
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constexpr bool is64bit = (sizeof(void *) == 8);
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2019-01-29 01:12:39 +08:00
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template <uint8_t N>
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constexpr uint64_t maxNBitValue = ((1ULL << N) - 1);
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static_assert(maxNBitValue<8> == std::numeric_limits<uint8_t>::max(), "");
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static_assert(maxNBitValue<16> == std::numeric_limits<uint16_t>::max(), "");
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static_assert(maxNBitValue<32> == std::numeric_limits<uint32_t>::max(), "");
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2017-12-21 07:45:38 +08:00
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namespace MemoryConstants {
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static const uint64_t zoneHigh = ~(uint64_t)0xFFFFFFFF;
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static const uint64_t kiloByte = 1024;
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static const uint64_t kiloByteShiftSize = 10;
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static const uint64_t megaByte = 1024 * kiloByte;
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static const uint64_t gigaByte = 1024 * megaByte;
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static const size_t minBufferAlignment = 4;
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static const size_t cacheLineSize = 64;
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static const size_t pageSize = 4 * kiloByte;
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static const size_t pageSize64k = 64 * kiloByte;
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static const size_t preferredAlignment = pageSize; // alignment preferred for performance reasons, i.e. internal allocations
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static const size_t allocationAlignment = pageSize; // alignment required to gratify incoming pointer, i.e. passed host_ptr
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static const size_t slmWindowAlignment = 128 * kiloByte;
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static const size_t slmWindowSize = 64 * kiloByte;
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static const uintptr_t pageMask = (pageSize - 1);
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2017-12-28 18:25:43 +08:00
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static const uintptr_t page64kMask = (pageSize64k - 1);
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2019-01-29 01:12:39 +08:00
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static const uint64_t max32BitAppAddress = maxNBitValue<31>;
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static const uint64_t max64BitAppAddress = maxNBitValue<47>;
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2018-03-27 18:55:20 +08:00
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static const uint32_t sizeOf4GBinPageEntities = (MemoryConstants::gigaByte * 4 - MemoryConstants::pageSize) / MemoryConstants::pageSize;
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2019-01-29 01:12:39 +08:00
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static const uint64_t max32BitAddress = maxNBitValue<32>;
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2019-01-10 22:36:57 +08:00
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static const uint64_t max36BitAddress = ((1ULL << 36) - 1);
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2019-01-29 01:12:39 +08:00
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static const uint64_t max48BitAddress = maxNBitValue<48>;
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2018-09-29 05:36:11 +08:00
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static const uintptr_t page4kEntryMask = std::numeric_limits<uintptr_t>::max() & ~MemoryConstants::pageMask;
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static const uintptr_t page64kEntryMask = std::numeric_limits<uintptr_t>::max() & ~MemoryConstants::page64kMask;
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2018-09-27 21:08:57 +08:00
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static const int GfxAddressBits = is64bit ? 48 : 32;
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2019-03-18 17:06:01 +08:00
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static const uint64_t maxSvmAddress = is64bit ? maxNBitValue<47> : maxNBitValue<32>;
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2019-04-03 21:59:31 +08:00
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2018-06-13 03:54:39 +08:00
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} // namespace MemoryConstants
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2019-04-03 21:59:31 +08:00
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namespace BlitterConstants {
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2019-05-09 16:56:25 +08:00
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static constexpr uint64_t maxBlitWidth = 0x7FC0; // 0x7FFF aligned to cacheline size
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2019-04-03 21:59:31 +08:00
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static constexpr uint64_t maxBlitHeight = 0x7FFF;
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2019-05-16 23:48:29 +08:00
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enum class BlitWithHostPtrDirection {
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ToHostPtr,
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FromHostPtr
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};
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2019-04-03 21:59:31 +08:00
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} // namespace BlitterConstants
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