2017-12-21 07:45:38 +08:00
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/*
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2019-02-18 20:43:10 +08:00
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* Copyright (C) 2018-2019 Intel Corporation
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2017-12-21 07:45:38 +08:00
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*
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2018-09-18 15:11:08 +08:00
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* SPDX-License-Identifier: MIT
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2017-12-21 07:45:38 +08:00
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*
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*/
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#include "runtime/command_stream/thread_arbitration_policy.h"
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2019-02-27 18:39:32 +08:00
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#include "runtime/gen8/reg_configs.h"
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2017-12-21 07:45:38 +08:00
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#include "runtime/helpers/options.h"
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#include "runtime/helpers/preamble.h"
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#include "unit_tests/fixtures/platform_fixture.h"
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2019-02-27 18:39:32 +08:00
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#include "unit_tests/preamble/preamble_fixture.h"
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2017-12-21 07:45:38 +08:00
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2019-03-26 18:59:46 +08:00
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using namespace NEO;
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2017-12-21 07:45:38 +08:00
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typedef PreambleFixture BdwSlm;
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BDWTEST_F(BdwSlm, shouldBeEnabledOnGen8) {
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typedef BDWFamily::MI_LOAD_REGISTER_IMM MI_LOAD_REGISTER_IMM;
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LinearStream &cs = linearStream;
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uint32_t l3Config = PreambleHelper<BDWFamily>::getL3Config(**platformDevices, true);
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PreambleHelper<BDWFamily>::programL3(&cs, l3Config);
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parseCommands<BDWFamily>(cs);
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auto itorLRI = find<MI_LOAD_REGISTER_IMM *>(cmdList.begin(), cmdList.end());
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ASSERT_NE(cmdList.end(), itorLRI);
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const auto &lri = *reinterpret_cast<MI_LOAD_REGISTER_IMM *>(*itorLRI);
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auto RegisterOffset = L3CNTLRegisterOffset<BDWFamily>::registerOffset;
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EXPECT_EQ(RegisterOffset, lri.getRegisterOffset());
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EXPECT_EQ(1u, lri.getDataDword() & 1);
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}
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typedef PreambleFixture Gen8L3Config;
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BDWTEST_F(Gen8L3Config, checkNoSLM) {
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bool slmUsed = false;
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uint32_t l3Config = 0;
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l3Config = getL3ConfigHelper<IGFX_BROADWELL>(slmUsed);
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2019-02-18 20:43:10 +08:00
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EXPECT_EQ(0x80000340u, l3Config);
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uint32_t errorDetectionBehaviorControlBit = 1 << 9;
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EXPECT_TRUE((l3Config & errorDetectionBehaviorControlBit) != 0);
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2017-12-21 07:45:38 +08:00
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}
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BDWTEST_F(Gen8L3Config, checkSLM) {
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bool slmUsed = true;
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uint32_t l3Config = 0;
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l3Config = getL3ConfigHelper<IGFX_BROADWELL>(slmUsed);
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EXPECT_EQ(0x60000321u, l3Config);
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uint32_t errorDetectionBehaviorControlBit = 1 << 9;
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EXPECT_TRUE((l3Config & errorDetectionBehaviorControlBit) != 0);
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2017-12-21 07:45:38 +08:00
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}
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typedef PreambleFixture ThreadArbitrationGen8;
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2018-02-20 15:11:24 +08:00
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BDWTEST_F(ThreadArbitrationGen8, givenPolicyWhenThreadArbitrationProgrammedThenDoNothing) {
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2017-12-21 07:45:38 +08:00
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typedef BDWFamily::MI_LOAD_REGISTER_IMM MI_LOAD_REGISTER_IMM;
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LinearStream &cs = linearStream;
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2018-02-20 15:11:24 +08:00
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PreambleHelper<BDWFamily>::programThreadArbitration(&cs, ThreadArbitrationPolicy::RoundRobin);
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2017-12-21 07:45:38 +08:00
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2018-02-20 15:11:24 +08:00
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EXPECT_EQ(0u, cs.getUsed());
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2017-12-21 07:45:38 +08:00
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2018-01-08 22:58:02 +08:00
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EXPECT_EQ(0u, PreambleHelper<BDWFamily>::getAdditionalCommandsSize(MockDevice(**platformDevices)));
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2018-04-20 19:55:54 +08:00
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EXPECT_EQ(0u, PreambleHelper<BDWFamily>::getThreadArbitrationCommandsSize());
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EXPECT_EQ(0u, PreambleHelper<BDWFamily>::getDefaultThreadArbitrationPolicy());
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}
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typedef PreambleFixture Gen8UrbEntryAllocationSize;
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BDWTEST_F(Gen8UrbEntryAllocationSize, getUrbEntryAllocationSize) {
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uint32_t actualVal = PreambleHelper<FamilyType>::getUrbEntryAllocationSize();
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EXPECT_EQ(0x782u, actualVal);
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}
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BDWTEST_F(PreambleVfeState, basic) {
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typedef BDWFamily::PIPE_CONTROL PIPE_CONTROL;
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LinearStream &cs = linearStream;
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PreambleHelper<BDWFamily>::programVFEState(&linearStream, **platformDevices, 0, 0);
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parseCommands<BDWFamily>(cs);
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auto itorPC = find<PIPE_CONTROL *>(cmdList.begin(), cmdList.end());
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ASSERT_NE(cmdList.end(), itorPC);
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const auto &pc = *reinterpret_cast<PIPE_CONTROL *>(*itorPC);
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EXPECT_TRUE(pc.getDcFlushEnable());
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EXPECT_EQ(1u, pc.getCommandStreamerStallEnable());
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}
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