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fix: align indirect data pointer to cacheline size in heapless mode 

Align indirect data pointer to cacheline size in heapless mode,
restore debug_break_if if avx2 load/store operation
gets unaligned pointer,
remove fallback to mm256 loadu/storeu unaligned operation

Related-To: NEO-7621
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
This commit is contained in:
Kamil Kopryk 2024-02-13 18:25:17 +00:00 committed by Compute-Runtime-Automation
parent 5120ec2f93
commit 004e6e647f
2 changed files with 7 additions and 11 deletions
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4
opencl/source/helpers/hardware_commands_helper_xehp_and_later.inl
View File

@ -63,7 +63,9 @@ size_t HardwareCommandsHelper<GfxFamily>::sendCrossThreadData(
constexpr bool heaplessModeEnabled = GfxFamily::template isHeaplessMode<WalkerType>();
if constexpr (heaplessModeEnabled == false) {
if constexpr (heaplessModeEnabled) {
indirectHeap.align(MemoryConstants::cacheLineSize);
} else {
indirectHeap.align(WalkerType::INDIRECTDATASTARTADDRESS_ALIGN_SIZE);
}

14
shared/source/helpers/uint16_avx2.h
View File

@ -53,11 +53,8 @@ struct uint16x16_t { // NOLINT(readability-identifier-naming)
}
inline void load(const void *alignedPtr) {
if (isAligned<32>(alignedPtr)) {
value = _mm256_load_si256(reinterpret_cast<const __m256i *>(alignedPtr)); // AVX
} else {
loadUnaligned(alignedPtr);
}
DEBUG_BREAK_IF(!isAligned<32>(alignedPtr));
value = _mm256_load_si256(reinterpret_cast<const __m256i *>(alignedPtr)); // AVX
}
inline void loadUnaligned(const void *ptr) {
@ -65,11 +62,8 @@ struct uint16x16_t { // NOLINT(readability-identifier-naming)
}
inline void store(void *alignedPtr) {
if (isAligned<32>(alignedPtr)) {
_mm256_store_si256(reinterpret_cast<__m256i *>(alignedPtr), value); // AVX
} else {
storeUnaligned(alignedPtr);
}
DEBUG_BREAK_IF(!isAligned<32>(alignedPtr));
_mm256_store_si256(reinterpret_cast<__m256i *>(alignedPtr), value); // AVX
}
inline void storeUnaligned(void *ptr) {