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Update RENDER_SURFACE_STATE for Xe Hpc

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For Xe Hp and later rename RSS tile mode enum from YMAJOR to TILE4

Related-To: NEO-6466
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
This commit is contained in:
Mateusz Jablonski
2022-01-21 12:14:46 +00:00
committed by Compute-Runtime-Automation
parent e3792491a3
commit 0c933d83af
8 changed files with 113 additions and 113 deletions
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2
shared/source/generated/xe_hp_core/hw_cmds_generated_xe_hp_core.inl
View File

@@ -1344,7 +1344,7 @@ typedef struct tagRENDER_SURFACE_STATE {
TILE_MODE_LINEAR = 0x0,
TILE_MODE_TILE64 = 0x1,
TILE_MODE_XMAJOR = 0x2,
TILE_MODE_YMAJOR = 0x3, // patched - old name for TILE_MODE_TILE4
TILE_MODE_TILE4 = 0x3,
} TILE_MODE;
typedef enum tagSURFACE_HORIZONTAL_ALIGNMENT {
SURFACE_HORIZONTAL_ALIGNMENT_HALIGN_16 = 0x0,

187
shared/source/generated/xe_hpc_core/hw_cmds_generated_xe_hpc_core.inl
View File

@@ -1422,7 +1422,7 @@ typedef struct tagRENDER_SURFACE_STATE {
uint32_t SurfaceHorizontalAlignment : BITFIELD_RANGE(14, 15);
uint32_t SurfaceVerticalAlignment : BITFIELD_RANGE(16, 17);
uint32_t SurfaceFormat : BITFIELD_RANGE(18, 26);
uint32_t AstcEnable : BITFIELD_RANGE(27, 27);
uint32_t Reserved_27 : BITFIELD_RANGE(27, 27);
uint32_t SurfaceArray : BITFIELD_RANGE(28, 28);
uint32_t SurfaceType : BITFIELD_RANGE(29, 31);
// DWORD 1
@@ -1432,7 +1432,7 @@ typedef struct tagRENDER_SURFACE_STATE {
uint32_t DoubleFetchDisable : BITFIELD_RANGE(17, 17);
uint32_t CornerTexelMode : BITFIELD_RANGE(18, 18);
uint32_t BaseMipLevel : BITFIELD_RANGE(19, 23);
uint32_t MemoryObjectControlStateReserved_56 : BITFIELD_RANGE(24, 24);
uint32_t MemoryObjectControlStateEncryptedData : BITFIELD_RANGE(24, 24);
uint32_t MemoryObjectControlStateIndexToMocsTables : BITFIELD_RANGE(25, 30);
uint32_t Reserved_63 : BITFIELD_RANGE(31, 31);
// DWORD 2
@@ -1443,8 +1443,7 @@ typedef struct tagRENDER_SURFACE_STATE {
uint32_t DepthStencilResource : BITFIELD_RANGE(31, 31);
// DWORD 3
uint32_t SurfacePitch : BITFIELD_RANGE(0, 17);
uint32_t NullProbingEnable : BITFIELD_RANGE(18, 18);
uint32_t Reserved_115 : BITFIELD_RANGE(19, 20);
uint32_t Reserved_114 : BITFIELD_RANGE(18, 20);
uint32_t Depth : BITFIELD_RANGE(21, 31);
// DWORD 4
uint32_t MultisamplePositionPaletteIndex : BITFIELD_RANGE(0, 2);
@@ -1453,14 +1452,14 @@ typedef struct tagRENDER_SURFACE_STATE {
uint32_t RenderTargetViewExtent : BITFIELD_RANGE(7, 17);
uint32_t MinimumArrayElement : BITFIELD_RANGE(18, 28);
uint32_t RenderTargetAndSampleUnormRotation : BITFIELD_RANGE(29, 30);
uint32_t Reserved_159 : BITFIELD_RANGE(31, 31);
uint32_t DecompressInL3 : BITFIELD_RANGE(31, 31);
// DWORD 5
uint32_t MipCountLod : BITFIELD_RANGE(0, 3);
uint32_t SurfaceMinLod : BITFIELD_RANGE(4, 7);
uint32_t MipTailStartLod : BITFIELD_RANGE(8, 11);
uint32_t Reserved_172 : BITFIELD_RANGE(12, 13);
uint32_t CoherencyType : BITFIELD_RANGE(14, 15);
uint32_t L1CachePolicyL1CacheControl : BITFIELD_RANGE(16, 18);
uint32_t L1CacheControlCachePolicy : BITFIELD_RANGE(16, 18);
uint32_t Reserved_179 : BITFIELD_RANGE(19, 19);
uint32_t EwaDisableForCube : BITFIELD_RANGE(20, 20);
uint32_t YOffset : BITFIELD_RANGE(21, 23);
@@ -1472,9 +1471,7 @@ typedef struct tagRENDER_SURFACE_STATE {
uint32_t Reserved_208 : BITFIELD_RANGE(16, 31);
// DWORD 7
uint32_t ResourceMinLod : BITFIELD_RANGE(0, 11);
uint32_t Reserved_236 : BITFIELD_RANGE(12, 13);
uint32_t DisableSupportForMultiGpuAtomics : BITFIELD_RANGE(14, 14);
uint32_t DisableSupportForMultiGpuPartialWrites : BITFIELD_RANGE(15, 15);
uint32_t Reserved_236 : BITFIELD_RANGE(12, 15);
uint32_t ShaderChannelSelectAlpha : BITFIELD_RANGE(16, 18);
uint32_t ShaderChannelSelectBlue : BITFIELD_RANGE(19, 21);
uint32_t ShaderChannelSelectGreen : BITFIELD_RANGE(22, 24);
@@ -1482,9 +1479,9 @@ typedef struct tagRENDER_SURFACE_STATE {
uint32_t Reserved_252 : BITFIELD_RANGE(28, 29);
uint32_t MemoryCompressionEnable : BITFIELD_RANGE(30, 30);
uint32_t MemoryCompressionMode : BITFIELD_RANGE(31, 31);
// DWORD 8
// DWORD 8, 9
uint64_t SurfaceBaseAddress;
// DWORD 10
// DWORD 10, 11
uint64_t QuiltWidth : BITFIELD_RANGE(0, 4);
uint64_t QuiltHeight : BITFIELD_RANGE(5, 9);
uint64_t ClearValueAddressEnable : BITFIELD_RANGE(10, 10);
@@ -1523,11 +1520,10 @@ typedef struct tagRENDER_SURFACE_STATE {
uint32_t SeparateUvPlaneEnable : BITFIELD_RANGE(31, 31);
// DWORD 7
uint32_t Reserved_224;
// DWORD 8
// DWORD 8, 9
uint64_t Reserved_256;
// DWORD 10
uint64_t Reserved_320 : BITFIELD_RANGE(0, 11);
uint64_t Reserved_332 : BITFIELD_RANGE(12, 31);
uint64_t Reserved_320 : BITFIELD_RANGE(0, 31);
// DWORD 11
uint64_t YOffsetForVPlane : BITFIELD_RANGE(32, 45);
uint64_t Reserved_366 : BITFIELD_RANGE(46, 47);
@@ -1558,15 +1554,14 @@ typedef struct tagRENDER_SURFACE_STATE {
// DWORD 6
uint32_t AuxiliarySurfaceMode : BITFIELD_RANGE(0, 2);
uint32_t AuxiliarySurfacePitch : BITFIELD_RANGE(3, 12);
uint32_t Reserved_205 : BITFIELD_RANGE(13, 13);
uint32_t Reserved_206 : BITFIELD_RANGE(14, 15);
uint32_t Reserved_205 : BITFIELD_RANGE(13, 15);
uint32_t AuxiliarySurfaceQpitch : BITFIELD_RANGE(16, 30);
uint32_t Reserved_223 : BITFIELD_RANGE(31, 31);
// DWORD 7
uint32_t Reserved_224;
// DWORD 8
// DWORD 8, 9
uint64_t Reserved_256;
// DWORD 10
// DWORD 10, 11
uint64_t Reserved_320;
// DWORD 12
uint32_t Reserved_384;
@@ -1594,9 +1589,9 @@ typedef struct tagRENDER_SURFACE_STATE {
uint32_t Reserved_192;
// DWORD 7
uint32_t Reserved_224;
// DWORD 8
// DWORD 8, 9
uint64_t Reserved_256;
// DWORD 10
// DWORD 10, 11
uint64_t Reserved_320 : BITFIELD_RANGE(0, 11);
uint64_t AuxiliarySurfaceBaseAddress : BITFIELD_RANGE(12, 63);
// DWORD 12
@@ -1623,13 +1618,14 @@ typedef struct tagRENDER_SURFACE_STATE {
TILE_MODE_LINEAR = 0x0,
TILE_MODE_TILE64 = 0x1,
TILE_MODE_XMAJOR = 0x2,
TILE_MODE_YMAJOR = 0x3,
TILE_MODE_TILE4 = 0x3,
} TILE_MODE;
typedef enum tagSURFACE_HORIZONTAL_ALIGNMENT {
SURFACE_HORIZONTAL_ALIGNMENT_HALIGN_4 = 0x1,
SURFACE_HORIZONTAL_ALIGNMENT_HALIGN_8 = 0x2,
SURFACE_HORIZONTAL_ALIGNMENT_HALIGN_16 = 0x3,
SURFACE_HORIZONTAL_ALIGNMENT_HALIGN_DEFAULT = SURFACE_HORIZONTAL_ALIGNMENT_HALIGN_4,
SURFACE_HORIZONTAL_ALIGNMENT_HALIGN_16 = 0x0,
SURFACE_HORIZONTAL_ALIGNMENT_HALIGN_32 = 0x1,
SURFACE_HORIZONTAL_ALIGNMENT_HALIGN_64 = 0x2,
SURFACE_HORIZONTAL_ALIGNMENT_HALIGN_128 = 0x3,
SURFACE_HORIZONTAL_ALIGNMENT_HALIGN_DEFAULT = SURFACE_HORIZONTAL_ALIGNMENT_HALIGN_32,
} SURFACE_HORIZONTAL_ALIGNMENT;
typedef enum tagSURFACE_VERTICAL_ALIGNMENT {
SURFACE_VERTICAL_ALIGNMENT_VALIGN_4 = 0x1,
@@ -1646,6 +1642,20 @@ typedef struct tagRENDER_SURFACE_STATE {
SURFACE_FORMAT_R32G32B32X32_FLOAT = 0x6,
SURFACE_FORMAT_R32G32B32A32_SSCALED = 0x7,
SURFACE_FORMAT_R32G32B32A32_USCALED = 0x8,
SURFACE_FORMAT_PLANAR_422_8_P208 = 0xc,
SURFACE_FORMAT_PLANAR_420_8_SAMPLE_8X8 = 0xd,
SURFACE_FORMAT_PLANAR_411_8 = 0xe,
SURFACE_FORMAT_PLANAR_422_8 = 0xf,
SURFACE_FORMAT_R8G8B8A8_UNORM_VDI = 0x10,
SURFACE_FORMAT_YCRCB_NORMAL_SAMPLE_8X8 = 0x11,
SURFACE_FORMAT_YCRCB_SWAPUVY_SAMPLE_8X8 = 0x12,
SURFACE_FORMAT_YCRCB_SWAPUV_SAMPLE_8X8 = 0x13,
SURFACE_FORMAT_YCRCB_SWAPY_SAMPLE_8X8 = 0x14,
SURFACE_FORMAT_R32G32B32A32_FLOAT_LD = 0x15,
SURFACE_FORMAT_PLANAR_420_16_SAMPLE_8X8 = 0x16,
SURFACE_FORMAT_R16B16_UNORM_SAMPLE_8X8 = 0x17,
SURFACE_FORMAT_Y16_UNORM_SAMPLE_8X8 = 0x18,
SURFACE_FORMAT_PLANAR_Y32_UNORM = 0x19,
SURFACE_FORMAT_R32G32B32A32_SFIXED = 0x20,
SURFACE_FORMAT_R64G64_PASSTHRU = 0x21,
SURFACE_FORMAT_R32G32B32_FLOAT = 0x40,
@@ -1655,6 +1665,7 @@ typedef struct tagRENDER_SURFACE_STATE {
SURFACE_FORMAT_R32G32B32_SNORM = 0x44,
SURFACE_FORMAT_R32G32B32_SSCALED = 0x45,
SURFACE_FORMAT_R32G32B32_USCALED = 0x46,
SURFACE_FORMAT_R32G32B32_FLOAT_LD = 0x47,
SURFACE_FORMAT_R32G32B32_SFIXED = 0x50,
SURFACE_FORMAT_R16G16B16A16_UNORM = 0x80,
SURFACE_FORMAT_R16G16B16A16_SNORM = 0x81,
@@ -1679,6 +1690,8 @@ typedef struct tagRENDER_SURFACE_STATE {
SURFACE_FORMAT_R16G16B16A16_USCALED = 0x94,
SURFACE_FORMAT_R32G32_SSCALED = 0x95,
SURFACE_FORMAT_R32G32_USCALED = 0x96,
SURFACE_FORMAT_R32G32_FLOAT_LD = 0x97,
SURFACE_FORMAT_R32_FLOAT_X8X24_TYPELESS_LD = 0x98,
SURFACE_FORMAT_R32G32_SFIXED = 0xa0,
SURFACE_FORMAT_R64_PASSTHRU = 0xa1,
SURFACE_FORMAT_B8G8R8A8_UNORM = 0xc0,
@@ -1687,6 +1700,7 @@ typedef struct tagRENDER_SURFACE_STATE {
SURFACE_FORMAT_R10G10B10A2_UNORM_SRGB = 0xc3,
SURFACE_FORMAT_R10G10B10A2_UINT = 0xc4,
SURFACE_FORMAT_R10G10B10_SNORM_A2_UNORM = 0xc5,
SURFACE_FORMAT_R10G10B10A2_UNORM_SAMPLE_8X8 = 0xc6,
SURFACE_FORMAT_R8G8B8A8_UNORM = 0xc7,
SURFACE_FORMAT_R8G8B8A8_UNORM_SRGB = 0xc8,
SURFACE_FORMAT_R8G8B8A8_SNORM = 0xc9,
@@ -1706,6 +1720,8 @@ typedef struct tagRENDER_SURFACE_STATE {
SURFACE_FORMAT_R32_FLOAT = 0xd8,
SURFACE_FORMAT_R24_UNORM_X8_TYPELESS = 0xd9,
SURFACE_FORMAT_X24_TYPELESS_G8_UINT = 0xda,
SURFACE_FORMAT_R32_FLOAT_LD = 0xdb,
SURFACE_FORMAT_R24_UNORM_X8_TYPELESS_LD = 0xdc,
SURFACE_FORMAT_L32_UNORM = 0xdd,
SURFACE_FORMAT_A32_UNORM = 0xde,
SURFACE_FORMAT_L16A16_UNORM = 0xdf,
@@ -1734,6 +1750,12 @@ typedef struct tagRENDER_SURFACE_STATE {
SURFACE_FORMAT_R16G16_USCALED = 0xf7,
SURFACE_FORMAT_R32_SSCALED = 0xf8,
SURFACE_FORMAT_R32_USCALED = 0xf9,
SURFACE_FORMAT_R8B8G8A8_UNORM = 0xfa,
SURFACE_FORMAT_R8G8B8A8_SINT_NOA = 0xfb,
SURFACE_FORMAT_R8G8B8A8_UINT_NOA = 0xfc,
SURFACE_FORMAT_R8G8B8A8_UNORM_YUV = 0xfd,
SURFACE_FORMAT_R8G8B8A8_UNORM_SNCK = 0xfe,
SURFACE_FORMAT_R8G8B8A8_UNORM_NOA = 0xff,
SURFACE_FORMAT_B5G6R5_UNORM = 0x100,
SURFACE_FORMAT_B5G6R5_UNORM_SRGB = 0x101,
SURFACE_FORMAT_B5G5R5A1_UNORM = 0x102,
@@ -1766,6 +1788,8 @@ typedef struct tagRENDER_SURFACE_STATE {
SURFACE_FORMAT_R8G8_USCALED = 0x11d,
SURFACE_FORMAT_R16_SSCALED = 0x11e,
SURFACE_FORMAT_R16_USCALED = 0x11f,
SURFACE_FORMAT_R8G8_SNORM_DX9 = 0x120,
SURFACE_FORMAT_R16_FLOAT_DX9 = 0x121,
SURFACE_FORMAT_P8A8_UNORM_PALETTE0 = 0x122,
SURFACE_FORMAT_P8A8_UNORM_PALETTE1 = 0x123,
SURFACE_FORMAT_A1B5G5R5_UNORM = 0x124,
@@ -1794,7 +1818,6 @@ typedef struct tagRENDER_SURFACE_STATE {
SURFACE_FORMAT_I8_UINT = 0x154,
SURFACE_FORMAT_I8_SINT = 0x155,
SURFACE_FORMAT_DXT1_RGB_SRGB = 0x180,
SURFACE_FORMAT_R1_UNORM = 0x181,
SURFACE_FORMAT_YCRCB_NORMAL = 0x182,
SURFACE_FORMAT_YCRCB_SWAPUVY = 0x183,
SURFACE_FORMAT_P2_UNORM_PALETTE0 = 0x184,
@@ -1824,6 +1847,7 @@ typedef struct tagRENDER_SURFACE_STATE {
SURFACE_FORMAT_R16G16B16_SNORM = 0x19d,
SURFACE_FORMAT_R16G16B16_SSCALED = 0x19e,
SURFACE_FORMAT_R16G16B16_USCALED = 0x19f,
SURFACE_FORMAT_R8B8_UNORM = 0x1a0,
SURFACE_FORMAT_BC6H_SF16 = 0x1a1,
SURFACE_FORMAT_BC7_UNORM = 0x1a2,
SURFACE_FORMAT_BC7_UNORM_SRGB = 0x1a3,
@@ -1873,10 +1897,6 @@ typedef struct tagRENDER_SURFACE_STATE {
SAMPLE_TAP_DISCARD_DISABLE_DISABLE = 0x0,
SAMPLE_TAP_DISCARD_DISABLE_ENABLE = 0x1,
} SAMPLE_TAP_DISCARD_DISABLE;
typedef enum tagNULL_PROBING_ENABLE {
NULL_PROBING_ENABLE_DISABLE = 0x0,
NULL_PROBING_ENABLE_ENABLE = 0x1,
} NULL_PROBING_ENABLE;
typedef enum tagNUMBER_OF_MULTISAMPLES {
NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_1 = 0x0,
NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_2 = 0x1,
@@ -1894,11 +1914,15 @@ typedef struct tagRENDER_SURFACE_STATE {
RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_180DEG = 0x2,
RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_270DEG = 0x3,
} RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION;
typedef enum tagDECOMPRESS_IN_L3 {
DECOMPRESS_IN_L3_DISABLE = 0x0,
} DECOMPRESS_IN_L3;
typedef enum tagCOHERENCY_TYPE {
COHERENCY_TYPE_GPU_COHERENT = 0x0,
COHERENCY_TYPE_IA_COHERENT = 0x1,
COHERENCY_TYPE_GPU_COHERENT = 0x0, // patched from COHERENCY_TYPE_SINGLE_GPU_COHERENT
COHERENCY_TYPE_IA_COHERENT = 0x1, // patched from COHERENCY_TYPE_SYSTEM_COHERENT
COHERENCY_TYPE_MULTI_GPU_COHERENT = 0x2,
} COHERENCY_TYPE;
typedef enum tagL1_CACHE_POLICY {
typedef enum tagL1_CACHE_POLICY { // patched
L1_CACHE_POLICY_WBP = 0x0,
L1_CACHE_POLICY_UC = 0x1,
L1_CACHE_POLICY_WB = 0x2,
@@ -1924,6 +1948,10 @@ typedef struct tagRENDER_SURFACE_STATE {
SHADER_CHANNEL_SELECT_BLUE = 0x6,
SHADER_CHANNEL_SELECT_ALPHA = 0x7,
} SHADER_CHANNEL_SELECT;
typedef enum tagMEMORY_COMPRESSION_TYPE {
MEMORY_COMPRESSION_TYPE_MEDIA_COMPRESSION = 0x0,
MEMORY_COMPRESSION_TYPE_3D_COMPRESSION = 0x1,
} MEMORY_COMPRESSION_TYPE;
typedef enum tagMEMORY_COMPRESSION_MODE {
MEMORY_COMPRESSION_MODE_HORIZONTAL = 0x0,
} MEMORY_COMPRESSION_MODE;
@@ -1953,17 +1981,15 @@ typedef struct tagRENDER_SURFACE_STATE {
TheStructure.Common.SurfaceVerticalAlignment = SURFACE_VERTICAL_ALIGNMENT_VALIGN_4;
TheStructure.Common.SurfaceType = SURFACE_TYPE_SURFTYPE_1D;
TheStructure.Common.SampleTapDiscardDisable = SAMPLE_TAP_DISCARD_DISABLE_DISABLE;
TheStructure.Common.NullProbingEnable = NULL_PROBING_ENABLE_DISABLE;
TheStructure.Common.NumberOfMultisamples = NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_1;
TheStructure.Common.MultisampledSurfaceStorageFormat = MULTISAMPLED_SURFACE_STORAGE_FORMAT_MSS;
TheStructure.Common.RenderTargetAndSampleUnormRotation = RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_0DEG;
TheStructure.Common.DecompressInL3 = DECOMPRESS_IN_L3_DISABLE;
TheStructure.Common.CoherencyType = COHERENCY_TYPE_GPU_COHERENT;
TheStructure.Common.L1CachePolicyL1CacheControl = L1_CACHE_POLICY_WBP;
TheStructure.Common.L1CacheControlCachePolicy = L1_CACHE_POLICY_WBP;
TheStructure.Common.MemoryCompressionMode = MEMORY_COMPRESSION_MODE_HORIZONTAL;
TheStructure._SurfaceFormatIsPlanar.HalfPitchForChroma = HALF_PITCH_FOR_CHROMA_DISABLE;
TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfaceMode = AUXILIARY_SURFACE_MODE_AUX_NONE;
TheStructure.Common.DisableSupportForMultiGpuAtomics = 1;
TheStructure.Common.DisableSupportForMultiGpuPartialWrites = 1;
}
static tagRENDER_SURFACE_STATE sInit() {
RENDER_SURFACE_STATE state;
@@ -2064,12 +2090,6 @@ typedef struct tagRENDER_SURFACE_STATE {
inline SURFACE_FORMAT getSurfaceFormat() const {
return static_cast<SURFACE_FORMAT>(TheStructure.Common.SurfaceFormat);
}
inline void setAstcEnable(const bool value) {
TheStructure.Common.AstcEnable = value;
}
inline bool getAstcEnable() const {
return TheStructure.Common.AstcEnable;
}
inline void setSurfaceArray(const bool value) {
TheStructure.Common.SurfaceArray = value;
}
@@ -2087,7 +2107,7 @@ typedef struct tagRENDER_SURFACE_STATE {
SURFACEQPITCH_ALIGN_SIZE = 0x4,
} SURFACEQPITCH;
inline void setSurfaceQpitch(const uint32_t value) {
UNRECOVERABLE_IF(value > 0x1ffff);
UNRECOVERABLE_IF((value >> SURFACEQPITCH_BIT_SHIFT) > 0x1ffff);
TheStructure.Common.SurfaceQpitch = value >> SURFACEQPITCH_BIT_SHIFT;
}
inline uint32_t getSurfaceQpitch() const {
@@ -2118,28 +2138,24 @@ typedef struct tagRENDER_SURFACE_STATE {
inline uint32_t getBaseMipLevel() const {
return TheStructure.Common.BaseMipLevel;
}
inline void setMemoryObjectControlStateReserved(const uint32_t value) {
TheStructure.Common.MemoryObjectControlStateReserved_56 = value;
}
inline uint32_t getMemoryObjectControlStateReserved() const {
return (TheStructure.Common.MemoryObjectControlStateReserved_56);
}
inline void setMemoryObjectControlState(const uint32_t value) {
TheStructure.Common.MemoryObjectControlStateReserved_56 = value;
inline void setMemoryObjectControlState(const uint32_t value) { // patched
TheStructure.Common.MemoryObjectControlStateEncryptedData = value;
TheStructure.Common.MemoryObjectControlStateIndexToMocsTables = (value >> 1);
}
inline uint32_t getMemoryObjectControlState() const {
uint32_t mocs = TheStructure.Common.MemoryObjectControlStateReserved_56;
inline uint32_t getMemoryObjectControlState() const { // patched
uint32_t mocs = TheStructure.Common.MemoryObjectControlStateEncryptedData;
mocs |= (TheStructure.Common.MemoryObjectControlStateIndexToMocsTables << 1);
return (mocs);
}
inline void setWidth(const uint32_t value) {
UNRECOVERABLE_IF((value - 1) > 0x3fff);
TheStructure.Common.Width = value - 1;
}
inline uint32_t getWidth() const {
return TheStructure.Common.Width + 1;
}
inline void setHeight(const uint32_t value) {
UNRECOVERABLE_IF((value - 1) > 0x3fff);
TheStructure.Common.Height = value - 1;
}
inline uint32_t getHeight() const {
@@ -2152,19 +2168,14 @@ typedef struct tagRENDER_SURFACE_STATE {
return TheStructure.Common.DepthStencilResource;
}
inline void setSurfacePitch(const uint32_t value) {
UNRECOVERABLE_IF(value > 0x40000);
UNRECOVERABLE_IF((value - 1) > 0x3ffff);
TheStructure.Common.SurfacePitch = value - 1;
}
inline uint32_t getSurfacePitch() const {
return TheStructure.Common.SurfacePitch + 1;
}
inline void setNullProbingEnable(const NULL_PROBING_ENABLE value) {
TheStructure.Common.NullProbingEnable = value;
}
inline NULL_PROBING_ENABLE getNullProbingEnable() const {
return static_cast<NULL_PROBING_ENABLE>(TheStructure.Common.NullProbingEnable);
}
inline void setDepth(const uint32_t value) {
UNRECOVERABLE_IF((value - 1) > 0x7ff);
TheStructure.Common.Depth = value - 1;
}
inline uint32_t getDepth() const {
@@ -2190,7 +2201,7 @@ typedef struct tagRENDER_SURFACE_STATE {
return static_cast<MULTISAMPLED_SURFACE_STORAGE_FORMAT>(TheStructure.Common.MultisampledSurfaceStorageFormat);
}
inline void setRenderTargetViewExtent(const uint32_t value) {
UNRECOVERABLE_IF(value > 0x7ff);
UNRECOVERABLE_IF((value - 1) > 0x7ff);
TheStructure.Common.RenderTargetViewExtent = value - 1;
}
inline uint32_t getRenderTargetViewExtent() const {
@@ -2209,6 +2220,12 @@ typedef struct tagRENDER_SURFACE_STATE {
inline RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION getRenderTargetAndSampleUnormRotation() const {
return static_cast<RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION>(TheStructure.Common.RenderTargetAndSampleUnormRotation);
}
inline void setDecompressInL3(const DECOMPRESS_IN_L3 value) {
TheStructure.Common.DecompressInL3 = value;
}
inline DECOMPRESS_IN_L3 getDecompressInL3() const {
return static_cast<DECOMPRESS_IN_L3>(TheStructure.Common.DecompressInL3);
}
inline void setMipCountLod(const uint32_t value) {
UNRECOVERABLE_IF(value > 0xf);
TheStructure.Common.MipCountLod = value;
@@ -2236,11 +2253,11 @@ typedef struct tagRENDER_SURFACE_STATE {
inline COHERENCY_TYPE getCoherencyType() const {
return static_cast<COHERENCY_TYPE>(TheStructure.Common.CoherencyType);
}
inline void setL1CachePolicyL1CacheControl(const L1_CACHE_POLICY value) {
TheStructure.Common.L1CachePolicyL1CacheControl = value;
inline void setL1CachePolicyL1CacheControl(const L1_CACHE_POLICY value) { // patched
TheStructure.Common.L1CacheControlCachePolicy = value;
}
inline L1_CACHE_POLICY getL1CachePolicyL1CacheControl() const {
return static_cast<L1_CACHE_POLICY>(TheStructure.Common.L1CachePolicyL1CacheControl);
inline L1_CACHE_POLICY getL1CachePolicyL1CacheControl() const { // patched
return static_cast<L1_CACHE_POLICY>(TheStructure.Common.L1CacheControlCachePolicy);
}
inline void setEwaDisableForCube(const bool value) {
TheStructure.Common.EwaDisableForCube = value;
@@ -2253,7 +2270,7 @@ typedef struct tagRENDER_SURFACE_STATE {
YOFFSET_ALIGN_SIZE = 0x4,
} YOFFSET;
inline void setYOffset(const uint32_t value) {
UNRECOVERABLE_IF(value > 0x1f);
UNRECOVERABLE_IF((value >> YOFFSET_BIT_SHIFT) > 0x1f);
TheStructure.Common.YOffset = value >> YOFFSET_BIT_SHIFT;
}
inline uint32_t getYOffset() const {
@@ -2264,7 +2281,7 @@ typedef struct tagRENDER_SURFACE_STATE {
XOFFSET_ALIGN_SIZE = 0x4,
} XOFFSET;
inline void setXOffset(const uint32_t value) {
UNRECOVERABLE_IF(value > 0x1ff);
UNRECOVERABLE_IF((value >> XOFFSET_BIT_SHIFT) > 0x1ff);
TheStructure.Common.XOffset = value >> XOFFSET_BIT_SHIFT;
}
inline uint32_t getXOffset() const {
@@ -2283,19 +2300,6 @@ typedef struct tagRENDER_SURFACE_STATE {
inline uint32_t getResourceMinLod() const {
return TheStructure.Common.ResourceMinLod;
}
inline void setDisableSupportForMultiGpuAtomics(const bool value) {
TheStructure.Common.DisableSupportForMultiGpuAtomics = value;
}
inline bool getDisableSupportForMultiGpuAtomics() const {
return TheStructure.Common.DisableSupportForMultiGpuAtomics;
}
inline void setDisableSupportForMultiGpuPartialWrites(const bool value) {
TheStructure.Common.DisableSupportForMultiGpuPartialWrites = value;
}
inline bool getDisableSupportForMultiGpuPartialWrites() const {
return TheStructure.Common.DisableSupportForMultiGpuPartialWrites;
}
inline void setShaderChannelSelectAlpha(const SHADER_CHANNEL_SELECT value) {
TheStructure.Common.ShaderChannelSelectAlpha = value;
}
@@ -2364,29 +2368,27 @@ typedef struct tagRENDER_SURFACE_STATE {
inline bool getProceduralTexture() const {
return TheStructure.Common.ProceduralTexture;
}
inline void setCompressionFormat(uint32_t compressionFormat) {
UNRECOVERABLE_IF(compressionFormat > 0x1F);
TheStructure.Common.CompressionFormat = compressionFormat;
inline void setCompressionFormat(const uint32_t value) { // patched
TheStructure.Common.CompressionFormat = value;
}
inline uint32_t getCompressionFormat() const {
inline uint32_t getCompressionFormat() const { // patched
return TheStructure.Common.CompressionFormat;
}
typedef enum tagCLEARADDRESSLOW {
CLEARADDRESSLOW_BIT_SHIFT = 0x6,
CLEARADDRESSLOW_ALIGN_SIZE = 0x40,
} CLEARADDRESSLOW;
inline void setClearColorAddress(const uint32_t value) {
UNRECOVERABLE_IF(value > 0xffffffff);
inline void setClearColorAddress(const uint32_t value) { // patched
TheStructure.Common.ClearAddressLow = value >> CLEARADDRESSLOW_BIT_SHIFT;
}
inline uint32_t getClearColorAddress() const {
inline uint32_t getClearColorAddress() const { // patched
return TheStructure.Common.ClearAddressLow << CLEARADDRESSLOW_BIT_SHIFT;
}
inline void setClearColorAddressHigh(const uint32_t value) {
inline void setClearColorAddressHigh(const uint32_t value) { // patched
UNRECOVERABLE_IF(value > 0xffff);
TheStructure.Common.ClearAddressHigh = value;
}
inline uint32_t getClearColorAddressHigh() const {
inline uint32_t getClearColorAddressHigh() const { // patched
return TheStructure.Common.ClearAddressHigh;
}
inline void setYOffsetForUOrUvPlane(const uint32_t value) {
@@ -2436,7 +2438,7 @@ typedef struct tagRENDER_SURFACE_STATE {
return static_cast<AUXILIARY_SURFACE_MODE>(TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfaceMode);
}
inline void setAuxiliarySurfacePitch(const uint32_t value) {
UNRECOVERABLE_IF(value > 0x3ff);
UNRECOVERABLE_IF((value - 1) > 0x3ff);
TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfacePitch = value - 1;
}
inline uint32_t getAuxiliarySurfacePitch() const {
@@ -2447,7 +2449,7 @@ typedef struct tagRENDER_SURFACE_STATE {
AUXILIARYSURFACEQPITCH_ALIGN_SIZE = 0x4,
} AUXILIARYSURFACEQPITCH;
inline void setAuxiliarySurfaceQpitch(const uint32_t value) {
UNRECOVERABLE_IF(value > 0x1ffff);
UNRECOVERABLE_IF((value >> AUXILIARYSURFACEQPITCH_BIT_SHIFT) > 0x1ffff);
TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfaceQpitch = value >> AUXILIARYSURFACEQPITCH_BIT_SHIFT;
}
inline uint32_t getAuxiliarySurfaceQpitch() const {
@@ -2458,7 +2460,6 @@ typedef struct tagRENDER_SURFACE_STATE {
AUXILIARYSURFACEBASEADDRESS_ALIGN_SIZE = 0x1000,
} AUXILIARYSURFACEBASEADDRESS;
inline void setAuxiliarySurfaceBaseAddress(const uint64_t value) {
UNRECOVERABLE_IF(value > 0xffffffffffffffffL);
TheStructure._SurfaceFormatIsnotPlanarAndMemoryCompressionEnableIs0.AuxiliarySurfaceBaseAddress = value >> AUXILIARYSURFACEBASEADDRESS_BIT_SHIFT;
}
inline uint64_t getAuxiliarySurfaceBaseAddress() const {

25
shared/source/generated/xe_hpg_core/hw_cmds_generated_xe_hpg_core.inl
View File

@@ -1217,9 +1217,9 @@ typedef struct tagRENDER_SURFACE_STATE {
uint32_t Reserved_252 : BITFIELD_RANGE(28, 29);
uint32_t MemoryCompressionEnable : BITFIELD_RANGE(30, 30);
uint32_t MemoryCompressionType : BITFIELD_RANGE(31, 31);
// DWORD 8
// DWORD 8, 9
uint64_t SurfaceBaseAddress;
// DWORD 10
// DWORD 10, 11
uint64_t QuiltWidth : BITFIELD_RANGE(0, 4);
uint64_t QuiltHeight : BITFIELD_RANGE(5, 9);
uint64_t ClearValueAddressEnable : BITFIELD_RANGE(10, 10);
@@ -1259,16 +1259,15 @@ typedef struct tagRENDER_SURFACE_STATE {
uint32_t SeparateUvPlaneEnable : BITFIELD_RANGE(31, 31);
// DWORD 7
uint32_t Reserved_224;
// DWORD 8
// DWORD 8, 9
uint64_t Reserved_256;
// DWORD 10
uint64_t Reserved_320 : BITFIELD_RANGE(0, 11);
uint64_t Reserved_332 : 20; /* WARNING: Uncontinuous fields, bit position gap. Patched with dummy field */
uint64_t Reserved_320 : BITFIELD_RANGE(0, 31);
// DWORD 11
uint64_t YOffsetForVPlane : BITFIELD_RANGE(32, 45);
uint64_t Reserved_366 : 2; /* WARNING: Uncontinuous fields, bit position gap. Patched with dummy field */
uint64_t Reserved_366 : BITFIELD_RANGE(46, 47);
uint64_t XOffsetForVPlane : BITFIELD_RANGE(48, 61);
uint64_t Reserved_382 : 2; /* WARNING: Uncontinuous fields, bit position gap. Patched with dummy field */
uint64_t Reserved_382 : BITFIELD_RANGE(62, 63);
// DWORD 12
uint32_t Reserved_384;
// DWORD 13
@@ -1294,15 +1293,14 @@ typedef struct tagRENDER_SURFACE_STATE {
// DWORD 6
uint32_t AuxiliarySurfaceMode : BITFIELD_RANGE(0, 2);
uint32_t AuxiliarySurfacePitch : BITFIELD_RANGE(3, 12);
uint32_t Reserved_205 : 1; /* WARNING: Uncontinuous fields, bit position gap. Patched with dummy field */
uint32_t Reserved_206 : BITFIELD_RANGE(14, 15);
uint32_t Reserved_205 : BITFIELD_RANGE(13, 15);
uint32_t AuxiliarySurfaceQpitch : BITFIELD_RANGE(16, 30);
uint32_t Reserved_223 : BITFIELD_RANGE(31, 31);
// DWORD 7
uint32_t Reserved_224;
// DWORD 8
// DWORD 8, 9
uint64_t Reserved_256;
// DWORD 10
// DWORD 10, 11
uint64_t Reserved_320;
// DWORD 12
uint32_t Reserved_384;
@@ -1330,9 +1328,9 @@ typedef struct tagRENDER_SURFACE_STATE {
uint32_t Reserved_192;
// DWORD 7
uint32_t Reserved_224;
// DWORD 8
// DWORD 8, 9
uint64_t Reserved_256;
// DWORD 10
// DWORD 10, 11
uint64_t Reserved_320 : BITFIELD_RANGE(0, 11);
uint64_t AuxiliarySurfaceBaseAddress : BITFIELD_RANGE(12, 63);
// DWORD 12
@@ -1360,7 +1358,6 @@ typedef struct tagRENDER_SURFACE_STATE {
TILE_MODE_TILE64 = 0x1,
TILE_MODE_XMAJOR = 0x2,
TILE_MODE_TILE4 = 0x3,
TILE_MODE_YMAJOR = 0x3, // patched - old name for TILE_MODE_TILE4
} TILE_MODE;
typedef enum tagSURFACE_HORIZONTAL_ALIGNMENT {
SURFACE_HORIZONTAL_ALIGNMENT_HALIGN_16 = 0x0,