Media/compute-runtime
1
0
Fork 0
mirror of https://github.com/intel/compute-runtime.git synced 2025-09-15 13:01:45 +08:00
Code Issues Packages Projects Releases Wiki Activity

Handle implicit arg relocation in L0 module

Browse Source 
Related-To: NEO-5081
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
This commit is contained in:
Mateusz Jablonski
2021-09-13 14:07:45 +00:00
committed by Compute-Runtime-Automation
parent e5d5c23606
commit 0d1c8be447
6 changed files with 77 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
shared/source/compiler_interface/linker.cpp
View File

@ -458,4 +458,12 @@ void Linker::applyDebugDataRelocations(const NEO::Elf::Elf<NEO::Elf::EI_CLASS_64
}
}
bool LinkerInput::areImplicitArgsRequired(uint32_t instructionsSegmentId) const {
if (relocations.size() > instructionsSegmentId) {
const auto &segmentRelocations = relocations[instructionsSegmentId];
return (segmentRelocations.end() != std::find_if(segmentRelocations.begin(), segmentRelocations.end(), [&](const auto &relocation) { return relocation.symbolName == implicitArgsRelocationSymbolName; }));
}
return false;
}
} // namespace NEO

1
shared/source/compiler_interface/linker.h
View File

@ -137,6 +137,7 @@ struct LinkerInput {
bool isValid() const {
return valid;
}
bool areImplicitArgsRequired(uint32_t instructionsSegmentId) const;
bool undefinedSymbolsAllowed = false;

19
shared/test/unit_test/compiler_interface/linker_tests.cpp
View File

@ -1875,3 +1875,22 @@ TEST(LinkerTests, givenImplicitArgRelocationThenPatchRelocationWithSizeOfImplici
EXPECT_EQ(initData, *(addressToPatch - 1));
EXPECT_EQ(initData, *(addressToPatch + 1));
}
TEST(LinkerTests, givenImplicitArgRelocationThenImplicitArgsAreRequired) {
NEO::LinkerInput linkerInput;
EXPECT_FALSE(linkerInput.areImplicitArgsRequired(0u));
vISA::GenRelocEntry reloc = {};
std::string relocationName = implicitArgsRelocationSymbolName;
memcpy_s(reloc.r_symbol, 1024, relocationName.c_str(), relocationName.size());
reloc.r_offset = 8;
reloc.r_type = vISA::GenRelocType::R_SYM_ADDR_32;
vISA::GenRelocEntry relocs[] = {reloc};
constexpr uint32_t numRelocations = 1;
bool decodeRelocSuccess = linkerInput.decodeRelocationTable(&relocs, numRelocations, 0);
EXPECT_TRUE(decodeRelocSuccess);
EXPECT_TRUE(linkerInput.areImplicitArgsRequired(0u));
}