From 16e9aaa1cff518d42bef658ecb1031d3c2b26778 Mon Sep 17 00:00:00 2001
From: Bartosz Dunajski <bartosz.dunajski@intel.com>
Date: Wed, 8 Dec 2021 09:55:49 +0000
Subject: [PATCH] Update ftr flags list

Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
---
 shared/source/sku_info/sku_info_base.h                 | 3 ++-
 shared/source/xe_hpc_core/linux/hw_info_config_pvc.cpp | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/shared/source/sku_info/sku_info_base.h b/shared/source/sku_info/sku_info_base.h
index 9de0459423..9be20ab275 100644
--- a/shared/source/sku_info/sku_info_base.h
+++ b/shared/source/sku_info/sku_info_base.h
@@ -95,7 +95,8 @@ struct FeatureTableBase {
         uint32_t ftrCCSMultiInstance : 1;
         uint32_t ftrPpgtt64KBWalkOptimization : 1;
         uint32_t ftrUnified3DMediaCompressionFormats : 1;
-        uint32_t reserved : 22;
+        uint32_t ftr57bGPUAddressing : 1;
+        uint32_t reserved : 21;
     };
 
     union {
diff --git a/shared/source/xe_hpc_core/linux/hw_info_config_pvc.cpp b/shared/source/xe_hpc_core/linux/hw_info_config_pvc.cpp
index d7fdb759db..ca3d288c8d 100644
--- a/shared/source/xe_hpc_core/linux/hw_info_config_pvc.cpp
+++ b/shared/source/xe_hpc_core/linux/hw_info_config_pvc.cpp
@@ -22,7 +22,7 @@ template <>
 int HwInfoConfigHw<gfxProduct>::configureHardwareCustom(HardwareInfo *hwInfo, OSInterface *osIface) {
     enableCompression(hwInfo);
 
-    hwInfo->featureTable.embargoFlags.ftr57bGPUAddressing = (hwInfo->capabilityTable.gpuAddressSpace == maxNBitValue(57));
+    hwInfo->featureTable.flags.ftr57bGPUAddressing = (hwInfo->capabilityTable.gpuAddressSpace == maxNBitValue(57));
 
     enableBlitterOperationsSupport(hwInfo);