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refactor: unify logic isPipeControlPriorToNonPipelinedStateCommandsWARequired 

accept debug flag for all platforms
cleanup ocl unit tests for xe hpg platforms
remove not needed excludes

Related-To: NEO-8187

Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
This commit is contained in:
Mateusz Jablonski 2023-08-31 09:16:18 +00:00 committed by Compute-Runtime-Automation
parent 4bd992b108
commit 1b9d30ca01
16 changed files with 32 additions and 127 deletions
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2
opencl/test/unit_test/command_stream/command_stream_receiver_hw_tests_dg2_and_later.cpp
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@ -66,7 +66,7 @@ HWTEST2_F(CommandStreamReceiverHwTestDg2AndLater, givenGen12AndLaterWhenRayTraci
typedef UltCommandStreamReceiverTest CommandStreamReceiverFlushTaskDg2AndLaterTests;
HWTEST2_F(CommandStreamReceiverFlushTaskDg2AndLaterTests, givenProgramExtendedPipeControlPriorToNonPipelinedStateCommandEnabledWhenPerDssBackedBufferThenThereIsPipeControlPriorToIt, MatcherIsRTCapable) {
HWTEST2_F(CommandStreamReceiverFlushTaskDg2AndLaterTests, givenProgramExtendedPipeControlPriorToNonPipelinedStateCommandEnabledWhenPerDssBackedBufferThenThereIsPipeControlPriorToIt, IsDG2) {
DebugManagerStateRestore restore;
DebugManager.flags.ProgramExtendedPipeControlPriorToNonPipelinedStateCommand.set(true);

4
opencl/test/unit_test/mem_obj/image_tests_xehp_and_later.cpp
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@ -73,7 +73,7 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, XeHPAndLaterImageTests, givenCompressionEnabledWhen
EXPECT_EQ(image->getGraphicsAllocation(context.getDevice(0)->getRootDeviceIndex())->getDefaultGmm()->gmmResourceInfo->getResourceFormat(), mockGmmClient->capturedFormat);
}
HWCMDTEST_F(IGFX_XE_HP_CORE, XeHPAndLaterImageTests, givenCompressionWhenAppendingImageFromBufferThenTwoIsSetAsCompressionFormat) {
HWTEST2_F(XeHPAndLaterImageTests, givenCompressionWhenAppendingImageFromBufferThenTwoIsSetAsCompressionFormat, IsXeHpcCore) {
typedef typename FamilyType::RENDER_SURFACE_STATE RENDER_SURFACE_STATE;
MockContext context;
@ -112,7 +112,7 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, XeHPAndLaterImageTests, givenCompressionWhenAppendi
clReleaseMemObject(imageDesc.mem_object);
}
HWCMDTEST_F(IGFX_XE_HP_CORE, XeHPAndLaterImageTests, givenImageFromBufferWhenSettingSurfaceStateThenPickCompressionFormatFromDebugVariable) {
HWTEST2_F(XeHPAndLaterImageTests, givenImageFromBufferWhenSettingSurfaceStateThenPickCompressionFormatFromDebugVariable, IsXeHpcCore) {
typedef typename FamilyType::RENDER_SURFACE_STATE RENDER_SURFACE_STATE;
DebugManagerStateRestore restorer;

3
opencl/test/unit_test/xe_hpc_core/excludes_ocl_xe_hpc_core.cpp
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2022 Intel Corporation
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@ -18,7 +18,6 @@ HWTEST_EXCLUDE_PRODUCT(BuiltInTests, givenBigOffsetAndSizeWhenBuilderCopyImageTo
HWTEST_EXCLUDE_PRODUCT(BuiltInTests, givenBigOffsetAndSizeWhenBuilderCopyImageToLocalBufferStatelessIsUsedThenParamsAreCorrect, IGFX_XE_HPC_CORE);
HWTEST_EXCLUDE_PRODUCT(ClDeviceHelperTests, givenDeviceWithoutClosBasedCacheReservationSupportWhenQueryingNumCacheClosDeviceInfoThenReturnZeroCacheClosRegions, IGFX_XE_HPC_CORE);
HWTEST_EXCLUDE_PRODUCT(LocalWorkSizeTest, givenDispatchInfoWhenWorkSizeInfoIsCreatedThenTestEuFusionFtr, IGFX_XE_HPC_CORE);
HWTEST_EXCLUDE_PRODUCT(CommandStreamReceiverFlushTaskDg2AndLaterTests, givenProgramExtendedPipeControlPriorToNonPipelinedStateCommandEnabledWhenPerDssBackedBufferThenThereIsPipeControlPriorToIt_MatcherIsRTCapable, IGFX_XE_HPC_CORE);
HWTEST_EXCLUDE_PRODUCT(CommandStreamReceiverHwTestDg2AndLater, givenGen12AndLaterWhenRayTracingEnabledThenCommandIsAddedToBatchBuffer_MatcherIsRTCapable, IGFX_XE_HPC_CORE);
HWTEST_EXCLUDE_PRODUCT(CommandStreamReceiverHwTestDg2AndLater, givenGen12AndLaterWhenRayTracingEnabledButAlreadySentThenCommandIsNotAddedToBatchBuffer_MatcherIsRTCapable, IGFX_XE_HPC_CORE);
HWTEST_EXCLUDE_PRODUCT(HardwareCommandsTest, GivenVariousValuesWhenAlignSlmSizeIsCalledThenCorrectValueIsReturned, IGFX_XE_HPC_CORE);

3
opencl/test/unit_test/xe_hpc_core/pvc/get_device_info_pvc.cpp
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2022 Intel Corporation
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@ -14,7 +14,6 @@
using namespace NEO;
HWTEST_EXCLUDE_PRODUCT(GetDeviceInfoMemCapabilitiesTest, GivenValidParametersWhenGetDeviceInfoIsCalledForXE_HP_COREThenClSuccessIsReturned, IGFX_XE_HPC_CORE);
HWTEST_EXCLUDE_PRODUCT(GetDeviceInfoMemCapabilitiesTest, GivenEnableUsmConcurrentAccessSupportWhenGetDeviceInfoIsCalledForXE_HP_COREThenClSuccessIsReturned, IGFX_XE_HPC_CORE);
PVCTEST_F(GetDeviceInfoMemCapabilitiesTest, GivenValidParametersWhenGetDeviceInfoIsCalledForPVCThenClSuccessIsReturned) {

17
opencl/test/unit_test/xe_hpg_core/cl_gfx_core_helper_tests_xe_hpg_core.cpp
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@ -5,6 +5,7 @@
*
*/
#include "shared/source/os_interface/product_helper.h"
#include "shared/source/program/kernel_info.h"
#include "shared/source/xe_hpg_core/hw_info.h"
#include "shared/source/xe_hpg_core/hw_info_xe_hpg_core.h"
@ -14,6 +15,7 @@
#include "shared/test/common/test_macros/test.h"
#include "opencl/test/unit_test/fixtures/cl_device_fixture.h"
#include "opencl/test/unit_test/fixtures/device_info_fixture.h"
#include "opencl/test/unit_test/mocks/mock_cl_gfx_core_helper.h"
using ClGfxCoreHelperTestsXeHpgCore = Test<ClDeviceFixture>;
@ -120,3 +122,18 @@ XE_HPG_CORETEST_F(ClGfxCoreHelperTestsXeHpgCore, givenDifferentCLImageFormatsWhe
EXPECT_EQ(format.isCompressable, result);
}
}
XE_HPG_CORETEST_F(GetDeviceInfoMemCapabilitiesTest, GivenValidParametersWhenGetDeviceInfoIsCalledThenClSuccessIsReturned) {
auto productHelper = ProductHelper::create(defaultHwInfo->platform.eProductFamily);
std::vector<TestParams> params = {
{CL_DEVICE_HOST_MEM_CAPABILITIES_INTEL, productHelper->getHostMemCapabilities(defaultHwInfo.get())},
{CL_DEVICE_DEVICE_MEM_CAPABILITIES_INTEL,
(CL_UNIFIED_SHARED_MEMORY_ACCESS_INTEL | CL_UNIFIED_SHARED_MEMORY_ATOMIC_ACCESS_INTEL)},
{CL_DEVICE_SINGLE_DEVICE_SHARED_MEM_CAPABILITIES_INTEL,
(CL_UNIFIED_SHARED_MEMORY_ACCESS_INTEL | CL_UNIFIED_SHARED_MEMORY_ATOMIC_ACCESS_INTEL)},
{CL_DEVICE_CROSS_DEVICE_SHARED_MEM_CAPABILITIES_INTEL,
(CL_UNIFIED_SHARED_MEMORY_ACCESS_INTEL | CL_UNIFIED_SHARED_MEMORY_ATOMIC_ACCESS_INTEL)},
{CL_DEVICE_SHARED_SYSTEM_MEM_CAPABILITIES_INTEL, 0}};
check(params);
}

1
opencl/test/unit_test/xe_hpg_core/dg2/CMakeLists.txt
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@ -14,7 +14,6 @@ if(TESTS_DG2)
${IGDRCL_SRCS_tests_xe_hpg_core_dg2_excludes}
${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
${CMAKE_CURRENT_SOURCE_DIR}/command_queue_tests_dg2.cpp
${CMAKE_CURRENT_SOURCE_DIR}/get_device_info_dg2.cpp
${CMAKE_CURRENT_SOURCE_DIR}/test_cmds_programming_dg2.cpp
${CMAKE_CURRENT_SOURCE_DIR}/test_cl_device_caps_dg2.cpp
)

3
opencl/test/unit_test/xe_hpg_core/dg2/excludes_ocl_dg2.cpp
View File

@ -7,9 +7,6 @@
#include "shared/test/common/test_macros/hw_test_base.h"
HWTEST_EXCLUDE_PRODUCT(ProductHelperTestXeHpAndLater, givenXeHPAndLaterPlatformWhenAskedIfTile64With3DSurfaceOnBCSIsSupportedThenFalseIsReturned, IGFX_DG2);
HWTEST_EXCLUDE_PRODUCT(GfxCoreHelperTestXeHPAndLater, GiveCcsNodeThenDefaultEngineTypeIsCcs, IGFX_DG2);
HWTEST_EXCLUDE_PRODUCT(XeHPAndLaterDeviceCapsTests, givenHwInfoWhenRequestedComputeUnitsUsedForScratchThenReturnValidValue, IGFX_DG2);
HWTEST_EXCLUDE_PRODUCT(ProgramTests, givenAtLeastXeHpgCoreWhenGetInternalOptionsThenCorrectBuildOptionIsSet_IsAtLeastXeHpgCore, IGFX_DG2);
HWTEST_EXCLUDE_PRODUCT(CmdsProgrammingTestsXeHpgCore, givenL3ToL1DebugFlagWhenStatelessMocsIsProgrammedThenItHasL1CachingOn, IGFX_DG2);
HWTEST_EXCLUDE_PRODUCT(CmdsProgrammingTestsXeHpgCore, givenAlignedCacheableReadOnlyBufferThenChoseOclBufferConstPolicy, IGFX_DG2);

30
opencl/test/unit_test/xe_hpg_core/dg2/get_device_info_dg2.cpp
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@ -1,30 +0,0 @@
/*
* Copyright (C) 2021-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/xe_hpg_core/hw_cmds_dg2.h"
#include "shared/test/common/test_macros/header/per_product_test_definitions.h"
#include "shared/test/common/test_macros/test.h"
#include "opencl/test/unit_test/fixtures/device_info_fixture.h"
using namespace NEO;
HWTEST_EXCLUDE_PRODUCT(GetDeviceInfoMemCapabilitiesTest, GivenValidParametersWhenGetDeviceInfoIsCalledForXE_HP_COREThenClSuccessIsReturned, IGFX_DG2);
DG2TEST_F(GetDeviceInfoMemCapabilitiesTest, GivenValidParametersWhenGetDeviceInfoIsCalledForDG2ThenClSuccessIsReturned) {
std::vector<TestParams> params = {
{CL_DEVICE_HOST_MEM_CAPABILITIES_INTEL, CL_UNIFIED_SHARED_MEMORY_ACCESS_INTEL},
{CL_DEVICE_DEVICE_MEM_CAPABILITIES_INTEL,
(CL_UNIFIED_SHARED_MEMORY_ACCESS_INTEL | CL_UNIFIED_SHARED_MEMORY_ATOMIC_ACCESS_INTEL)},
{CL_DEVICE_SINGLE_DEVICE_SHARED_MEM_CAPABILITIES_INTEL,
(CL_UNIFIED_SHARED_MEMORY_ACCESS_INTEL | CL_UNIFIED_SHARED_MEMORY_ATOMIC_ACCESS_INTEL)},
{CL_DEVICE_CROSS_DEVICE_SHARED_MEM_CAPABILITIES_INTEL,
(CL_UNIFIED_SHARED_MEMORY_ACCESS_INTEL | CL_UNIFIED_SHARED_MEMORY_ATOMIC_ACCESS_INTEL)},
{CL_DEVICE_SHARED_SYSTEM_MEM_CAPABILITIES_INTEL, 0}};
check(params);
}

4
opencl/test/unit_test/xe_hpg_core/excludes_ocl_xe_hpg_core.cpp
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2022 Intel Corporation
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@ -9,7 +9,5 @@
HWTEST_EXCLUDE_PRODUCT(BufferSetSurfaceTests, givenAlignedCacheableReadOnlyBufferThenChoseOclBufferPolicy, IGFX_XE_HPG_CORE);
HWTEST_EXCLUDE_PRODUCT(BufferSetSurfaceTests, givenBufferSetSurfaceThatMemoryIsUnalignedToCachelineButReadOnlyThenL3CacheShouldBeStillOn, IGFX_XE_HPG_CORE);
HWTEST_EXCLUDE_PRODUCT(XeHPAndLaterImageTests, givenCompressionWhenAppendingImageFromBufferThenTwoIsSetAsCompressionFormat, IGFX_XE_HPG_CORE);
HWTEST_EXCLUDE_PRODUCT(XeHPAndLaterImageTests, givenImageFromBufferWhenSettingSurfaceStateThenPickCompressionFormatFromDebugVariable, IGFX_XE_HPG_CORE);
HWTEST_EXCLUDE_PRODUCT(DeviceGetCapsTest, givenEnabledFtrPooledEuWhenCalculatingMaxEuPerSSThenDontIgnoreEuCountPerPoolMin, IGFX_XE_HPG_CORE);
HWTEST_EXCLUDE_PRODUCT(DeviceGetCapsTest, givenDeviceThatHasHighNumberOfExecutionUnitsWhenMaxWorkgroupSizeIsComputedItIsLimitedTo1024, IGFX_XE_HPG_CORE);

8
opencl/test/unit_test/xe_hpg_core/mtl/CMakeLists.txt
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@ -5,16 +5,8 @@
#
if(TESTS_MTL)
set(IGDRCL_SRCS_tests_xe_hpg_core_mtl_excludes
${CMAKE_CURRENT_SOURCE_DIR}/excludes_ocl_mtl.cpp
)
set_property(GLOBAL APPEND PROPERTY IGDRCL_SRCS_tests_excludes ${IGDRCL_SRCS_tests_xe_hpg_core_mtl_excludes})
set(IGDRCL_SRCS_tests_xe_hpg_core_mtl
${IGDRCL_SRCS_tests_xe_hpg_core_mtl_excludes}
${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
${CMAKE_CURRENT_SOURCE_DIR}/get_device_info_mtl.cpp
${CMAKE_CURRENT_SOURCE_DIR}/image_tests_mtl.cpp
${CMAKE_CURRENT_SOURCE_DIR}/test_cl_device_caps_mtl.cpp
)

12
opencl/test/unit_test/xe_hpg_core/mtl/excludes_ocl_mtl.cpp
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@ -1,12 +0,0 @@
/*
* Copyright (C) 2022-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/test/common/test_macros/hw_test_base.h"
HWTEST_EXCLUDE_PRODUCT(CommandStreamReceiverFlushTaskDg2AndLaterTests, givenProgramExtendedPipeControlPriorToNonPipelinedStateCommandEnabledWhenPerDssBackedBufferThenThereIsPipeControlPriorToIt_MatcherIsRTCapable, IGFX_METEORLAKE);
HWTEST_EXCLUDE_PRODUCT(CommandStreamReceiverFlushTaskXeHPAndLaterTests, givenProgramExtendedPipeControlPriorToNonPipelinedStateCommandEnabledAndStateSipWhenItIsRequiredThenThereIsPipeControlPriorToIt, IGFX_METEORLAKE);
HWTEST_EXCLUDE_PRODUCT(CommandStreamReceiverFlushTaskXeHPAndLaterTests, givenProgramExtendedPipeControlPriorToNonPipelinedStateCommandEnabledAndStateBaseAddressWhenItIsRequiredThenThereIsPipeControlPriorToIt, IGFX_METEORLAKE);

28
opencl/test/unit_test/xe_hpg_core/mtl/get_device_info_mtl.cpp
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@ -1,28 +0,0 @@
/*
* Copyright (C) 2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/test/common/test_macros/hw_test.h"
#include "opencl/test/unit_test/fixtures/device_info_fixture.h"
using namespace NEO;
HWTEST_EXCLUDE_PRODUCT(GetDeviceInfoMemCapabilitiesTest, GivenValidParametersWhenGetDeviceInfoIsCalledForXE_HP_COREThenClSuccessIsReturned, IGFX_METEORLAKE);
MTLTEST_F(GetDeviceInfoMemCapabilitiesTest, GivenValidParametersWhenGetDeviceInfoIsCalledForMTLThenClSuccessIsReturned) {
std::vector<TestParams> params = {
{CL_DEVICE_HOST_MEM_CAPABILITIES_INTEL, CL_UNIFIED_SHARED_MEMORY_ACCESS_INTEL | CL_UNIFIED_SHARED_MEMORY_ATOMIC_ACCESS_INTEL},
{CL_DEVICE_DEVICE_MEM_CAPABILITIES_INTEL,
(CL_UNIFIED_SHARED_MEMORY_ACCESS_INTEL | CL_UNIFIED_SHARED_MEMORY_ATOMIC_ACCESS_INTEL)},
{CL_DEVICE_SINGLE_DEVICE_SHARED_MEM_CAPABILITIES_INTEL,
(CL_UNIFIED_SHARED_MEMORY_ACCESS_INTEL | CL_UNIFIED_SHARED_MEMORY_ATOMIC_ACCESS_INTEL)},
{CL_DEVICE_CROSS_DEVICE_SHARED_MEM_CAPABILITIES_INTEL,
(CL_UNIFIED_SHARED_MEMORY_ACCESS_INTEL | CL_UNIFIED_SHARED_MEMORY_ATOMIC_ACCESS_INTEL)},
{CL_DEVICE_SHARED_SYSTEM_MEM_CAPABILITIES_INTEL, 0}};
check(params);
}

13
opencl/test/unit_test/xe_hpg_core/mtl/image_tests_mtl.cpp
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@ -1,13 +0,0 @@
/*
* Copyright (C) 2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/test/common/test_macros/hw_test.h"
using namespace NEO;
HWTEST_EXCLUDE_PRODUCT(XeHPAndLaterImageTests, givenCompressionWhenAppendingImageFromBufferThenTwoIsSetAsCompressionFormat, IGFX_METEORLAKE);
HWTEST_EXCLUDE_PRODUCT(XeHPAndLaterImageTests, givenImageFromBufferWhenSettingSurfaceStateThenPickCompressionFormatFromDebugVariable, IGFX_METEORLAKE);

10
shared/source/os_interface/product_helper.inl
View File

@ -291,7 +291,15 @@ bool ProductHelperHw<gfxProduct>::isAssignEngineRoundRobinSupported() const {
template <PRODUCT_FAMILY gfxProduct>
std::pair<bool, bool> ProductHelperHw<gfxProduct>::isPipeControlPriorToNonPipelinedStateCommandsWARequired(const HardwareInfo &hwInfo, bool isRcs, const ReleaseHelper *releaseHelper) const {
return {false, false};
auto isBasicWARequired = false;
if (releaseHelper) {
isBasicWARequired = releaseHelper->isPipeControlPriorToNonPipelinedStateCommandsWARequired();
}
auto isExtendedWARequired = false;
if (DebugManager.flags.ProgramExtendedPipeControlPriorToNonPipelinedStateCommand.get() != -1) {
isExtendedWARequired = DebugManager.flags.ProgramExtendedPipeControlPriorToNonPipelinedStateCommand.get();
}
return {isBasicWARequired, isExtendedWARequired};
}
template <PRODUCT_FAMILY gfxProduct>

12
shared/source/xe_hpc_core/os_agnostic_product_helper_xe_hpc_core.inl
View File

@ -26,18 +26,6 @@ bool ProductHelperHw<gfxProduct>::isTimestampWaitSupportedForEvents() const {
return true;
}
template <>
std::pair<bool, bool> ProductHelperHw<gfxProduct>::isPipeControlPriorToNonPipelinedStateCommandsWARequired(const HardwareInfo &hwInfo, bool isRcs, const ReleaseHelper *releaseHelper) const {
auto isBasicWARequired = false;
auto isExtendedWARequired = false;
if (DebugManager.flags.ProgramExtendedPipeControlPriorToNonPipelinedStateCommand.get() != -1) {
isExtendedWARequired = DebugManager.flags.ProgramExtendedPipeControlPriorToNonPipelinedStateCommand.get();
}
return {isBasicWARequired, isExtendedWARequired};
}
template <>
void ProductHelperHw<gfxProduct>::adjustSamplerState(void *sampler, const HardwareInfo &hwInfo) const {
using SAMPLER_STATE = typename XeHpcCoreFamily::SAMPLER_STATE;

9
shared/source/xe_hpg_core/xe_lpg/os_agnostic_product_helper_xe_lpg.inl
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@ -44,15 +44,6 @@ bool ProductHelperHw<gfxProduct>::isDirectSubmissionConstantCacheInvalidationNee
return true;
}
template <>
std::pair<bool, bool> ProductHelperHw<gfxProduct>::isPipeControlPriorToNonPipelinedStateCommandsWARequired(const HardwareInfo &hwInfo, bool isRcs, const ReleaseHelper *releaseHelper) const {
UNRECOVERABLE_IF(!releaseHelper);
auto isBasicWARequired = releaseHelper->isPipeControlPriorToNonPipelinedStateCommandsWARequired();
auto isExtendedWARequired = false;
return {isBasicWARequired, isExtendedWARequired};
}
template <>
bool ProductHelperHw<gfxProduct>::isInitBuiltinAsyncSupported(const HardwareInfo &hwInfo) const {
return false;