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fix: signal in-order counter for Barrier after Event 

Related-To: NEO-7966

Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
This commit is contained in:
Dunajski, Bartosz 2023-11-03 12:52:28 +00:00 committed by Compute-Runtime-Automation
parent dcb351e9dd
commit 1c44f02e84
2 changed files with 37 additions and 21 deletions
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33
level_zero/core/source/cmdlist/cmdlist_hw.inl
View File

@ -3113,29 +3113,30 @@ ze_result_t CommandListCoreFamily<gfxCoreFamily>::appendBarrier(ze_event_handle_
appendEventForProfiling(signalEvent, true, false);
if (this->isInOrderExecutionEnabled()) {
appendSignalInOrderDependencyCounter();
} else if (isCopyOnly()) {
NEO::MiFlushArgs args{this->dummyBlitWa};
uint64_t gpuAddress = 0u;
TaskCountType value = 0u;
if (this->cmdListType == TYPE_IMMEDIATE) {
args.commandWithPostSync = true;
gpuAddress = this->csr->getBarrierCountGpuAddress();
value = this->csr->getNextBarrierCount() + 1;
commandContainer.addToResidencyContainer(this->csr->getTagAllocation());
}
if (!this->isInOrderExecutionEnabled()) {
if (isCopyOnly()) {
NEO::MiFlushArgs args{this->dummyBlitWa};
uint64_t gpuAddress = 0u;
TaskCountType value = 0u;
if (this->cmdListType == TYPE_IMMEDIATE) {
args.commandWithPostSync = true;
gpuAddress = this->csr->getBarrierCountGpuAddress();
value = this->csr->getNextBarrierCount() + 1;
commandContainer.addToResidencyContainer(this->csr->getTagAllocation());
}
NEO::EncodeMiFlushDW<GfxFamily>::programWithWa(*commandContainer.getCommandStream(), gpuAddress, value, args);
makeResidentDummyAllocation();
} else {
appendComputeBarrierCommand();
NEO::EncodeMiFlushDW<GfxFamily>::programWithWa(*commandContainer.getCommandStream(), gpuAddress, value, args);
makeResidentDummyAllocation();
} else {
appendComputeBarrierCommand();
}
}
addToMappedEventList(signalEvent);
appendSignalEventPostWalker(signalEvent, this->isInOrderExecutionEnabled());
if (isInOrderExecutionEnabled()) {
appendSignalInOrderDependencyCounter();
handleInOrderDependencyCounter(signalEvent, false);
}

25
level_zero/core/test/unit_tests/sources/cmdlist/test_cmdlist_append_launch_kernel_3.cpp
View File

@ -3288,8 +3288,9 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenProgrammingAppendBarrierWitho
EXPECT_EQ(0u, sdiCmd->getDataDword1());
}
HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenProgrammingAppendBarrierWithoutWaitlistAndRegularEventThenSignalSyncAllocation, IsAtLeastXeHpCore) {
using PIPE_CONTROL = typename FamilyType::PIPE_CONTROL;
HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenProgrammingAppendBarrierWithoutWaitlistAndRegularEventThenSignalSyncAllocation, IsAtLeastSkl) {
using MI_NOOP = typename FamilyType::MI_NOOP;
using MI_BATCH_BUFFER_END = typename FamilyType::MI_BATCH_BUFFER_END;
using MI_STORE_DATA_IMM = typename FamilyType::MI_STORE_DATA_IMM;
auto immCmdList = createImmCmdList<gfxCoreFamily>();
@ -3314,10 +3315,24 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenProgrammingAppendBarrierWitho
ptrOffset(cmdStream->getCpuBase(), offset),
(cmdStream->getUsed() - offset)));
auto sdiItor = find<MI_STORE_DATA_IMM *>(cmdList.begin(), cmdList.end());
ASSERT_NE(cmdList.end(), sdiItor);
auto cmd = cmdList.rbegin();
MI_STORE_DATA_IMM *sdiCmd = nullptr;
auto sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(*sdiItor);
while (cmd != cmdList.rend()) {
sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(*cmd);
if (sdiCmd) {
break;
}
if (genCmdCast<MI_NOOP *>(*cmd) || genCmdCast<MI_BATCH_BUFFER_END *>(*cmd)) {
cmd++;
continue;
}
ASSERT_TRUE(false);
}
ASSERT_NE(nullptr, sdiCmd);
EXPECT_EQ(immCmdList->inOrderExecInfo->inOrderDependencyCounterAllocation.getGpuAddress(), sdiCmd->getAddress());
EXPECT_EQ(immCmdList->isQwordInOrderCounter(), sdiCmd->getStoreQword());