fix: signal in-order counter for Barrier after Event
Related-To: NEO-7966 Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
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@ -3113,29 +3113,30 @@ ze_result_t CommandListCoreFamily<gfxCoreFamily>::appendBarrier(ze_event_handle_
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appendEventForProfiling(signalEvent, true, false);
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appendEventForProfiling(signalEvent, true, false);
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if (this->isInOrderExecutionEnabled()) {
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if (!this->isInOrderExecutionEnabled()) {
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appendSignalInOrderDependencyCounter();
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if (isCopyOnly()) {
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} else if (isCopyOnly()) {
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NEO::MiFlushArgs args{this->dummyBlitWa};
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NEO::MiFlushArgs args{this->dummyBlitWa};
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uint64_t gpuAddress = 0u;
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uint64_t gpuAddress = 0u;
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TaskCountType value = 0u;
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TaskCountType value = 0u;
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if (this->cmdListType == TYPE_IMMEDIATE) {
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if (this->cmdListType == TYPE_IMMEDIATE) {
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args.commandWithPostSync = true;
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args.commandWithPostSync = true;
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gpuAddress = this->csr->getBarrierCountGpuAddress();
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gpuAddress = this->csr->getBarrierCountGpuAddress();
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value = this->csr->getNextBarrierCount() + 1;
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value = this->csr->getNextBarrierCount() + 1;
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commandContainer.addToResidencyContainer(this->csr->getTagAllocation());
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commandContainer.addToResidencyContainer(this->csr->getTagAllocation());
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}
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}
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NEO::EncodeMiFlushDW<GfxFamily>::programWithWa(*commandContainer.getCommandStream(), gpuAddress, value, args);
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NEO::EncodeMiFlushDW<GfxFamily>::programWithWa(*commandContainer.getCommandStream(), gpuAddress, value, args);
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makeResidentDummyAllocation();
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makeResidentDummyAllocation();
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} else {
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} else {
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appendComputeBarrierCommand();
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appendComputeBarrierCommand();
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}
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}
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}
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addToMappedEventList(signalEvent);
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addToMappedEventList(signalEvent);
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appendSignalEventPostWalker(signalEvent, this->isInOrderExecutionEnabled());
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appendSignalEventPostWalker(signalEvent, this->isInOrderExecutionEnabled());
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if (isInOrderExecutionEnabled()) {
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if (isInOrderExecutionEnabled()) {
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appendSignalInOrderDependencyCounter();
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handleInOrderDependencyCounter(signalEvent, false);
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handleInOrderDependencyCounter(signalEvent, false);
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}
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}
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@ -3288,8 +3288,9 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenProgrammingAppendBarrierWitho
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EXPECT_EQ(0u, sdiCmd->getDataDword1());
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EXPECT_EQ(0u, sdiCmd->getDataDword1());
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}
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}
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HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenProgrammingAppendBarrierWithoutWaitlistAndRegularEventThenSignalSyncAllocation, IsAtLeastXeHpCore) {
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HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenProgrammingAppendBarrierWithoutWaitlistAndRegularEventThenSignalSyncAllocation, IsAtLeastSkl) {
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using PIPE_CONTROL = typename FamilyType::PIPE_CONTROL;
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using MI_NOOP = typename FamilyType::MI_NOOP;
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using MI_BATCH_BUFFER_END = typename FamilyType::MI_BATCH_BUFFER_END;
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using MI_STORE_DATA_IMM = typename FamilyType::MI_STORE_DATA_IMM;
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using MI_STORE_DATA_IMM = typename FamilyType::MI_STORE_DATA_IMM;
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auto immCmdList = createImmCmdList<gfxCoreFamily>();
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auto immCmdList = createImmCmdList<gfxCoreFamily>();
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@ -3314,10 +3315,24 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenProgrammingAppendBarrierWitho
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ptrOffset(cmdStream->getCpuBase(), offset),
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ptrOffset(cmdStream->getCpuBase(), offset),
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(cmdStream->getUsed() - offset)));
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(cmdStream->getUsed() - offset)));
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auto sdiItor = find<MI_STORE_DATA_IMM *>(cmdList.begin(), cmdList.end());
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auto cmd = cmdList.rbegin();
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ASSERT_NE(cmdList.end(), sdiItor);
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MI_STORE_DATA_IMM *sdiCmd = nullptr;
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auto sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(*sdiItor);
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while (cmd != cmdList.rend()) {
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sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(*cmd);
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if (sdiCmd) {
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break;
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}
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if (genCmdCast<MI_NOOP *>(*cmd) || genCmdCast<MI_BATCH_BUFFER_END *>(*cmd)) {
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cmd++;
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continue;
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}
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ASSERT_TRUE(false);
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}
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ASSERT_NE(nullptr, sdiCmd);
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EXPECT_EQ(immCmdList->inOrderExecInfo->inOrderDependencyCounterAllocation.getGpuAddress(), sdiCmd->getAddress());
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EXPECT_EQ(immCmdList->inOrderExecInfo->inOrderDependencyCounterAllocation.getGpuAddress(), sdiCmd->getAddress());
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EXPECT_EQ(immCmdList->isQwordInOrderCounter(), sdiCmd->getStoreQword());
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EXPECT_EQ(immCmdList->isQwordInOrderCounter(), sdiCmd->getStoreQword());
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