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Add post sync capability to implicit scaling barrier

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Related-To: NEO-6262

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
This commit is contained in:
Zbigniew Zdanowicz
2021-11-10 19:56:42 +00:00
committed by Compute-Runtime-Automation
parent d15eed035b
commit 3b556a5e44
13 changed files with 726 additions and 32 deletions
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8
shared/source/command_container/implicit_scaling.h
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@ -15,6 +15,7 @@ struct WalkerPartitionArgs;
}
namespace NEO {
struct HardwareInfo;
class LinearStream;
struct PipeControlArgs;
@ -54,10 +55,15 @@ struct ImplicitScalingDispatch {
static bool &getPipeControlStallRequired();
static size_t getBarrierSize(bool apiSelfCleanup);
static size_t getBarrierSize(const HardwareInfo &hwInfo,
bool apiSelfCleanup,
bool usePostSync);
static void dispatchBarrierCommands(LinearStream &commandStream,
const DeviceBitfield &devices,
PipeControlArgs &flushArgs,
const HardwareInfo &hwInfo,
uint64_t gpuAddress,
uint64_t immediateData,
bool apiSelfCleanup,
bool useSecondaryBatchBuffer);