Media
/
compute-runtime
mirror of https://github.com/intel/compute-runtime.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Update i915 headers 

Sync to https://github.com/intel-gpu/drm-uapi-helper/releases/tag/v2.0-rc11


Signed-off-by: Naklicki, Mateusz <mateusz.naklicki@intel.com>
This commit is contained in:
Naklicki, Mateusz 2022-03-24 18:28:22 +00:00 committed by Compute-Runtime-Automation
parent 0fa923dff6
commit 5176cfb660
2 changed files with 231 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

184
third_party/uapi/prelim/drm/i915_drm.h vendored
View File

@ -1409,12 +1409,11 @@ struct drm_i915_gem_busy {
* reading from the object simultaneously.
*
* The value of each engine class is the same as specified in the
* I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
* I915_CONTEXT_PARAM_ENGINES context parameter and via perf, i.e.
* I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
* reported as active itself. Some hardware may have parallel
* execution engines, e.g. multiple media engines, which are
* mapped to the same class identifier and so are not separately
* reported for busyness.
* Some hardware may have parallel execution engines, e.g. multiple
* media engines, which are mapped to the same class identifier and so
* are not separately reported for busyness.
*
* Caveat emptor:
* Only the boolean result of this query is reliable; that is whether
@ -1875,6 +1874,69 @@ struct drm_i915_gem_context_param_sseu {
__u32 rsvd;
};
/**
* DOC: Virtual Engine uAPI
*
* Virtual engine is a concept where userspace is able to configure a set of
* physical engines, submit a batch buffer, and let the driver execute it on any
* engine from the set as it sees fit.
*
* This is primarily useful on parts which have multiple instances of a same
* class engine, like for example GT3+ Skylake parts with their two VCS engines.
*
* For instance userspace can enumerate all engines of a certain class using the
* previously described `Engine Discovery uAPI`_. After that userspace can
* create a GEM context with a placeholder slot for the virtual engine (using
* `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class
* and instance respectively) and finally using the
* `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in
* the same reserved slot.
*
* Example of creating a virtual engine and submitting a batch buffer to it:
*
* .. code-block:: C
*
* I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = {
* .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE,
* .engine_index = 0, // Place this virtual engine into engine map slot 0
* .num_siblings = 2,
* .engines = { { I915_ENGINE_CLASS_VIDEO, 0 },
* { I915_ENGINE_CLASS_VIDEO, 1 }, },
* };
* I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
* .engines = { { I915_ENGINE_CLASS_INVALID,
* I915_ENGINE_CLASS_INVALID_NONE } },
* .extensions = to_user_pointer(&virtual), // Chains after load_balance extension
* };
* struct drm_i915_gem_context_create_ext_setparam p_engines = {
* .base = {
* .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
* },
* .param = {
* .param = I915_CONTEXT_PARAM_ENGINES,
* .value = to_user_pointer(&engines),
* .size = sizeof(engines),
* },
* };
* struct drm_i915_gem_context_create_ext create = {
* .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
* .extensions = to_user_pointer(&p_engines);
* };
*
* ctx_id = gem_context_create_ext(drm_fd, &create);
*
* // Now we have created a GEM context with its engine map containing a
* // single virtual engine. Submissions to this slot can go either to
* // vcs0 or vcs1, depending on the load balancing algorithm used inside
* // the driver. The load balancing is dynamic from one batch buffer to
* // another and transparent to userspace.
*
* ...
* execbuf.rsvd1 = ctx_id;
* execbuf.flags = 0; // Submits to index 0 which is the virtual engine
* gem_execbuf(drm_fd, &execbuf);
*/
/*
* i915_context_engines_load_balance:
*
@ -2222,14 +2284,52 @@ struct drm_i915_reset_stats {
__u32 pad;
};
/**
* struct drm_i915_gem_userptr - Create GEM object from user allocated memory.
*
* Userptr objects have several restrictions on what ioctls can be used with the
* object handle.
*/
struct drm_i915_gem_userptr {
/**
* @user_ptr: The pointer to the allocated memory.
*
* Needs to be aligned to PAGE_SIZE.
*/
__u64 user_ptr;
/**
* @user_size:
*
* The size in bytes for the allocated memory. This will also become the
* object size.
*
* Needs to be aligned to PAGE_SIZE, and should be at least PAGE_SIZE,
* or larger.
*/
__u64 user_size;
/**
* @flags:
*
* Supported flags:
*
* I915_USERPTR_READ_ONLY:
*
* Mark the object as readonly, this also means GPU access can only be
* readonly. This is only supported on HW which supports readonly access
* through the GTT. If the HW can't support readonly access, an error is
* returned.
*
* I915_USERPTR_UNSYNCHRONIZED:
*
* NOT USED. Setting this flag will result in an error.
*/
__u32 flags;
#define I915_USERPTR_READ_ONLY 0x1
#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
/**
* Returned handle for the object.
* @handle: Returned handle for the object.
*
* Object handles are nonzero.
*/
@ -2612,6 +2712,76 @@ struct drm_i915_query_topology_info {
__u8 data[];
};
/**
* DOC: Engine Discovery uAPI
*
* Engine discovery uAPI is a way of enumerating physical engines present in a
* GPU associated with an open i915 DRM file descriptor. This supersedes the old
* way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like
* `I915_PARAM_HAS_BLT`.
*
* The need for this interface came starting with Icelake and newer GPUs, which
* started to establish a pattern of having multiple engines of a same class,
* where not all instances were always completely functionally equivalent.
*
* Entry point for this uapi is `DRM_IOCTL_I915_QUERY` with the
* `DRM_I915_QUERY_ENGINE_INFO` as the queried item id.
*
* Example for getting the list of engines:
*
* .. code-block:: C
*
* struct drm_i915_query_engine_info *info;
* struct drm_i915_query_item item = {
* .query_id = DRM_I915_QUERY_ENGINE_INFO;
* };
* struct drm_i915_query query = {
* .num_items = 1,
* .items_ptr = (uintptr_t)&item,
* };
* int err, i;
*
* // First query the size of the blob we need, this needs to be large
* // enough to hold our array of engines. The kernel will fill out the
* // item.length for us, which is the number of bytes we need.
* //
* // Alternatively a large buffer can be allocated straight away enabling
* // querying in one pass, in which case item.length should contain the
* // length of the provided buffer.
* err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
* if (err) ...
*
* info = calloc(1, item.length);
* // Now that we allocated the required number of bytes, we call the ioctl
* // again, this time with the data_ptr pointing to our newly allocated
* // blob, which the kernel can then populate with info on all engines.
* item.data_ptr = (uintptr_t)&info,
*
* err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
* if (err) ...
*
* // We can now access each engine in the array
* for (i = 0; i < info->num_engines; i++) {
* struct drm_i915_engine_info einfo = info->engines[i];
* u16 class = einfo.engine.class;
* u16 instance = einfo.engine.instance;
* ....
* }
*
* free(info);
*
* Each of the enumerated engines, apart from being defined by its class and
* instance (see `struct i915_engine_class_instance`), also can have flags and
* capabilities defined as documented in i915_drm.h.
*
* For instance video engines which support HEVC encoding will have the
* `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set.
*
* Engine discovery only fully comes to its own when combined with the new way
* of addressing engines when submitting batch buffers using contexts with
* engine maps configured.
*/
/**
* struct drm_i915_engine_info
*
@ -2850,4 +3020,4 @@ struct drm_i915_query_memory_regions {
}
#endif
#endif /* _I915_DRM_H_ */
#endif /* _I915_DRM_H_ */

69
third_party/uapi/prelim/drm/i915_drm_prelim.h vendored
View File

@ -265,9 +265,12 @@ struct prelim_drm_i915_gem_create_ext {
*/
__u32 handle;
__u32 pad;
#define PRELIM_I915_GEM_CREATE_EXT_SETPARAM (PRELIM_I915_USER_EXT | 1)
#define PRELIM_I915_GEM_CREATE_EXT_FLAGS_UNKNOWN \
(~PRELIM_I915_GEM_CREATE_EXT_SETPARAM)
#define PRELIM_I915_GEM_CREATE_EXT_VM_PRIVATE (PRELIM_I915_USER_EXT | 3)
#define PRELIM_I915_GEM_CREATE_EXT_FLAGS_UNKNOWN \
(~(PRELIM_I915_GEM_CREATE_EXT_SETPARAM | \
PRELIM_I915_GEM_CREATE_EXT_VM_PRIVATE))
__u64 extensions;
};
@ -309,6 +312,13 @@ struct prelim_drm_i915_gem_create_ext_setparam {
struct prelim_drm_i915_gem_object_param param;
};
struct prelim_drm_i915_gem_create_ext_vm_private {
/** @base: Extension link. See struct i915_user_extension. */
struct i915_user_extension base;
/** @vm_id: Id of the VM to which Object is private */
__u32 vm_id;
};
#define PRELIM_PERF_VERSION (1000)
/**
@ -405,18 +415,36 @@ struct prelim_drm_i915_query_item {
* query's item.data_ptr directly if the allocated length is big enough
* For details about table format and content see intel_hwconfig_types.h
*/
#define PRELIM_DRM_I915_QUERY_HWCONFIG_TABLE (PRELIM_DRM_I915_QUERY | 6)
#define PRELIM_DRM_I915_QUERY_GEOMETRY_SLICES (PRELIM_DRM_I915_QUERY | 7)
#define PRELIM_DRM_I915_QUERY_COMPUTE_SLICES (PRELIM_DRM_I915_QUERY | 8)
#define PRELIM_DRM_I915_QUERY_HWCONFIG_TABLE (PRELIM_DRM_I915_QUERY | 6)
/**
* Query Geometry Subslices: returns the items found in query_topology info
* with a mask for geometry_subslice_mask applied
*
* @flags:
*
* bits 0:7 must be a valid engine class and bits 8:15 must be a valid engine
* instance.
*/
#define PRELIM_DRM_I915_QUERY_GEOMETRY_SUBSLICES (PRELIM_DRM_I915_QUERY | 7)
#define PRELIM_DRM_I915_QUERY_GEOMETRY_SLICES PRELIM_DRM_I915_QUERY_GEOMETRY_SUBSLICES
/**
* Query Compute Subslices: returns the items found in query_topology info
* with a mask for compute_subslice_mask applied
*
* @flags:
*
* bits 0:7 must be a valid engine class and bits 8:15 must be a valid engine
* instance.
*/
#define PRELIM_DRM_I915_QUERY_COMPUTE_SUBSLICES (PRELIM_DRM_I915_QUERY | 8)
#define PRELIM_DRM_I915_QUERY_COMPUTE_SLICES PRELIM_DRM_I915_QUERY_COMPUTE_SUBSLICES
/**
* Query Command Streamer timestamp register.
*/
#define PRELIM_DRM_I915_QUERY_CS_CYCLES (PRELIM_DRM_I915_QUERY | 9)
#define PRELIM_DRM_I915_QUERY_FABRIC_INFO (PRELIM_DRM_I915_QUERY | 11)
#define PRELIM_DRM_I915_QUERY_ENGINE_INFO (PRELIM_DRM_I915_QUERY | 13)
#define PRELIM_DRM_I915_QUERY_L3_BANK_COUNT (PRELIM_DRM_I915_QUERY | 14)
#define PRELIM_DRM_I915_QUERY_CS_CYCLES (PRELIM_DRM_I915_QUERY | 9)
#define PRELIM_DRM_I915_QUERY_FABRIC_INFO (PRELIM_DRM_I915_QUERY | 11)
#define PRELIM_DRM_I915_QUERY_ENGINE_INFO (PRELIM_DRM_I915_QUERY | 13)
#define PRELIM_DRM_I915_QUERY_L3_BANK_COUNT (PRELIM_DRM_I915_QUERY | 14)
};
/*
@ -558,9 +586,11 @@ struct prelim_drm_i915_gem_context_param {
};
struct prelim_drm_i915_gem_context_create_ext {
/* Depricated in favor of PRELIM_I915_CONTEXT_CREATE_FLAGS_LONG_RUNNING */
#define PRELIM_I915_CONTEXT_CREATE_FLAGS_ULLS (1u << 31)
#define PRELIM_I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
(~(PRELIM_I915_CONTEXT_CREATE_FLAGS_ULLS | ~I915_CONTEXT_CREATE_FLAGS_UNKNOWN))
#define PRELIM_I915_CONTEXT_CREATE_FLAGS_LONG_RUNNING (1u << 31)
#define PRELIM_I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
(~(PRELIM_I915_CONTEXT_CREATE_FLAGS_LONG_RUNNING | ~I915_CONTEXT_CREATE_FLAGS_UNKNOWN))
};
/*
@ -1054,7 +1084,7 @@ struct prelim_drm_i915_gem_vm_bind {
/** BO handle or file descriptor. Set 'fd' to -1 for system pages **/
union {
__u32 handle;
__u32 handle; /* For unbind, it is reserved and must be 0 */
__s32 fd;
};
@ -1206,6 +1236,7 @@ struct prelim_drm_i915_gem_execbuffer_ext_user_fence {
__u64 rsvd;
};
/* Deprecated in favor of prelim_drm_i915_vm_bind_ext_user_fence */
struct prelim_drm_i915_vm_bind_ext_sync_fence {
#define PRELIM_I915_VM_BIND_EXT_SYNC_FENCE (PRELIM_I915_USER_EXT | 0)
struct i915_user_extension base;
@ -1213,6 +1244,14 @@ struct prelim_drm_i915_vm_bind_ext_sync_fence {
__u64 val;
};
struct prelim_drm_i915_vm_bind_ext_user_fence {
#define PRELIM_I915_VM_BIND_EXT_USER_FENCE (PRELIM_I915_USER_EXT | 3)
struct i915_user_extension base;
__u64 addr;
__u64 val;
__u64 rsvd;
};
struct prelim_drm_i915_gem_vm_control {
#define PRELIM_I915_VM_CREATE_FLAGS_DISABLE_SCRATCH (1 << 16)
#define PRELIM_I915_VM_CREATE_FLAGS_ENABLE_PAGE_FAULT (1 << 17)
@ -1314,4 +1353,4 @@ struct prelim_drm_i915_gem_vm_param {
__u64 value;
};
#endif /* __I915_DRM_PRELIM_H__ */
#endif /* __I915_DRM_PRELIM_H__ */