Media
/
compute-runtime
mirror of https://github.com/intel/compute-runtime.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

feature: update Xe KMD header 

xe_drm.h header is taken from commit e51e857ffad411e1b78821866e9f02187345a11a
https://gitlab.freedesktop.org/drm/xe/kernel

Related-To: NEO-8324

Signed-off-by: Francois Dugast <francois.dugast@intel.com>
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
This commit is contained in:
Francois Dugast 2023-09-13 18:58:57 +00:00 committed by Compute-Runtime-Automation
parent 7c1f5585d7
commit 670eaeb050
3 changed files with 465 additions and 209 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

62
shared/source/os_interface/linux/xe/ioctl_helper_xe.cpp
View File

@ -42,14 +42,6 @@
namespace NEO { namespace NEO {
static_assert(DRM_XE_ENGINE_CLASS_RENDER == I915_ENGINE_CLASS_RENDER);
static_assert(DRM_XE_ENGINE_CLASS_COPY == I915_ENGINE_CLASS_COPY);
static_assert(DRM_XE_ENGINE_CLASS_VIDEO_DECODE == I915_ENGINE_CLASS_VIDEO);
static_assert(DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE == I915_ENGINE_CLASS_VIDEO_ENHANCE);
static_assert(DRM_XE_ENGINE_CLASS_COMPUTE == I915_ENGINE_CLASS_COMPUTE);
static_assert(XE_MEM_REGION_CLASS_VRAM == I915_MEMORY_CLASS_DEVICE);
static_assert(XE_MEM_REGION_CLASS_SYSMEM == I915_MEMORY_CLASS_SYSTEM);
int IoctlHelperXe::xeGetQuery(Query *data) { int IoctlHelperXe::xeGetQuery(Query *data) {
if (data->numItems == 1) { if (data->numItems == 1) {
QueryItem *queryItem = (QueryItem *)data->itemsPtr; QueryItem *queryItem = (QueryItem *)data->itemsPtr;
@ -165,13 +157,8 @@ bool IoctlHelperXe::initialize() {
XE_QUERY_CONFIG_FLAGS_HAS_VRAM XE_QUERY_CONFIG_FLAGS_HAS_VRAM
? "ON" ? "ON"
: "OFF"); : "OFF");
xeLog(" XE_QUERY_CONFIG_FLAGS_USE_GUC\t\t%s\n", xeLog("XE_QUERY_CONFIG_MIN_ALIGNMENT\t\t%#llx\n",
config->info[XE_QUERY_CONFIG_FLAGS] & config->info[XE_QUERY_CONFIG_MIN_ALIGNMENT]);
XE_QUERY_CONFIG_FLAGS_USE_GUC
? "ON"
: "OFF");
xeLog("XE_QUERY_CONFIG_MIN_ALIGNEMENT\t\t%#llx\n",
config->info[XE_QUERY_CONFIG_MIN_ALIGNEMENT]);
xeLog("XE_QUERY_CONFIG_VA_BITS\t\t%#llx\n", xeLog("XE_QUERY_CONFIG_VA_BITS\t\t%#llx\n",
config->info[XE_QUERY_CONFIG_VA_BITS]); config->info[XE_QUERY_CONFIG_VA_BITS]);
xeLog("XE_QUERY_CONFIG_GT_COUNT\t\t%llu\n", xeLog("XE_QUERY_CONFIG_GT_COUNT\t\t%llu\n",
@ -275,7 +262,7 @@ std::unique_ptr<EngineInfo> IoctlHelperXe::createEngineInfo(bool isSysmanEnabled
return std::make_unique<EngineInfo>(&drm, enginesPerTile); return std::make_unique<EngineInfo>(&drm, enginesPerTile);
} }
inline MemoryRegion createMemoryRegionFromXeMemRegion(const drm_xe_query_mem_usage::drm_xe_query_mem_region &xeMemRegion) { inline MemoryRegion createMemoryRegionFromXeMemRegion(const drm_xe_query_mem_region &xeMemRegion) {
MemoryRegion memoryRegion{}; MemoryRegion memoryRegion{};
memoryRegion.region.memoryInstance = xeMemRegion.instance; memoryRegion.region.memoryInstance = xeMemRegion.instance;
memoryRegion.region.memoryClass = xeMemRegion.mem_class; memoryRegion.region.memoryClass = xeMemRegion.mem_class;
@ -296,7 +283,7 @@ std::unique_ptr<MemoryInfo> IoctlHelperXe::createMemoryInfo() {
auto xeMemUsageData = reinterpret_cast<drm_xe_query_mem_usage *>(memUsageData.data()); auto xeMemUsageData = reinterpret_cast<drm_xe_query_mem_usage *>(memUsageData.data());
auto xeGtsData = reinterpret_cast<drm_xe_query_gts *>(gtsData.data()); auto xeGtsData = reinterpret_cast<drm_xe_query_gts *>(gtsData.data());
std::array<drm_xe_query_mem_usage::drm_xe_query_mem_region *, 64> memoryRegionInstances{}; std::array<drm_xe_query_mem_region *, 64> memoryRegionInstances{};
for (auto i = 0u; i < xeMemUsageData->num_regions; i++) { for (auto i = 0u; i < xeMemUsageData->num_regions; i++) {
auto &region = xeMemUsageData->regions[i]; auto &region = xeMemUsageData->regions[i];
@ -622,7 +609,7 @@ int IoctlHelperXe::execBuffer(ExecBuffer *execBuffer, uint64_t completionGpuAddr
sync[0].timeline_value = counterValue; sync[0].timeline_value = counterValue;
struct drm_xe_exec exec = {}; struct drm_xe_exec exec = {};
exec.engine_id = engine; exec.exec_queue_id = engine;
exec.num_syncs = 1; exec.num_syncs = 1;
exec.syncs = reinterpret_cast<uintptr_t>(&sync); exec.syncs = reinterpret_cast<uintptr_t>(&sync);
exec.address = obj->offset + d->batch_start_offset; exec.address = obj->offset + d->batch_start_offset;
@ -801,9 +788,9 @@ unsigned int IoctlHelperXe::getIoctlRequestValue(DrmIoctl ioctlRequest) const {
case DrmIoctl::Query: case DrmIoctl::Query:
RETURN_ME(DRM_IOCTL_XE_DEVICE_QUERY); RETURN_ME(DRM_IOCTL_XE_DEVICE_QUERY);
case DrmIoctl::GemContextCreateExt: case DrmIoctl::GemContextCreateExt:
RETURN_ME(DRM_IOCTL_XE_ENGINE_CREATE); RETURN_ME(DRM_IOCTL_XE_EXEC_QUEUE_CREATE);
case DrmIoctl::GemContextDestroy: case DrmIoctl::GemContextDestroy:
RETURN_ME(DRM_IOCTL_XE_ENGINE_DESTROY); RETURN_ME(DRM_IOCTL_XE_EXEC_QUEUE_DESTROY);
case DrmIoctl::GemWaitUserFence: case DrmIoctl::GemWaitUserFence:
RETURN_ME(DRM_IOCTL_XE_WAIT_USER_FENCE); RETURN_ME(DRM_IOCTL_XE_WAIT_USER_FENCE);
case DrmIoctl::PrimeFdToHandle: case DrmIoctl::PrimeFdToHandle:
@ -823,22 +810,21 @@ int IoctlHelperXe::getDrmParamValue(DrmParam drmParam) const {
switch (drmParam) { switch (drmParam) {
case DrmParam::MemoryClassDevice: case DrmParam::MemoryClassDevice:
return I915_MEMORY_CLASS_DEVICE; return XE_MEM_REGION_CLASS_VRAM;
case DrmParam::MemoryClassSystem: case DrmParam::MemoryClassSystem:
return I915_MEMORY_CLASS_SYSTEM; return XE_MEM_REGION_CLASS_SYSMEM;
case DrmParam::EngineClassRender: case DrmParam::EngineClassRender:
return drm_i915_gem_engine_class::I915_ENGINE_CLASS_RENDER; return DRM_XE_ENGINE_CLASS_RENDER;
case DrmParam::EngineClassCopy: case DrmParam::EngineClassCopy:
return drm_i915_gem_engine_class::I915_ENGINE_CLASS_COPY; return DRM_XE_ENGINE_CLASS_COPY;
case DrmParam::EngineClassVideo: case DrmParam::EngineClassVideo:
return drm_i915_gem_engine_class::I915_ENGINE_CLASS_VIDEO; return DRM_XE_ENGINE_CLASS_VIDEO_DECODE;
case DrmParam::EngineClassVideoEnhance: case DrmParam::EngineClassVideoEnhance:
return drm_i915_gem_engine_class::I915_ENGINE_CLASS_VIDEO_ENHANCE; return DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE;
case DrmParam::EngineClassCompute: case DrmParam::EngineClassCompute:
return prelim_drm_i915_gem_engine_class::PRELIM_I915_ENGINE_CLASS_COMPUTE; return DRM_XE_ENGINE_CLASS_COMPUTE;
case DrmParam::EngineClassInvalid: case DrmParam::EngineClassInvalid:
return drm_i915_gem_engine_class::I915_ENGINE_CLASS_INVALID; return -1;
default: default:
return getDrmParamValueBase(drmParam); return getDrmParamValueBase(drmParam);
@ -873,9 +859,9 @@ std::string IoctlHelperXe::getIoctlString(DrmIoctl ioctlRequest) const {
case DrmIoctl::Query: case DrmIoctl::Query:
STRINGIFY_ME(DRM_IOCTL_XE_DEVICE_QUERY); STRINGIFY_ME(DRM_IOCTL_XE_DEVICE_QUERY);
case DrmIoctl::GemContextCreateExt: case DrmIoctl::GemContextCreateExt:
STRINGIFY_ME(DRM_IOCTL_XE_ENGINE_CREATE); STRINGIFY_ME(DRM_IOCTL_XE_EXEC_QUEUE_CREATE);
case DrmIoctl::GemContextDestroy: case DrmIoctl::GemContextDestroy:
STRINGIFY_ME(DRM_IOCTL_XE_ENGINE_DESTROY); STRINGIFY_ME(DRM_IOCTL_XE_EXEC_QUEUE_DESTROY);
case DrmIoctl::GemWaitUserFence: case DrmIoctl::GemWaitUserFence:
STRINGIFY_ME(DRM_IOCTL_XE_WAIT_USER_FENCE); STRINGIFY_ME(DRM_IOCTL_XE_WAIT_USER_FENCE);
case DrmIoctl::PrimeFdToHandle: case DrmIoctl::PrimeFdToHandle:
@ -948,8 +934,8 @@ int IoctlHelperXe::ioctl(DrmIoctl request, void *arg) {
} break; } break;
case DrmIoctl::GemContextDestroy: { case DrmIoctl::GemContextDestroy: {
GemContextDestroy *d = static_cast<GemContextDestroy *>(arg); GemContextDestroy *d = static_cast<GemContextDestroy *>(arg);
struct drm_xe_engine_destroy destroy = {}; struct drm_xe_exec_queue_destroy destroy = {};
destroy.engine_id = d->contextId; destroy.exec_queue_id = d->contextId;
if (d->contextId != 0xffffffff) if (d->contextId != 0xffffffff)
ret = IoctlHelper::ioctl(request, &destroy); ret = IoctlHelper::ioctl(request, &destroy);
else else
@ -1136,7 +1122,7 @@ void IoctlHelperXe::xeShowBindTable() {
} }
int IoctlHelperXe::createDrmContext(Drm &drm, OsContextLinux &osContext, uint32_t drmVmId, uint32_t deviceIndex) { int IoctlHelperXe::createDrmContext(Drm &drm, OsContextLinux &osContext, uint32_t drmVmId, uint32_t deviceIndex) {
struct drm_xe_engine_create create = {}; struct drm_xe_exec_queue_create create = {};
uint32_t drmContextId = 0; uint32_t drmContextId = 0;
struct drm_xe_engine_class_instance *currentEngine = nullptr; struct drm_xe_engine_class_instance *currentEngine = nullptr;
std::vector<struct drm_xe_engine_class_instance> engine; std::vector<struct drm_xe_engine_class_instance> engine;
@ -1190,14 +1176,14 @@ int IoctlHelperXe::createDrmContext(Drm &drm, OsContextLinux &osContext, uint32_
} }
create.instances = castToUint64(engine.data()); create.instances = castToUint64(engine.data());
create.num_placements = engine.size(); create.num_placements = engine.size();
struct drm_xe_ext_engine_set_property ext = {}; struct drm_xe_ext_exec_queue_set_property ext = {};
ext.base.name = XE_ENGINE_EXTENSION_SET_PROPERTY; ext.base.name = XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY;
ext.property = XE_ENGINE_PROPERTY_COMPUTE_MODE; ext.property = XE_EXEC_QUEUE_SET_PROPERTY_COMPUTE_MODE;
ext.value = 1; ext.value = 1;
create.extensions = castToUint64(&ext); create.extensions = castToUint64(&ext);
int ret = IoctlHelper::ioctl(DrmIoctl::GemContextCreateExt, &create); int ret = IoctlHelper::ioctl(DrmIoctl::GemContextCreateExt, &create);
drmContextId = create.engine_id; drmContextId = create.exec_queue_id;
xeLog("%s:%d (%d) vmid=0x%x ctx=0x%x r=0x%x\n", xeGetClassName(engine[0].engine_class), xeLog("%s:%d (%d) vmid=0x%x ctx=0x%x r=0x%x\n", xeGetClassName(engine[0].engine_class),
engine[0].engine_instance, create.num_placements, drmVmId, drmContextId, ret); engine[0].engine_instance, create.num_placements, drmVmId, drmContextId, ret);
if (ret != 0) { if (ret != 0) {

29
shared/test/unit_test/os_interface/linux/xe/ioctl_helper_xe_tests.cpp
View File

@ -116,7 +116,6 @@ class DrmMockXe : public DrmMockCustom {
1, // instance 1, // instance
0, // padding 0, // padding
MemoryConstants::pageSize, // min page size MemoryConstants::pageSize, // min page size
MemoryConstants::pageSize, // max page size
2 * MemoryConstants::gigaByte, // total size 2 * MemoryConstants::gigaByte, // total size
MemoryConstants::megaByte // used size MemoryConstants::megaByte // used size
}; };
@ -125,7 +124,6 @@ class DrmMockXe : public DrmMockCustom {
0, // instance 0, // instance
0, // padding 0, // padding
MemoryConstants::pageSize, // min page size MemoryConstants::pageSize, // min page size
MemoryConstants::pageSize, // max page size
MemoryConstants::gigaByte, // total size MemoryConstants::gigaByte, // total size
MemoryConstants::kiloByte // used size MemoryConstants::kiloByte // used size
}; };
@ -134,7 +132,6 @@ class DrmMockXe : public DrmMockCustom {
2, // instance 2, // instance
0, // padding 0, // padding
MemoryConstants::pageSize, // min page size MemoryConstants::pageSize, // min page size
MemoryConstants::pageSize, // max page size
4 * MemoryConstants::gigaByte, // total size 4 * MemoryConstants::gigaByte, // total size
MemoryConstants::gigaByte // used size MemoryConstants::gigaByte // used size
}; };
@ -316,7 +313,7 @@ class DrmMockXe : public DrmMockCustom {
{DRM_XE_ENGINE_CLASS_VIDEO_DECODE, 7, 1}, {DRM_XE_ENGINE_CLASS_VIDEO_DECODE, 7, 1},
{DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE, 8, 0}}; {DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE, 8, 0}};
static_assert(sizeof(drm_xe_query_mem_usage::drm_xe_query_mem_region) == 12 * sizeof(uint64_t), ""); static_assert(sizeof(drm_xe_query_mem_region) == 12 * sizeof(uint64_t), "");
uint64_t queryMemUsage[37]{}; // 1 qword for num regions and 12 qwords per region uint64_t queryMemUsage[37]{}; // 1 qword for num regions and 12 qwords per region
static_assert(sizeof(drm_xe_query_gts::drm_xe_query_gt) == 13 * sizeof(uint64_t), ""); static_assert(sizeof(drm_xe_query_gts::drm_xe_query_gt) == 13 * sizeof(uint64_t), "");
uint64_t queryGts[27]{}; // 1 qword for num gts and 13 qwords per gt uint64_t queryGts[27]{}; // 1 qword for num gts and 13 qwords per gt
@ -555,14 +552,14 @@ TEST(IoctlHelperXeTest, givenIoctlHelperXeWhenCallingAnyMethodThenDummyValueIsRe
// Default no translation: // Default no translation:
verifyDrmGetParamValue(static_cast<int>(DrmParam::ExecRender), DrmParam::ExecRender); verifyDrmGetParamValue(static_cast<int>(DrmParam::ExecRender), DrmParam::ExecRender);
// test exception: // test exception:
verifyDrmGetParamValue(NEO::PrelimI915::I915_MEMORY_CLASS_DEVICE, DrmParam::MemoryClassDevice); verifyDrmGetParamValue(XE_MEM_REGION_CLASS_VRAM, DrmParam::MemoryClassDevice);
verifyDrmGetParamValue(NEO::PrelimI915::I915_MEMORY_CLASS_SYSTEM, DrmParam::MemoryClassSystem); verifyDrmGetParamValue(XE_MEM_REGION_CLASS_SYSMEM, DrmParam::MemoryClassSystem);
verifyDrmGetParamValue(NEO::PrelimI915::I915_ENGINE_CLASS_RENDER, DrmParam::EngineClassRender); verifyDrmGetParamValue(DRM_XE_ENGINE_CLASS_RENDER, DrmParam::EngineClassRender);
verifyDrmGetParamValue(NEO::PrelimI915::I915_ENGINE_CLASS_COPY, DrmParam::EngineClassCopy); verifyDrmGetParamValue(DRM_XE_ENGINE_CLASS_COPY, DrmParam::EngineClassCopy);
verifyDrmGetParamValue(NEO::PrelimI915::I915_ENGINE_CLASS_VIDEO, DrmParam::EngineClassVideo); verifyDrmGetParamValue(DRM_XE_ENGINE_CLASS_VIDEO_DECODE, DrmParam::EngineClassVideo);
verifyDrmGetParamValue(NEO::PrelimI915::I915_ENGINE_CLASS_VIDEO_ENHANCE, DrmParam::EngineClassVideoEnhance); verifyDrmGetParamValue(DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE, DrmParam::EngineClassVideoEnhance);
verifyDrmGetParamValue(NEO::PrelimI915::I915_ENGINE_CLASS_COMPUTE, DrmParam::EngineClassCompute); verifyDrmGetParamValue(DRM_XE_ENGINE_CLASS_COMPUTE, DrmParam::EngineClassCompute);
verifyDrmGetParamValue(NEO::PrelimI915::I915_ENGINE_CLASS_INVALID, DrmParam::EngineClassInvalid); verifyDrmGetParamValue(-1, DrmParam::EngineClassInvalid);
// Expect stringify // Expect stringify
verifyDrmParamString("ContextCreateExtSetparam", DrmParam::ContextCreateExtSetparam); verifyDrmParamString("ContextCreateExtSetparam", DrmParam::ContextCreateExtSetparam);
@ -620,8 +617,8 @@ TEST(IoctlHelperXeTest, givenIoctlHelperXeWhenCallingAnyMethodThenDummyValueIsRe
verifyIoctlString(DrmIoctl::GemExecbuffer2, "DRM_IOCTL_XE_EXEC"); verifyIoctlString(DrmIoctl::GemExecbuffer2, "DRM_IOCTL_XE_EXEC");
verifyIoctlString(DrmIoctl::GemVmBind, "DRM_IOCTL_XE_VM_BIND"); verifyIoctlString(DrmIoctl::GemVmBind, "DRM_IOCTL_XE_VM_BIND");
verifyIoctlString(DrmIoctl::Query, "DRM_IOCTL_XE_DEVICE_QUERY"); verifyIoctlString(DrmIoctl::Query, "DRM_IOCTL_XE_DEVICE_QUERY");
verifyIoctlString(DrmIoctl::GemContextCreateExt, "DRM_IOCTL_XE_ENGINE_CREATE"); verifyIoctlString(DrmIoctl::GemContextCreateExt, "DRM_IOCTL_XE_EXEC_QUEUE_CREATE");
verifyIoctlString(DrmIoctl::GemContextDestroy, "DRM_IOCTL_XE_ENGINE_DESTROY"); verifyIoctlString(DrmIoctl::GemContextDestroy, "DRM_IOCTL_XE_EXEC_QUEUE_DESTROY");
verifyIoctlString(DrmIoctl::GemWaitUserFence, "DRM_IOCTL_XE_WAIT_USER_FENCE"); verifyIoctlString(DrmIoctl::GemWaitUserFence, "DRM_IOCTL_XE_WAIT_USER_FENCE");
verifyIoctlString(DrmIoctl::PrimeFdToHandle, "DRM_IOCTL_PRIME_FD_TO_HANDLE"); verifyIoctlString(DrmIoctl::PrimeFdToHandle, "DRM_IOCTL_PRIME_FD_TO_HANDLE");
verifyIoctlString(DrmIoctl::PrimeHandleToFd, "DRM_IOCTL_PRIME_HANDLE_TO_FD"); verifyIoctlString(DrmIoctl::PrimeHandleToFd, "DRM_IOCTL_PRIME_HANDLE_TO_FD");
@ -662,8 +659,8 @@ TEST(IoctlHelperXeTest, whenGettingIoctlRequestValueThenPropertValueIsReturned)
verifyIoctlRequestValue(DRM_IOCTL_XE_VM_DESTROY, DrmIoctl::GemVmDestroy); verifyIoctlRequestValue(DRM_IOCTL_XE_VM_DESTROY, DrmIoctl::GemVmDestroy);
verifyIoctlRequestValue(DRM_IOCTL_XE_GEM_MMAP_OFFSET, DrmIoctl::GemMmapOffset); verifyIoctlRequestValue(DRM_IOCTL_XE_GEM_MMAP_OFFSET, DrmIoctl::GemMmapOffset);
verifyIoctlRequestValue(DRM_IOCTL_XE_DEVICE_QUERY, DrmIoctl::Query); verifyIoctlRequestValue(DRM_IOCTL_XE_DEVICE_QUERY, DrmIoctl::Query);
verifyIoctlRequestValue(DRM_IOCTL_XE_ENGINE_CREATE, DrmIoctl::GemContextCreateExt); verifyIoctlRequestValue(DRM_IOCTL_XE_EXEC_QUEUE_CREATE, DrmIoctl::GemContextCreateExt);
verifyIoctlRequestValue(DRM_IOCTL_XE_ENGINE_DESTROY, DrmIoctl::GemContextDestroy); verifyIoctlRequestValue(DRM_IOCTL_XE_EXEC_QUEUE_DESTROY, DrmIoctl::GemContextDestroy);
verifyIoctlRequestValue(DRM_IOCTL_PRIME_FD_TO_HANDLE, DrmIoctl::PrimeFdToHandle); verifyIoctlRequestValue(DRM_IOCTL_PRIME_FD_TO_HANDLE, DrmIoctl::PrimeFdToHandle);
verifyIoctlRequestValue(DRM_IOCTL_PRIME_HANDLE_TO_FD, DrmIoctl::PrimeHandleToFd); verifyIoctlRequestValue(DRM_IOCTL_PRIME_HANDLE_TO_FD, DrmIoctl::PrimeHandleToFd);
verifyIoctlRequestValue(DRM_IOCTL_XE_MMIO, DrmIoctl::RegRead); verifyIoctlRequestValue(DRM_IOCTL_XE_MMIO, DrmIoctl::RegRead);

567
third_party/uapi/drm/xe_drm.h vendored
View File

@ -1,30 +1,10 @@
/* SPDX-License-Identifier: MIT */
/* /*
* Copyright 2021 Intel Corporation. All Rights Reserved. * Copyright © 2023 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/ */
#ifndef _UAPI_XE_DRM_H_ #ifndef _XE_DRM_H_
#define _UAPI_XE_DRM_H_ #define _XE_DRM_H_
#include "drm.h" #include "drm.h"
@ -37,7 +17,17 @@ extern "C" {
*/ */
/** /**
* struct i915_user_extension - Base class for defining a chain of extensions * DOC: uevent generated by xe on it's pci node.
*
* XE_RESET_FAILED_UEVENT - Event is generated when attempt to reset gt
* fails. The value supplied with the event is always "NEEDS_RESET".
* Additional information supplied is tile id and gt id of the gt unit for
* which reset has failed.
*/
#define XE_RESET_FAILED_UEVENT "DEVICE_STATUS"
/**
* struct xe_user_extension - Base class for defining a chain of extensions
* *
* Many interfaces need to grow over time. In most cases we can simply * Many interfaces need to grow over time. In most cases we can simply
* extend the struct and have userspace pass in more data. Another option, * extend the struct and have userspace pass in more data. Another option,
@ -49,26 +39,26 @@ extern "C" {
* redefine the interface more easily than an ever growing struct of * redefine the interface more easily than an ever growing struct of
* increasing complexity, and for large parts of that interface to be * increasing complexity, and for large parts of that interface to be
* entirely optional. The downside is more pointer chasing; chasing across * entirely optional. The downside is more pointer chasing; chasing across
* the __user boundary with pointers encapsulated inside u64. * the boundary with pointers encapsulated inside u64.
* *
* Example chaining: * Example chaining:
* *
* .. code-block:: C * .. code-block:: C
* *
* struct i915_user_extension ext3 { * struct xe_user_extension ext3 {
* .next_extension = 0, // end * .next_extension = 0, // end
* .name = ..., * .name = ...,
* }; * };
* struct i915_user_extension ext2 { * struct xe_user_extension ext2 {
* .next_extension = (uintptr_t)&ext3, * .next_extension = (uintptr_t)&ext3,
* .name = ..., * .name = ...,
* }; * };
* struct i915_user_extension ext1 { * struct xe_user_extension ext1 {
* .next_extension = (uintptr_t)&ext2, * .next_extension = (uintptr_t)&ext2,
* .name = ..., * .name = ...,
* }; * };
* *
* Typically the struct i915_user_extension would be embedded in some uAPI * Typically the struct xe_user_extension would be embedded in some uAPI
* struct, and in this case we would feed it the head of the chain(i.e ext1), * struct, and in this case we would feed it the head of the chain(i.e ext1),
* which would then apply all of the above extensions. * which would then apply all of the above extensions.
* *
@ -77,9 +67,10 @@ struct xe_user_extension {
/** /**
* @next_extension: * @next_extension:
* *
* Pointer to the next struct i915_user_extension, or zero if the end. * Pointer to the next struct xe_user_extension, or zero if the end.
*/ */
__u64 next_extension; __u64 next_extension;
/** /**
* @name: Name of the extension. * @name: Name of the extension.
* *
@ -87,11 +78,12 @@ struct xe_user_extension {
* *
* Also note that the name space for this is not global for the whole * Also note that the name space for this is not global for the whole
* driver, but rather its scope/meaning is limited to the specific piece * driver, but rather its scope/meaning is limited to the specific piece
* of uAPI which has embedded the struct i915_user_extension. * of uAPI which has embedded the struct xe_user_extension.
*/ */
__u32 name; __u32 name;
/** /**
* @flags: MBZ * @pad: MBZ
* *
* All undefined bits must be zero. * All undefined bits must be zero.
*/ */
@ -99,7 +91,7 @@ struct xe_user_extension {
}; };
/* /*
* i915 specific ioctls. * xe specific ioctls.
* *
* The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
* [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
@ -111,13 +103,14 @@ struct xe_user_extension {
#define DRM_XE_VM_CREATE 0x03 #define DRM_XE_VM_CREATE 0x03
#define DRM_XE_VM_DESTROY 0x04 #define DRM_XE_VM_DESTROY 0x04
#define DRM_XE_VM_BIND 0x05 #define DRM_XE_VM_BIND 0x05
#define DRM_XE_ENGINE_CREATE 0x06 #define DRM_XE_EXEC_QUEUE_CREATE 0x06
#define DRM_XE_ENGINE_DESTROY 0x07 #define DRM_XE_EXEC_QUEUE_DESTROY 0x07
#define DRM_XE_EXEC 0x08 #define DRM_XE_EXEC 0x08
#define DRM_XE_MMIO 0x09 #define DRM_XE_MMIO 0x09
#define DRM_XE_ENGINE_SET_PROPERTY 0x0a #define DRM_XE_EXEC_QUEUE_SET_PROPERTY 0x0a
#define DRM_XE_WAIT_USER_FENCE 0x0b #define DRM_XE_WAIT_USER_FENCE 0x0b
#define DRM_XE_VM_MADVISE 0x0c #define DRM_XE_VM_MADVISE 0x0c
#define DRM_XE_EXEC_QUEUE_GET_PROPERTY 0x0d
/* Must be kept compact -- no holes */ /* Must be kept compact -- no holes */
#define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query) #define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query)
@ -126,75 +119,170 @@ struct xe_user_extension {
#define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create) #define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create)
#define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy) #define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy)
#define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind) #define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind)
#define DRM_IOCTL_XE_ENGINE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_ENGINE_CREATE, struct drm_xe_engine_create) #define DRM_IOCTL_XE_EXEC_QUEUE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create)
#define DRM_IOCTL_XE_ENGINE_DESTROY DRM_IOW( DRM_COMMAND_BASE + DRM_XE_ENGINE_DESTROY, struct drm_xe_engine_destroy) #define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property)
#define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy)
#define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec) #define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec)
#define DRM_IOCTL_XE_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_MMIO, struct drm_xe_mmio) #define DRM_IOCTL_XE_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_MMIO, struct drm_xe_mmio)
#define DRM_IOCTL_XE_ENGINE_SET_PROPERTY DRM_IOW( DRM_COMMAND_BASE + DRM_XE_ENGINE_SET_PROPERTY, struct drm_xe_engine_set_property) #define DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_SET_PROPERTY, struct drm_xe_exec_queue_set_property)
#define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence) #define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence)
#define DRM_IOCTL_XE_VM_MADVISE DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_MADVISE, struct drm_xe_vm_madvise) #define DRM_IOCTL_XE_VM_MADVISE DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_MADVISE, struct drm_xe_vm_madvise)
struct drm_xe_engine_class_instance { /**
__u16 engine_class; * enum drm_xe_memory_class - Supported memory classes.
#define DRM_XE_ENGINE_CLASS_RENDER 0
#define DRM_XE_ENGINE_CLASS_COPY 1
#define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2
#define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3
#define DRM_XE_ENGINE_CLASS_COMPUTE 4
/*
* Kernel only class (not actual hardware engine class). Used for
* creating ordered queues of VM bind operations.
*/ */
#define DRM_XE_ENGINE_CLASS_VM_BIND 5 enum drm_xe_memory_class {
/** @XE_MEM_REGION_CLASS_SYSMEM: Represents system memory. */
__u16 engine_instance; XE_MEM_REGION_CLASS_SYSMEM = 0,
__u16 gt_id; /**
* @XE_MEM_REGION_CLASS_VRAM: On discrete platforms, this
* represents the memory that is local to the device, which we
* call VRAM. Not valid on integrated platforms.
*/
XE_MEM_REGION_CLASS_VRAM
}; };
#define XE_MEM_REGION_CLASS_SYSMEM 0 /**
#define XE_MEM_REGION_CLASS_VRAM 1 * struct drm_xe_query_mem_region - Describes some region as known to
* the driver.
struct drm_xe_query_mem_usage { */
__u32 num_regions;
__u32 pad;
struct drm_xe_query_mem_region { struct drm_xe_query_mem_region {
/**
* @mem_class: The memory class describing this region.
*
* See enum drm_xe_memory_class for supported values.
*/
__u16 mem_class; __u16 mem_class;
__u16 instance; /* unique ID even among different classes */ /**
* @instance: The instance for this region.
*
* The @mem_class and @instance taken together will always give
* a unique pair.
*/
__u16 instance;
/** @pad: MBZ */
__u32 pad; __u32 pad;
/**
* @min_page_size: Min page-size in bytes for this region.
*
* When the kernel allocates memory for this region, the
* underlying pages will be at least @min_page_size in size.
*
* Important note: When userspace allocates a GTT address which
* can point to memory allocated from this region, it must also
* respect this minimum alignment. This is enforced by the
* kernel.
*/
__u32 min_page_size; __u32 min_page_size;
__u32 max_page_size; /**
* @total_size: The usable size in bytes for this region.
*/
__u64 total_size; __u64 total_size;
/**
* @used: Estimate of the memory used in bytes for this region.
*
* Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable
* accounting. Without this the value here will always equal
* zero.
*/
__u64 used; __u64 used;
__u64 reserved[8]; /**
} regions[]; * @cpu_visible_size: How much of this region can be CPU
* accessed, in bytes.
*
* This will always be <= @total_size, and the remainder (if
* any) will not be CPU accessible. If the CPU accessible part
* is smaller than @total_size then this is referred to as a
* small BAR system.
*
* On systems without small BAR (full BAR), the probed_size will
* always equal the @total_size, since all of it will be CPU
* accessible.
*
* Note this is only tracked for XE_MEM_REGION_CLASS_VRAM
* regions (for other types the value here will always equal
* zero).
*/
__u64 cpu_visible_size;
/**
* @cpu_visible_used: Estimate of CPU visible memory used, in
* bytes.
*
* Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable
* accounting. Without this the value here will always equal
* zero. Note this is only currently tracked for
* XE_MEM_REGION_CLASS_VRAM regions (for other types the value
* here will always be zero).
*/
__u64 cpu_visible_used;
/** @reserved: MBZ */
__u64 reserved[6];
}; };
struct drm_xe_query_config { /**
__u32 num_params; * struct drm_xe_query_mem_usage - describe memory regions and usage
*
* If a query is made with a struct drm_xe_device_query where .query
* is equal to DRM_XE_DEVICE_QUERY_MEM_USAGE, then the reply uses
* struct drm_xe_query_mem_usage in .data.
*/
struct drm_xe_query_mem_usage {
/** @num_regions: number of memory regions returned in @regions */
__u32 num_regions;
/** @pad: MBZ */
__u32 pad; __u32 pad;
/** @regions: The returned regions for this device */
struct drm_xe_query_mem_region regions[];
};
/**
* struct drm_xe_query_config - describe the device configuration
*
* If a query is made with a struct drm_xe_device_query where .query
* is equal to DRM_XE_DEVICE_QUERY_CONFIG, then the reply uses
* struct drm_xe_query_config in .data.
*/
struct drm_xe_query_config {
/** @num_params: number of parameters returned in info */
__u32 num_params;
/** @pad: MBZ */
__u32 pad;
#define XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0 #define XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0
#define XE_QUERY_CONFIG_FLAGS 1 #define XE_QUERY_CONFIG_FLAGS 1
#define XE_QUERY_CONFIG_FLAGS_HAS_VRAM (0x1 << 0) #define XE_QUERY_CONFIG_FLAGS_HAS_VRAM (0x1 << 0)
#define XE_QUERY_CONFIG_FLAGS_USE_GUC (0x1 << 1) #define XE_QUERY_CONFIG_MIN_ALIGNMENT 2
#define XE_QUERY_CONFIG_MIN_ALIGNEMENT 2
#define XE_QUERY_CONFIG_VA_BITS 3 #define XE_QUERY_CONFIG_VA_BITS 3
#define XE_QUERY_CONFIG_GT_COUNT 4 #define XE_QUERY_CONFIG_GT_COUNT 4
#define XE_QUERY_CONFIG_MEM_REGION_COUNT 5 #define XE_QUERY_CONFIG_MEM_REGION_COUNT 5
#define XE_QUERY_CONFIG_NUM_PARAM XE_QUERY_CONFIG_MEM_REGION_COUNT + 1 #define XE_QUERY_CONFIG_MAX_ENGINE_PRIORITY 6
#define XE_QUERY_CONFIG_NUM_PARAM (XE_QUERY_CONFIG_MAX_ENGINE_PRIORITY + 1)
/** @info: array of elements containing the config info */
__u64 info[]; __u64 info[];
}; };
/**
* struct drm_xe_query_gts - describe GTs
*
* If a query is made with a struct drm_xe_device_query where .query
* is equal to DRM_XE_DEVICE_QUERY_GTS, then the reply uses struct
* drm_xe_query_gts in .data.
*/
struct drm_xe_query_gts { struct drm_xe_query_gts {
/** @num_gt: number of GTs returned in gts */
__u32 num_gt; __u32 num_gt;
/** @pad: MBZ */
__u32 pad; __u32 pad;
/* /**
* @gts: The GTs returned for this device
*
* TODO: convert drm_xe_query_gt to proper kernel-doc.
* TODO: Perhaps info about every mem region relative to this GT? e.g. * TODO: Perhaps info about every mem region relative to this GT? e.g.
* bandwidth between this GT and remote region? * bandwidth between this GT and remote region?
*/ */
struct drm_xe_query_gt { struct drm_xe_query_gt {
#define XE_QUERY_GT_TYPE_MAIN 0 #define XE_QUERY_GT_TYPE_MAIN 0
#define XE_QUERY_GT_TYPE_REMOTE 1 #define XE_QUERY_GT_TYPE_REMOTE 1
@ -210,15 +298,46 @@ struct drm_xe_query_gts {
} gts[]; } gts[];
}; };
/**
* struct drm_xe_query_topology_mask - describe the topology mask of a GT
*
* This is the hardware topology which reflects the internal physical
* structure of the GPU.
*
* If a query is made with a struct drm_xe_device_query where .query
* is equal to DRM_XE_DEVICE_QUERY_GT_TOPOLOGY, then the reply uses
* struct drm_xe_query_topology_mask in .data.
*/
struct drm_xe_query_topology_mask { struct drm_xe_query_topology_mask {
/** @gt_id: GT ID the mask is associated with */ /** @gt_id: GT ID the mask is associated with */
__u16 gt_id; __u16 gt_id;
/*
* To query the mask of Dual Sub Slices (DSS) available for geometry
* operations. For example a query response containing the following
* in mask:
* DSS_GEOMETRY ff ff ff ff 00 00 00 00
* means 32 DSS are available for geometry.
*/
#define XE_TOPO_DSS_GEOMETRY (1 << 0)
/*
* To query the mask of Dual Sub Slices (DSS) available for compute
* operations. For example a query response containing the following
* in mask:
* DSS_COMPUTE ff ff ff ff 00 00 00 00
* means 32 DSS are available for compute.
*/
#define XE_TOPO_DSS_COMPUTE (1 << 1)
/*
* To query the mask of Execution Units (EU) available per Dual Sub
* Slices (DSS). For example a query response containing the following
* in mask:
* EU_PER_DSS ff ff 00 00 00 00 00 00
* means each DSS has 16 EU.
*/
#define XE_TOPO_EU_PER_DSS (1 << 2)
/** @type: type of mask */ /** @type: type of mask */
__u16 type; __u16 type;
#define XE_TOPO_DSS_GEOMETRY (1 << 0)
#define XE_TOPO_DSS_COMPUTE (1 << 1)
#define XE_TOPO_EU_PER_DSS (1 << 2)
/** @num_bytes: number of bytes in requested mask */ /** @num_bytes: number of bytes in requested mask */
__u32 num_bytes; __u32 num_bytes;
@ -227,19 +346,53 @@ struct drm_xe_query_topology_mask {
__u8 mask[]; __u8 mask[];
}; };
/**
* struct drm_xe_device_query - main structure to query device information
*
* If size is set to 0, the driver fills it with the required size for the
* requested type of data to query. If size is equal to the required size,
* the queried information is copied into data.
*
* For example the following code snippet allows retrieving and printing
* information about the device engines with DRM_XE_DEVICE_QUERY_ENGINES:
*
* .. code-block:: C
*
* struct drm_xe_engine_class_instance *hwe;
* struct drm_xe_device_query query = {
* .extensions = 0,
* .query = DRM_XE_DEVICE_QUERY_ENGINES,
* .size = 0,
* .data = 0,
* };
* ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query);
* hwe = malloc(query.size);
* query.data = (uintptr_t)hwe;
* ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query);
* int num_engines = query.size / sizeof(*hwe);
* for (int i = 0; i < num_engines; i++) {
* printf("Engine %d: %s\n", i,
* hwe[i].engine_class == DRM_XE_ENGINE_CLASS_RENDER ? "RENDER":
* hwe[i].engine_class == DRM_XE_ENGINE_CLASS_COPY ? "COPY":
* hwe[i].engine_class == DRM_XE_ENGINE_CLASS_VIDEO_DECODE ? "VIDEO_DECODE":
* hwe[i].engine_class == DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE ? "VIDEO_ENHANCE":
* hwe[i].engine_class == DRM_XE_ENGINE_CLASS_COMPUTE ? "COMPUTE":
* "UNKNOWN");
* }
* free(hwe);
*/
struct drm_xe_device_query { struct drm_xe_device_query {
/** @extensions: Pointer to the first extension struct, if any */ /** @extensions: Pointer to the first extension struct, if any */
__u64 extensions; __u64 extensions;
/** @query: The type of data to query */
__u32 query;
#define DRM_XE_DEVICE_QUERY_ENGINES 0 #define DRM_XE_DEVICE_QUERY_ENGINES 0
#define DRM_XE_DEVICE_QUERY_MEM_USAGE 1 #define DRM_XE_DEVICE_QUERY_MEM_USAGE 1
#define DRM_XE_DEVICE_QUERY_CONFIG 2 #define DRM_XE_DEVICE_QUERY_CONFIG 2
#define DRM_XE_DEVICE_QUERY_GTS 3 #define DRM_XE_DEVICE_QUERY_GTS 3
#define DRM_XE_DEVICE_QUERY_HWCONFIG 4 #define DRM_XE_DEVICE_QUERY_HWCONFIG 4
#define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5 #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5
/** @query: The type of data to query */
__u32 query;
/** @size: Size of the queried data */ /** @size: Size of the queried data */
__u32 size; __u32 size;
@ -262,12 +415,28 @@ struct drm_xe_gem_create {
*/ */
__u64 size; __u64 size;
#define XE_GEM_CREATE_FLAG_DEFER_BACKING (0x1 << 24)
#define XE_GEM_CREATE_FLAG_SCANOUT (0x1 << 25)
/*
* When using VRAM as a possible placement, ensure that the corresponding VRAM
* allocation will always use the CPU accessible part of VRAM. This is important
* for small-bar systems (on full-bar systems this gets turned into a noop).
*
* Note: System memory can be used as an extra placement if the kernel should
* spill the allocation to system memory, if space can't be made available in
* the CPU accessible part of VRAM (giving the same behaviour as the i915
* interface, see I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS).
*
* Note: For clear-color CCS surfaces the kernel needs to read the clear-color
* value stored in the buffer, and on discrete platforms we need to use VRAM for
* display surfaces, therefore the kernel requires setting this flag for such
* objects, otherwise an error is thrown on small-bar systems.
*/
#define XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (0x1 << 26)
/** /**
* @flags: Flags, currently a mask of memory instances of where BO can * @flags: Flags, currently a mask of memory instances of where BO can
* be placed * be placed
*/ */
#define XE_GEM_CREATE_FLAG_DEFER_BACKING (0x1 << 24)
#define XE_GEM_CREATE_FLAG_SCANOUT (0x1 << 25)
__u32 flags; __u32 flags;
/** /**
@ -276,7 +445,6 @@ struct drm_xe_gem_create {
* If a VM is specified, this BO must: * If a VM is specified, this BO must:
* *
* 1. Only ever be bound to that VM. * 1. Only ever be bound to that VM.
*
* 2. Cannot be exported as a PRIME fd. * 2. Cannot be exported as a PRIME fd.
*/ */
__u32 vm_id; __u32 vm_id;
@ -288,6 +456,9 @@ struct drm_xe_gem_create {
*/ */
__u32 handle; __u32 handle;
/** @pad: MBZ */
__u32 pad;
/** @reserved: Reserved */ /** @reserved: Reserved */
__u64 reserved[2]; __u64 reserved[2];
}; };
@ -313,12 +484,15 @@ struct drm_xe_gem_mmap_offset {
* struct drm_xe_vm_bind_op_error_capture - format of VM bind op error capture * struct drm_xe_vm_bind_op_error_capture - format of VM bind op error capture
*/ */
struct drm_xe_vm_bind_op_error_capture { struct drm_xe_vm_bind_op_error_capture {
/** @error: errno that occured */ /** @error: errno that occurred */
__s32 error; __s32 error;
/** @op: operation that encounter an error */ /** @op: operation that encounter an error */
__u32 op; __u32 op;
/** @addr: address of bind op */ /** @addr: address of bind op */
__u64 addr; __u64 addr;
/** @size: size of bind */ /** @size: size of bind */
__u64 size; __u64 size;
}; };
@ -328,10 +502,13 @@ struct drm_xe_ext_vm_set_property {
/** @base: base user extension */ /** @base: base user extension */
struct xe_user_extension base; struct xe_user_extension base;
/** @property: property to set */
#define XE_VM_PROPERTY_BIND_OP_ERROR_CAPTURE_ADDRESS 0 #define XE_VM_PROPERTY_BIND_OP_ERROR_CAPTURE_ADDRESS 0
/** @property: property to set */
__u32 property; __u32 property;
/** @pad: MBZ */
__u32 pad;
/** @value: property value */ /** @value: property value */
__u64 value; __u64 value;
@ -340,17 +517,16 @@ struct drm_xe_ext_vm_set_property {
}; };
struct drm_xe_vm_create { struct drm_xe_vm_create {
/** @extensions: Pointer to the first extension struct, if any */
#define XE_VM_EXTENSION_SET_PROPERTY 0 #define XE_VM_EXTENSION_SET_PROPERTY 0
/** @extensions: Pointer to the first extension struct, if any */
__u64 extensions; __u64 extensions;
/** @flags: Flags */
__u32 flags;
#define DRM_XE_VM_CREATE_SCRATCH_PAGE (0x1 << 0) #define DRM_XE_VM_CREATE_SCRATCH_PAGE (0x1 << 0)
#define DRM_XE_VM_CREATE_COMPUTE_MODE (0x1 << 1) #define DRM_XE_VM_CREATE_COMPUTE_MODE (0x1 << 1)
#define DRM_XE_VM_CREATE_ASYNC_BIND_OPS (0x1 << 2) #define DRM_XE_VM_CREATE_ASYNC_BIND_OPS (0x1 << 2)
#define DRM_XE_VM_CREATE_FAULT_MODE (0x1 << 3) #define DRM_XE_VM_CREATE_FAULT_MODE (0x1 << 3)
/** @flags: Flags */
__u32 flags;
/** @vm_id: Returned VM ID */ /** @vm_id: Returned VM ID */
__u32 vm_id; __u32 vm_id;
@ -376,12 +552,16 @@ struct drm_xe_vm_bind_op {
*/ */
__u32 obj; __u32 obj;
/** @pad: MBZ */
__u32 pad;
union { union {
/** /**
* @obj_offset: Offset into the object, MBZ for CLEAR_RANGE, * @obj_offset: Offset into the object, MBZ for CLEAR_RANGE,
* ignored for unbind * ignored for unbind
*/ */
__u64 obj_offset; __u64 obj_offset;
/** @userptr: user pointer to bind on */ /** @userptr: user pointer to bind on */
__u64 userptr; __u64 userptr;
}; };
@ -395,16 +575,10 @@ struct drm_xe_vm_bind_op {
__u64 addr; __u64 addr;
/** /**
* @gt_mask: Mask for which GTs to create binds for, 0 == All GTs, * @tile_mask: Mask for which tiles to create binds for, 0 == All tiles,
* only applies to creating new VMAs * only applies to creating new VMAs
*/ */
__u64 gt_mask; __u64 tile_mask;
/** @op: Operation to perform (lower 16 bits) and flags (upper 16 bits) */
__u32 op;
/** @mem_region: Memory region to prefetch VMA to, instance not a mask */
__u32 region;
#define XE_VM_BIND_OP_MAP 0x0 #define XE_VM_BIND_OP_MAP 0x0
#define XE_VM_BIND_OP_UNMAP 0x1 #define XE_VM_BIND_OP_UNMAP 0x1
@ -425,12 +599,12 @@ struct drm_xe_vm_bind_op {
* If this flag is clear and the IOCTL doesn't return an error, in * If this flag is clear and the IOCTL doesn't return an error, in
* practice the bind op is good and will complete. * practice the bind op is good and will complete.
* *
* If this flag is set and doesn't return return an error, the bind op * If this flag is set and doesn't return an error, the bind op can
* can still fail and recovery is needed. If configured, the bind op that * still fail and recovery is needed. If configured, the bind op that
* caused the error will be captured in drm_xe_vm_bind_op_error_capture. * caused the error will be captured in drm_xe_vm_bind_op_error_capture.
* Once the user sees the error (via a ufence + * Once the user sees the error (via a ufence +
* XE_VM_PROPERTY_BIND_OP_ERROR_CAPTURE_ADDRESS), it should free memory * XE_VM_PROPERTY_BIND_OP_ERROR_CAPTURE_ADDRESS), it should free memory
* via non-async unbinds, and then restart all queue'd async binds op via * via non-async unbinds, and then restart all queued async binds op via
* XE_VM_BIND_OP_RESTART. Or alternatively the user should destroy the * XE_VM_BIND_OP_RESTART. Or alternatively the user should destroy the
* VM. * VM.
* *
@ -441,9 +615,22 @@ struct drm_xe_vm_bind_op {
#define XE_VM_BIND_FLAG_ASYNC (0x1 << 17) #define XE_VM_BIND_FLAG_ASYNC (0x1 << 17)
/* /*
* Valid on a faulting VM only, do the MAP operation immediately rather * Valid on a faulting VM only, do the MAP operation immediately rather
* than differing the MAP to the page fault handler. * than deferring the MAP to the page fault handler.
*/ */
#define XE_VM_BIND_FLAG_IMMEDIATE (0x1 << 18) #define XE_VM_BIND_FLAG_IMMEDIATE (0x1 << 18)
/*
* When the NULL flag is set, the page tables are setup with a special
* bit which indicates writes are dropped and all reads return zero. In
* the future, the NULL flags will only be valid for XE_VM_BIND_OP_MAP
* operations, the BO handle MBZ, and the BO offset MBZ. This flag is
* intended to implement VK sparse bindings.
*/
#define XE_VM_BIND_FLAG_NULL (0x1 << 19)
/** @op: Operation to perform (lower 16 bits) and flags (upper 16 bits) */
__u32 op;
/** @mem_region: Memory region to prefetch VMA to, instance not a mask */
__u32 region;
/** @reserved: Reserved */ /** @reserved: Reserved */
__u64 reserved[2]; __u64 reserved[2];
@ -457,18 +644,22 @@ struct drm_xe_vm_bind {
__u32 vm_id; __u32 vm_id;
/** /**
* @engine_id: engine_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND * @exec_queue_id: exec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND
* and engine must have same vm_id. If zero, the default VM bind engine * and exec queue must have same vm_id. If zero, the default VM bind engine
* is used. * is used.
*/ */
__u32 engine_id; __u32 exec_queue_id;
/** @num_binds: number of binds in this IOCTL */ /** @num_binds: number of binds in this IOCTL */
__u32 num_binds; __u32 num_binds;
/** @pad: MBZ */
__u32 pad;
union { union {
/** @bind: used if num_binds == 1 */ /** @bind: used if num_binds == 1 */
struct drm_xe_vm_bind_op bind; struct drm_xe_vm_bind_op bind;
/** /**
* @vector_of_binds: userptr to array of struct * @vector_of_binds: userptr to array of struct
* drm_xe_vm_bind_op if num_binds > 1 * drm_xe_vm_bind_op if num_binds > 1
@ -479,6 +670,9 @@ struct drm_xe_vm_bind {
/** @num_syncs: amount of syncs to wait on */ /** @num_syncs: amount of syncs to wait on */
__u32 num_syncs; __u32 num_syncs;
/** @pad2: MBZ */
__u32 pad2;
/** @syncs: pointer to struct drm_xe_sync array */ /** @syncs: pointer to struct drm_xe_sync array */
__u64 syncs; __u64 syncs;
@ -486,46 +680,49 @@ struct drm_xe_vm_bind {
__u64 reserved[2]; __u64 reserved[2];
}; };
/** struct drm_xe_ext_engine_set_property - engine set property extension */ /** struct drm_xe_ext_exec_queue_set_property - exec queue set property extension */
struct drm_xe_ext_engine_set_property { struct drm_xe_ext_exec_queue_set_property {
/** @base: base user extension */ /** @base: base user extension */
struct xe_user_extension base; struct xe_user_extension base;
/** @property: property to set */ /** @property: property to set */
__u32 property; __u32 property;
/** @pad: MBZ */
__u32 pad;
/** @value: property value */ /** @value: property value */
__u64 value; __u64 value;
}; };
/** /**
* struct drm_xe_engine_set_property - engine set property * struct drm_xe_exec_queue_set_property - exec queue set property
* *
* Same namespace for extensions as drm_xe_engine_create * Same namespace for extensions as drm_xe_exec_queue_create
*/ */
struct drm_xe_engine_set_property { struct drm_xe_exec_queue_set_property {
/** @extensions: Pointer to the first extension struct, if any */ /** @extensions: Pointer to the first extension struct, if any */
__u64 extensions; __u64 extensions;
/** @engine_id: Engine ID */ /** @exec_queue_id: Exec queue ID */
__u32 engine_id; __u32 exec_queue_id;
/** @property: property to set */ #define XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0
#define XE_ENGINE_PROPERTY_PRIORITY 0 #define XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1
#define XE_ENGINE_PROPERTY_TIMESLICE 1 #define XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT 2
#define XE_ENGINE_PROPERTY_PREEMPTION_TIMEOUT 2
/* /*
* Long running or ULLS engine mode. DMA fences not allowed in this * Long running or ULLS engine mode. DMA fences not allowed in this
* mode. Must match the value of DRM_XE_VM_CREATE_COMPUTE_MODE, serves * mode. Must match the value of DRM_XE_VM_CREATE_COMPUTE_MODE, serves
* as a sanity check the UMD knows what it is doing. Can only be set at * as a sanity check the UMD knows what it is doing. Can only be set at
* engine create time. * engine create time.
*/ */
#define XE_ENGINE_PROPERTY_COMPUTE_MODE 3 #define XE_EXEC_QUEUE_SET_PROPERTY_COMPUTE_MODE 3
#define XE_ENGINE_PROPERTY_PERSISTENCE 4 #define XE_EXEC_QUEUE_SET_PROPERTY_PERSISTENCE 4
#define XE_ENGINE_PROPERTY_JOB_TIMEOUT 5 #define XE_EXEC_QUEUE_SET_PROPERTY_JOB_TIMEOUT 5
#define XE_ENGINE_PROPERTY_ACC_TRIGGER 6 #define XE_EXEC_QUEUE_SET_PROPERTY_ACC_TRIGGER 6
#define XE_ENGINE_PROPERTY_ACC_NOTIFY 7 #define XE_EXEC_QUEUE_SET_PROPERTY_ACC_NOTIFY 7
#define XE_ENGINE_PROPERTY_ACC_GRANULARITY 8 #define XE_EXEC_QUEUE_SET_PROPERTY_ACC_GRANULARITY 8
/** @property: property to set */
__u32 property; __u32 property;
/** @value: property value */ /** @value: property value */
@ -535,25 +732,43 @@ struct drm_xe_engine_set_property {
__u64 reserved[2]; __u64 reserved[2];
}; };
struct drm_xe_engine_create { /** struct drm_xe_engine_class_instance - instance of an engine class */
struct drm_xe_engine_class_instance {
#define DRM_XE_ENGINE_CLASS_RENDER 0
#define DRM_XE_ENGINE_CLASS_COPY 1
#define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2
#define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3
#define DRM_XE_ENGINE_CLASS_COMPUTE 4
/*
* Kernel only class (not actual hardware engine class). Used for
* creating ordered queues of VM bind operations.
*/
#define DRM_XE_ENGINE_CLASS_VM_BIND 5
__u16 engine_class;
__u16 engine_instance;
__u16 gt_id;
};
struct drm_xe_exec_queue_create {
#define XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0
/** @extensions: Pointer to the first extension struct, if any */ /** @extensions: Pointer to the first extension struct, if any */
#define XE_ENGINE_EXTENSION_SET_PROPERTY 0
__u64 extensions; __u64 extensions;
/** @width: submission width (number BB per exec) for this engine */ /** @width: submission width (number BB per exec) for this exec queue */
__u16 width; __u16 width;
/** @num_placements: number of valid placements for this engine */ /** @num_placements: number of valid placements for this exec queue */
__u16 num_placements; __u16 num_placements;
/** @vm_id: VM to use for this engine */ /** @vm_id: VM to use for this exec queue */
__u32 vm_id; __u32 vm_id;
/** @flags: MBZ */ /** @flags: MBZ */
__u32 flags; __u32 flags;
/** @engine_id: Returned engine ID */ /** @exec_queue_id: Returned exec queue ID */
__u32 engine_id; __u32 exec_queue_id;
/** /**
* @instances: user pointer to a 2-d array of struct * @instances: user pointer to a 2-d array of struct
@ -568,9 +783,27 @@ struct drm_xe_engine_create {
__u64 reserved[2]; __u64 reserved[2];
}; };
struct drm_xe_engine_destroy { struct drm_xe_exec_queue_get_property {
/** @vm_id: VM ID */ /** @extensions: Pointer to the first extension struct, if any */
__u32 engine_id; __u64 extensions;
/** @exec_queue_id: Exec queue ID */
__u32 exec_queue_id;
#define XE_EXEC_QUEUE_GET_PROPERTY_BAN 0
/** @property: property to get */
__u32 property;
/** @value: property value */
__u64 value;
/** @reserved: Reserved */
__u64 reserved[2];
};
struct drm_xe_exec_queue_destroy {
/** @exec_queue_id: Exec queue ID */
__u32 exec_queue_id;
/** @pad: MBZ */ /** @pad: MBZ */
__u32 pad; __u32 pad;
@ -583,16 +816,19 @@ struct drm_xe_sync {
/** @extensions: Pointer to the first extension struct, if any */ /** @extensions: Pointer to the first extension struct, if any */
__u64 extensions; __u64 extensions;
__u32 flags;
#define DRM_XE_SYNC_SYNCOBJ 0x0 #define DRM_XE_SYNC_SYNCOBJ 0x0
#define DRM_XE_SYNC_TIMELINE_SYNCOBJ 0x1 #define DRM_XE_SYNC_TIMELINE_SYNCOBJ 0x1
#define DRM_XE_SYNC_DMA_BUF 0x2 #define DRM_XE_SYNC_DMA_BUF 0x2
#define DRM_XE_SYNC_USER_FENCE 0x3 #define DRM_XE_SYNC_USER_FENCE 0x3
#define DRM_XE_SYNC_SIGNAL 0x10 #define DRM_XE_SYNC_SIGNAL 0x10
__u32 flags;
/** @pad: MBZ */
__u32 pad;
union { union {
__u32 handle; __u32 handle;
/** /**
* @addr: Address of user fence. When sync passed in via exec * @addr: Address of user fence. When sync passed in via exec
* IOCTL this a GPU address in the VM. When sync passed in via * IOCTL this a GPU address in the VM. When sync passed in via
@ -614,8 +850,8 @@ struct drm_xe_exec {
/** @extensions: Pointer to the first extension struct, if any */ /** @extensions: Pointer to the first extension struct, if any */
__u64 extensions; __u64 extensions;
/** @vm_id: VM ID to run batch buffer in */ /** @exec_queue_id: Exec queue ID for the batch buffer */
__u32 engine_id; __u32 exec_queue_id;
/** @num_syncs: Amount of struct drm_xe_sync in array. */ /** @num_syncs: Amount of struct drm_xe_sync in array. */
__u32 num_syncs; __u32 num_syncs;
@ -635,6 +871,9 @@ struct drm_xe_exec {
*/ */
__u16 num_batch_buffer; __u16 num_batch_buffer;
/** @pad: MBZ */
__u16 pad[3];
/** @reserved: Reserved */ /** @reserved: Reserved */
__u64 reserved[2]; __u64 reserved[2];
}; };
@ -645,8 +884,6 @@ struct drm_xe_mmio {
__u32 addr; __u32 addr;
__u32 flags;
#define DRM_XE_MMIO_8BIT 0x0 #define DRM_XE_MMIO_8BIT 0x0
#define DRM_XE_MMIO_16BIT 0x1 #define DRM_XE_MMIO_16BIT 0x1
#define DRM_XE_MMIO_32BIT 0x2 #define DRM_XE_MMIO_32BIT 0x2
@ -654,6 +891,7 @@ struct drm_xe_mmio {
#define DRM_XE_MMIO_BITS_MASK 0x3 #define DRM_XE_MMIO_BITS_MASK 0x3
#define DRM_XE_MMIO_READ 0x4 #define DRM_XE_MMIO_READ 0x4
#define DRM_XE_MMIO_WRITE 0x8 #define DRM_XE_MMIO_WRITE 0x8
__u32 flags;
__u64 value; __u64 value;
@ -664,8 +902,9 @@ struct drm_xe_mmio {
/** /**
* struct drm_xe_wait_user_fence - wait user fence * struct drm_xe_wait_user_fence - wait user fence
* *
* Wait on user fence, XE will wakeup on every HW engine interrupt in the * Wait on user fence, XE will wake-up on every HW engine interrupt in the
* instances list and check if user fence is complete: * instances list and check if user fence is complete::
*
* (*addr & MASK) OP (VALUE & MASK) * (*addr & MASK) OP (VALUE & MASK)
* *
* Returns to user on user fence completion or timeout. * Returns to user on user fence completion or timeout.
@ -673,45 +912,69 @@ struct drm_xe_mmio {
struct drm_xe_wait_user_fence { struct drm_xe_wait_user_fence {
/** @extensions: Pointer to the first extension struct, if any */ /** @extensions: Pointer to the first extension struct, if any */
__u64 extensions; __u64 extensions;
union { union {
/** /**
* @addr: user pointer address to wait on, must qword aligned * @addr: user pointer address to wait on, must qword aligned
*/ */
__u64 addr; __u64 addr;
/** /**
* @vm_id: The ID of the VM which encounter an error used with * @vm_id: The ID of the VM which encounter an error used with
* DRM_XE_UFENCE_WAIT_VM_ERROR. Upper 32 bits must be clear. * DRM_XE_UFENCE_WAIT_VM_ERROR. Upper 32 bits must be clear.
*/ */
__u64 vm_id; __u64 vm_id;
}; };
/** @op: wait operation (type of comparison) */
#define DRM_XE_UFENCE_WAIT_EQ 0 #define DRM_XE_UFENCE_WAIT_EQ 0
#define DRM_XE_UFENCE_WAIT_NEQ 1 #define DRM_XE_UFENCE_WAIT_NEQ 1
#define DRM_XE_UFENCE_WAIT_GT 2 #define DRM_XE_UFENCE_WAIT_GT 2
#define DRM_XE_UFENCE_WAIT_GTE 3 #define DRM_XE_UFENCE_WAIT_GTE 3
#define DRM_XE_UFENCE_WAIT_LT 4 #define DRM_XE_UFENCE_WAIT_LT 4
#define DRM_XE_UFENCE_WAIT_LTE 5 #define DRM_XE_UFENCE_WAIT_LTE 5
/** @op: wait operation (type of comparison) */
__u16 op; __u16 op;
/** @flags: wait flags */
#define DRM_XE_UFENCE_WAIT_SOFT_OP (1 << 0) /* e.g. Wait on VM bind */ #define DRM_XE_UFENCE_WAIT_SOFT_OP (1 << 0) /* e.g. Wait on VM bind */
#define DRM_XE_UFENCE_WAIT_ABSTIME (1 << 1) #define DRM_XE_UFENCE_WAIT_ABSTIME (1 << 1)
#define DRM_XE_UFENCE_WAIT_VM_ERROR (1 << 2) #define DRM_XE_UFENCE_WAIT_VM_ERROR (1 << 2)
/** @flags: wait flags */
__u16 flags; __u16 flags;
/** @pad: MBZ */
__u32 pad;
/** @value: compare value */ /** @value: compare value */
__u64 value; __u64 value;
/** @mask: comparison mask */
#define DRM_XE_UFENCE_WAIT_U8 0xffu #define DRM_XE_UFENCE_WAIT_U8 0xffu
#define DRM_XE_UFENCE_WAIT_U16 0xffffu #define DRM_XE_UFENCE_WAIT_U16 0xffffu
#define DRM_XE_UFENCE_WAIT_U32 0xffffffffu #define DRM_XE_UFENCE_WAIT_U32 0xffffffffu
#define DRM_XE_UFENCE_WAIT_U64 0xffffffffffffffffu #define DRM_XE_UFENCE_WAIT_U64 0xffffffffffffffffu
/** @mask: comparison mask */
__u64 mask; __u64 mask;
/** @timeout: how long to wait before bailing, value in jiffies */ /**
* @timeout: how long to wait before bailing, value in nanoseconds.
* Without DRM_XE_UFENCE_WAIT_ABSTIME flag set (relative timeout)
* it contains timeout expressed in nanoseconds to wait (fence will
* expire at now() + timeout).
* When DRM_XE_UFENCE_WAIT_ABSTIME flat is set (absolute timeout) wait
* will end at timeout (uses system MONOTONIC_CLOCK).
* Passing negative timeout leads to neverending wait.
*
* On relative timeout this value is updated with timeout left
* (for restarting the call in case of signal delivery).
* On absolute timeout this value stays intact (restarted call still
* expire at the same point of time).
*/
__s64 timeout; __s64 timeout;
/** /**
* @num_engines: number of engine instances to wait on, must be zero * @num_engines: number of engine instances to wait on, must be zero
* when DRM_XE_UFENCE_WAIT_SOFT_OP set * when DRM_XE_UFENCE_WAIT_SOFT_OP set
*/ */
__u64 num_engines; __u64 num_engines;
/** /**
* @instances: user pointer to array of drm_xe_engine_class_instance to * @instances: user pointer to array of drm_xe_engine_class_instance to
* wait on, must be NULL when DRM_XE_UFENCE_WAIT_SOFT_OP set * wait on, must be NULL when DRM_XE_UFENCE_WAIT_SOFT_OP set
@ -729,6 +992,9 @@ struct drm_xe_vm_madvise {
/** @vm_id: The ID VM in which the VMA exists */ /** @vm_id: The ID VM in which the VMA exists */
__u32 vm_id; __u32 vm_id;
/** @pad: MBZ */
__u32 pad;
/** @range: Number of bytes in the VMA */ /** @range: Number of bytes in the VMA */
__u64 range; __u64 range;
@ -739,6 +1005,9 @@ struct drm_xe_vm_madvise {
* Setting the preferred location will trigger a migrate of the VMA * Setting the preferred location will trigger a migrate of the VMA
* backing store to new location if the backing store is already * backing store to new location if the backing store is already
* allocated. * allocated.
*
* For DRM_XE_VM_MADVISE_PREFERRED_MEM_CLASS usage, see enum
* drm_xe_memory_class.
*/ */
#define DRM_XE_VM_MADVISE_PREFERRED_MEM_CLASS 0 #define DRM_XE_VM_MADVISE_PREFERRED_MEM_CLASS 0
#define DRM_XE_VM_MADVISE_PREFERRED_GT 1 #define DRM_XE_VM_MADVISE_PREFERRED_GT 1
@ -765,14 +1034,18 @@ struct drm_xe_vm_madvise {
*/ */
#define DRM_XE_VM_MADVISE_PRIORITY 5 #define DRM_XE_VM_MADVISE_PRIORITY 5
#define DRM_XE_VMA_PRIORITY_LOW 0 #define DRM_XE_VMA_PRIORITY_LOW 0
#define DRM_XE_VMA_PRIORITY_NORMAL 1 /* Default */ /* Default */
#define DRM_XE_VMA_PRIORITY_HIGH 2 /* Must be elevated user */ #define DRM_XE_VMA_PRIORITY_NORMAL 1
/* Pin the VMA in memory, must be elevated user */ /* Must be user with elevated privileges */
#define DRM_XE_VMA_PRIORITY_HIGH 2
/* Pin the VMA in memory, must be user with elevated privileges */
#define DRM_XE_VM_MADVISE_PIN 6 #define DRM_XE_VM_MADVISE_PIN 6
/** @property: property to set */ /** @property: property to set */
__u32 property; __u32 property;
/** @pad2: MBZ */
__u32 pad2;
/** @value: property value */ /** @value: property value */
__u64 value; __u64 value;
@ -784,4 +1057,4 @@ struct drm_xe_vm_madvise {
} }
#endif #endif
#endif /* _UAPI_XE_DRM_H_ */ #endif /* _XE_DRM_H_ */