mirror of
https://github.com/intel/compute-runtime.git
synced 2025-11-15 10:14:56 +08:00
Remove ftrGT flags support
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
This commit is contained in:
committed by
Compute-Runtime-Automation
parent
07c75c2de3
commit
90d85bee55
@@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2018-2021 Intel Corporation
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* Copyright (C) 2018-2022 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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@@ -23,22 +23,8 @@ class SkuInfoReceiver {
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RECEIVE_FTR(Desktop);
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RECEIVE_FTR(ChannelSwizzlingXOREnabled);
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RECEIVE_FTR(GtBigDie);
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RECEIVE_FTR(GtMediumDie);
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RECEIVE_FTR(GtSmallDie);
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RECEIVE_FTR(GT1);
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RECEIVE_FTR(GT1_5);
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RECEIVE_FTR(GT2);
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RECEIVE_FTR(GT2_5);
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RECEIVE_FTR(GT3);
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RECEIVE_FTR(GT4);
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RECEIVE_FTR(IVBM0M1Platform);
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RECEIVE_FTR(SGTPVSKUStrapPresent);
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RECEIVE_FTR(GTA);
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RECEIVE_FTR(GTC);
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RECEIVE_FTR(GTX);
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RECEIVE_FTR(5Slice);
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RECEIVE_FTR(GpGpuMidBatchPreempt);
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@@ -25,20 +25,8 @@ struct FeatureTableBase {
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// DW0
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uint32_t ftrDesktop : 1;
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uint32_t ftrChannelSwizzlingXOREnabled : 1;
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uint32_t ftrGtBigDie : 1;
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uint32_t ftrGtMediumDie : 1;
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uint32_t ftrGtSmallDie : 1;
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uint32_t ftrGT1 : 1;
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uint32_t ftrGT1_5 : 1;
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uint32_t ftrGT2 : 1;
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uint32_t ftrGT2_5 : 1;
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uint32_t ftrGT3 : 1;
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uint32_t ftrGT4 : 1;
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uint32_t ftrIVBM0M1Platform : 1;
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uint32_t ftrSGTPVSKUStrapPresent : 1;
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uint32_t ftrGTA : 1;
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uint32_t ftrGTC : 1;
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uint32_t ftrGTX : 1;
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uint32_t ftr5Slice : 1;
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uint32_t ftrGpGpuMidBatchPreempt : 1;
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uint32_t ftrGpGpuThreadGroupLevelPreempt : 1;
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@@ -55,7 +43,6 @@ struct FeatureTableBase {
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uint32_t ftr3dMidBatchPreempt : 1;
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uint32_t ftr3dObjectLevelPreempt : 1;
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uint32_t ftrPerCtxtPreemptionGranularityControl : 1;
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// DW1
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uint32_t ftrTileY : 1;
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uint32_t ftrDisplayYTiling : 1;
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uint32_t ftrTranslationTable : 1;
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@@ -68,6 +55,7 @@ struct FeatureTableBase {
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uint32_t ftrVcs2 : 1;
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uint32_t ftrVEBOX : 1;
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uint32_t ftrSingleVeboxSlice : 1;
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// DW1
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uint32_t ftrULT : 1;
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uint32_t ftrLCIA : 1;
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uint32_t ftrGttCacheInvalidation : 1;
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@@ -88,7 +76,6 @@ struct FeatureTableBase {
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uint32_t ftrSimulationMode : 1;
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uint32_t ftrE2ECompression : 1;
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uint32_t ftrLinearCCS : 1;
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//DW2
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uint32_t ftrCCSRing : 1;
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uint32_t ftrCCSNode : 1;
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uint32_t ftrRcsNode : 1;
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@@ -100,14 +87,13 @@ struct FeatureTableBase {
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uint32_t ftrPpgtt64KBWalkOptimization : 1;
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uint32_t ftrUnified3DMediaCompressionFormats : 1;
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uint32_t ftr57bGPUAddressing : 1;
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uint32_t reserved : 21;
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};
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BcsInfoMask ftrBcsInfo = 1;
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union {
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Flags flags;
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std::array<uint32_t, 3> packed = {};
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std::array<uint32_t, 2> packed = {};
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};
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};
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