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Initial DG2 support

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Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
This commit is contained in:
Bartosz Dunajski
2021-11-15 12:23:07 +00:00
committed by Compute-Runtime-Automation
parent b8aa2871bd
commit 91dfa5c2ac
78 changed files with 9884 additions and 1 deletions
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4
cmake/fill_gens.cmake
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@ -9,4 +9,6 @@ list(APPEND ALL_GEN_TYPES "GEN9")
list(APPEND ALL_GEN_TYPES "GEN11")
list(APPEND ALL_GEN_TYPES "GEN12LP")
list(APPEND ALL_GEN_TYPES "XE_HP_CORE")
list(APPEND XEHP_AND_LATER_GENS "XE_HP_CORE")
list(APPEND ALL_GEN_TYPES "XE_HPG_CORE")
list(APPEND XEHP_AND_LATER_GENS "XE_HP_CORE" "XE_HPG_CORE")
list(APPEND DG2_AND_LATER_GENS "XE_HPG_CORE")

27
cmake/setup_platform_flags.cmake
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@ -25,6 +25,15 @@ foreach(GEN_TYPE ${DEVICE_ENQUEUE_DISABLED_GENS})
set(SUPPORT_DEVICE_ENQUEUE_${GEN_TYPE} FALSE CACHE BOOL "Disabled support ${GEN_TYPE} for device side enqueue" FORCE)
endforeach()
foreach(GEN_TYPE ${DG2_AND_LATER_GENS})
if(TESTS_${GEN_TYPE})
set(TESTS_DG2_AND_LATER 1)
endif()
if(SUPPORT_${GEN_TYPE})
set(SUPPORT_DG2_AND_LATER 1)
endif()
endforeach()
# Add supported and tested platforms
if(SUPPORT_GEN8)
set(CORE_GEN8_REVISIONS 0)
@ -234,3 +243,21 @@ if(SUPPORT_XE_HP_CORE)
endif()
endif()
endif()
if(SUPPORT_XE_HPG_CORE)
set(CORE_XE_HPG_CORE_REVISIONS 0)
if(TESTS_XE_HPG_CORE)
ADD_ITEM_FOR_GEN("FAMILY_NAME" "TESTED" "XE_HPG_CORE" "XE_HPG_COREFamily")
endif()
if(SUPPORT_DG2)
set(DG2_XE_HPG_CORE_REVISIONS 0)
ADD_PRODUCT("SUPPORTED" "DG2" "IGFX_DG2")
ADD_PLATFORM_FOR_GEN("SUPPORTED" "XE_HPG_CORE" "DG2" "DG2")
ADD_PLATFORM_FOR_GEN("SUPPORTED_AUX_TRANSLATION" "XE_HPG_CORE" "DG2" "DG2")
ADD_PLATFORM_FOR_GEN("SUPPORTED_IMAGES" "XE_HPG_CORE" "DG2" "DG2")
if(TESTS_DG2)
ADD_ITEM_FOR_GEN("PLATFORMS" "TESTED" "XE_HPG_CORE" "DG2")
ADD_PRODUCT("TESTED" "DG2" "IGFX_DG2")
endif()
endif()
endif()

21
level_zero/core/source/xe_hpg_core/CMakeLists.txt Normal file
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@ -0,0 +1,21 @@
#
# Copyright (C) 2021 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
if(SUPPORT_XE_HPG_CORE)
set(HW_SOURCES_XE_HPG_CORE
${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
${CMAKE_CURRENT_SOURCE_DIR}/debugger_xe_hpg_core.cpp
${CMAKE_CURRENT_SOURCE_DIR}/image_xe_hpg_core.inl
${CMAKE_CURRENT_SOURCE_DIR}/sampler_xe_hpg_core.inl
${CMAKE_CURRENT_SOURCE_DIR}/enable_family_full_l0_xe_hpg_core.cpp
${CMAKE_CURRENT_SOURCE_DIR}/l0_hw_helper_xe_hpg_core.cpp
)
add_subdirectories()
target_sources(${L0_STATIC_LIB_NAME} PRIVATE ${HW_SOURCES_XE_HPG_CORE})
set_property(GLOBAL PROPERTY L0_HW_SOURCES_XE_HPG_CORE ${HW_SOURCES_XE_HPG_CORE})
endif()

19
level_zero/core/source/xe_hpg_core/debugger_xe_hpg_core.cpp Normal file
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@ -0,0 +1,19 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "level_zero/core/source/debugger/debugger_l0.inl"
namespace NEO {
struct XE_HPG_COREFamily;
using GfxFamily = XE_HPG_COREFamily;
} // namespace NEO
namespace L0 {
template class DebuggerL0Hw<NEO::GfxFamily>;
DebuggerL0PopulateFactory<IGFX_XE_HPG_CORE, NEO::GfxFamily> debuggerXeHpgCore;
} // namespace L0

19
level_zero/core/source/xe_hpg_core/dg2/CMakeLists.txt Normal file
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@ -0,0 +1,19 @@
#
# Copyright (C) 2021 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
if(SUPPORT_DG2)
set(HW_SOURCES_XE_HPG_CORE
${HW_SOURCES_XE_HPG_CORE}
${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
${CMAKE_CURRENT_SOURCE_DIR}/cmdlist_dg2.cpp
${CMAKE_CURRENT_SOURCE_DIR}/cmdlist_dg2.h
${CMAKE_CURRENT_SOURCE_DIR}/cmdqueue_dg2.cpp
${CMAKE_CURRENT_SOURCE_DIR}/kernel_dg2.cpp
${CMAKE_CURRENT_SOURCE_DIR}/image_dg2.cpp
${CMAKE_CURRENT_SOURCE_DIR}/sampler_dg2.cpp
PARENT_SCOPE
)
endif()

26
level_zero/core/source/xe_hpg_core/dg2/cmdlist_dg2.cpp Normal file
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@ -0,0 +1,26 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "cmdlist_dg2.h"
#include "level_zero/core/source/cmdlist/cmdlist_hw.inl"
#include "level_zero/core/source/cmdlist/cmdlist_hw_immediate.inl"
#include "level_zero/core/source/cmdlist/cmdlist_hw_xehp_and_later.inl"
#include "cmdlist_extended.inl"
namespace L0 {
template struct CommandListCoreFamily<IGFX_XE_HPG_CORE>;
static CommandListPopulateFactory<IGFX_DG2, CommandListProductFamily<IGFX_DG2>>
populateDG2;
static CommandListImmediatePopulateFactory<IGFX_DG2, CommandListImmediateProductFamily<IGFX_DG2>>
populateDG2Immediate;
} // namespace L0

25
level_zero/core/source/xe_hpg_core/dg2/cmdlist_dg2.h Normal file
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@ -0,0 +1,25 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "level_zero/core/source/cmdlist/cmdlist_hw.h"
#include "level_zero/core/source/cmdlist/cmdlist_hw_immediate.h"
namespace L0 {
template <>
struct CommandListImmediateProductFamily<IGFX_DG2> : public CommandListCoreFamilyImmediate<IGFX_XE_HPG_CORE> {
using CommandListCoreFamilyImmediate::CommandListCoreFamilyImmediate;
};
template <>
struct CommandListProductFamily<IGFX_DG2> : public CommandListCoreFamily<IGFX_XE_HPG_CORE> {
using CommandListCoreFamily::CommandListCoreFamily;
void clearComputeModePropertiesIfNeeded(bool requiresCoherency, uint32_t numGrfRequired, uint32_t threadArbitrationPolicy) override {
finalStreamState.stateComputeMode = {};
finalStreamState.stateComputeMode.setProperties(requiresCoherency, numGrfRequired, threadArbitrationPolicy);
}
};
} // namespace L0

21
level_zero/core/source/xe_hpg_core/dg2/cmdqueue_dg2.cpp Normal file
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@ -0,0 +1,21 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/xe_hpg_core/hw_cmds.h"
#include "shared/source/xe_hpg_core/hw_info.h"
#include "level_zero/core/source/cmdqueue/cmdqueue_hw.inl"
#include "level_zero/core/source/cmdqueue/cmdqueue_xe_hp_core_and_later.inl"
#include "cmdqueue_extended.inl"
namespace L0 {
template struct CommandQueueHw<IGFX_XE_HPG_CORE>;
static CommandQueuePopulateFactory<IGFX_DG2, CommandQueueHw<IGFX_XE_HPG_CORE>>
populateDG2;
} // namespace L0

23
level_zero/core/source/xe_hpg_core/dg2/image_dg2.cpp Normal file
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@ -0,0 +1,23 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "level_zero/core/source/xe_hpg_core/image_xe_hpg_core.inl"
namespace L0 {
template <>
struct ImageProductFamily<IGFX_DG2> : public ImageCoreFamily<IGFX_XE_HPG_CORE> {
using ImageCoreFamily::ImageCoreFamily;
ze_result_t initialize(Device *device, const ze_image_desc_t *desc) override {
return ImageCoreFamily<IGFX_XE_HPG_CORE>::initialize(device, desc);
};
};
static ImagePopulateFactory<IGFX_DG2, ImageProductFamily<IGFX_DG2>> populateDG2;
} // namespace L0

14
level_zero/core/source/xe_hpg_core/dg2/kernel_dg2.cpp Normal file
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@ -0,0 +1,14 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "level_zero/core/source/kernel/kernel_hw.h"
namespace L0 {
static KernelPopulateFactory<IGFX_DG2, KernelHw<IGFX_XE_HPG_CORE>> populateDG2;
} // namespace L0

29
level_zero/core/source/xe_hpg_core/dg2/sampler_dg2.cpp Normal file
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@ -0,0 +1,29 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/debug_settings/debug_settings_manager.h"
#include "level_zero/core/source/xe_hpg_core/sampler_xe_hpg_core.inl"
namespace L0 {
template struct SamplerCoreFamily<IGFX_XE_HPG_CORE>;
template <>
struct SamplerProductFamily<IGFX_DG2> : public SamplerCoreFamily<IGFX_XE_HPG_CORE> {
using SamplerCoreFamily::SamplerCoreFamily;
void appendSamplerStateParams(SAMPLER_STATE *state) override {
if (NEO::DebugManager.flags.ForceSamplerLowFilteringPrecision.get()) {
state->setLowQualityFilter(SAMPLER_STATE::LOW_QUALITY_FILTER_ENABLE);
}
}
ze_result_t initialize(Device *device, const ze_sampler_desc_t *desc) override {
return SamplerCoreFamily<IGFX_XE_HPG_CORE>::initialize(device, desc);
};
};
static SamplerPopulateFactory<IGFX_DG2, SamplerProductFamily<IGFX_DG2>> populateDG2;
} // namespace L0

30
level_zero/core/source/xe_hpg_core/enable_family_full_l0_xe_hpg_core.cpp Normal file
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@ -0,0 +1,30 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/command_stream/aub_command_stream_receiver_hw.h"
#include "shared/source/command_stream/command_stream_receiver_hw.h"
#include "shared/source/command_stream/tbx_command_stream_receiver_hw.h"
#include "shared/source/helpers/populate_factory.h"
#include "level_zero/core/source/helpers/l0_populate_factory.h"
#include "level_zero/core/source/hw_helpers/l0_hw_helper.h"
namespace NEO {
typedef XE_HPG_COREFamily Family;
struct EnableL0XeHpgCore {
EnableL0XeHpgCore() {
populateFactoryTable<AUBCommandStreamReceiverHw<Family>>();
populateFactoryTable<TbxCommandStreamReceiverHw<Family>>();
populateFactoryTable<CommandStreamReceiverHw<Family>>();
L0::populateFactoryTable<L0::L0HwHelperHw<Family>>();
}
};
static EnableL0XeHpgCore enable;
} // namespace NEO

11
level_zero/core/source/xe_hpg_core/image_xe_hpg_core.inl Normal file
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@ -0,0 +1,11 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/xe_hpg_core/hw_cmds.h"
#include "shared/source/xe_hpg_core/hw_info.h"
#include "level_zero/core/source/image/image_hw.inl"

36
level_zero/core/source/xe_hpg_core/l0_hw_helper_xe_hpg_core.cpp Normal file
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@ -0,0 +1,36 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "level_zero/core/source/helpers/l0_populate_factory.h"
#include "level_zero/core/source/hw_helpers/l0_hw_helper_base.inl"
#include "level_zero/core/source/hw_helpers/l0_hw_helper_skl_and_later.inl"
#include "hw_cmds.h"
namespace L0 {
using Family = NEO::XE_HPG_COREFamily;
static auto gfxCore = IGFX_XE_HPG_CORE;
template <>
void populateFactoryTable<L0HwHelperHw<Family>>() {
extern L0HwHelper *l0HwHelperFactory[IGFX_MAX_CORE];
l0HwHelperFactory[gfxCore] = &L0HwHelperHw<Family>::get();
}
template <>
bool L0HwHelperHw<Family>::isResumeWARequired() {
return true;
}
// clang-format off
#include "level_zero/core/source/hw_helpers/l0_hw_helper_tgllp_plus.inl"
// clang-format on
template class L0HwHelperHw<Family>;
} // namespace L0

11
level_zero/core/source/xe_hpg_core/sampler_xe_hpg_core.inl Normal file
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@ -0,0 +1,11 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/xe_hpg_core/hw_cmds.h"
#include "shared/source/xe_hpg_core/hw_info.h"
#include "level_zero/core/source/sampler/sampler_hw.inl"

14
opencl/source/xe_hpg_core/CMakeLists.txt Normal file
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@ -0,0 +1,14 @@
#
# Copyright (C) 2021 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
if(SUPPORT_XE_HPG_CORE)
set(RUNTIME_SRCS_XE_HPG_CORE
${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
)
target_sources(${NEO_STATIC_LIB_NAME} PRIVATE ${RUNTIME_SRCS_XE_HPG_CORE})
set_property(GLOBAL PROPERTY RUNTIME_SRCS_XE_HPG_CORE ${RUNTIME_SRCS_XE_HPG_CORE})
endif()

13
opencl/source/xe_hpg_core/additionall_files_xe_hpg_core.cmake Normal file
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@ -0,0 +1,13 @@
#
# Copyright (C) 2021 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
set(RUNTIME_SRCS_ADDITIONAL_FILES_XE_HPG_CORE
${CMAKE_CURRENT_SOURCE_DIR}/xe_hpg_core/definitions${BRANCH_DIR_SUFFIX}gtpin_setup_xe_hpg_core.inl
)
include_directories(${NEO_SOURCE_DIR}/opencl/source/xe_hpg_core/definitions${BRANCH_DIR_SUFFIX})
target_sources(${NEO_STATIC_LIB_NAME} PRIVATE ${RUNTIME_SRCS_ADDITIONAL_FILES_XE_HPG_CORE})
set_property(GLOBAL PROPERTY RUNTIME_SRCS_ADDITIONAL_FILES_XE_HPG_CORE ${RUNTIME_SRCS_ADDITIONAL_FILES_XE_HPG_CORE})

20
opencl/source/xe_hpg_core/buffer_xe_hpg_core.cpp Normal file
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@ -0,0 +1,20 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/xe_hpg_core/hw_cmds.h"
#include "opencl/source/mem_obj/buffer_base.inl"
namespace NEO {
typedef XE_HPG_COREFamily Family;
static auto gfxCore = IGFX_XE_HPG_CORE;
template class BufferHw<Family>;
#include "opencl/source/mem_obj/buffer_factory_init.inl"
} // namespace NEO

87
opencl/source/xe_hpg_core/cl_hw_helper_xe_hpg_core.cpp Normal file
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@ -0,0 +1,87 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/debug_settings/debug_settings_manager.h"
#include "shared/source/helpers/populate_factory.h"
#include "shared/source/os_interface/hw_info_config.h"
#include "opencl/source/helpers/cl_hw_helper_base.inl"
#include "opencl/source/helpers/cl_hw_helper_xehp_and_later.inl"
#include "opencl/source/helpers/surface_formats.h"
#include "hw_cmds.h"
namespace NEO {
using Family = XE_HPG_COREFamily;
static auto gfxCore = IGFX_XE_HPG_CORE;
template <>
void populateFactoryTable<ClHwHelperHw<Family>>() {
extern ClHwHelper *clHwHelperFactory[IGFX_MAX_CORE];
clHwHelperFactory[gfxCore] = &ClHwHelperHw<Family>::get();
}
template <>
bool ClHwHelperHw<Family>::requiresNonAuxMode(const ArgDescPointer &argAsPtr, const HardwareInfo &hwInfo) const {
if (HwInfoConfig::get(hwInfo.platform.eProductFamily)->allowStatelessCompression(hwInfo)) {
return false;
} else {
return !argAsPtr.isPureStateful();
}
}
template <>
bool ClHwHelperHw<Family>::requiresAuxResolves(const KernelInfo &kernelInfo, const HardwareInfo &hwInfo) const {
if (HwInfoConfig::get(hwInfo.platform.eProductFamily)->allowStatelessCompression(hwInfo)) {
return false;
} else {
return hasStatelessAccessToBuffer(kernelInfo);
}
}
template <>
std::vector<uint32_t> ClHwHelperHw<Family>::getSupportedThreadArbitrationPolicies() const {
return std::vector<uint32_t>{};
}
template <>
bool ClHwHelperHw<Family>::isSupportedKernelThreadArbitrationPolicy() const { return false; }
template <>
cl_version ClHwHelperHw<Family>::getDeviceIpVersion(const HardwareInfo &hwInfo) const {
return makeDeviceIpVersion(12, 7, makeDeviceRevision(hwInfo));
}
static const std::vector<cl_image_format> incompressibleFormats = {
{CL_LUMINANCE, CL_UNORM_INT8},
{CL_LUMINANCE, CL_UNORM_INT16},
{CL_LUMINANCE, CL_HALF_FLOAT},
{CL_LUMINANCE, CL_FLOAT},
{CL_INTENSITY, CL_UNORM_INT8},
{CL_INTENSITY, CL_UNORM_INT16},
{CL_INTENSITY, CL_HALF_FLOAT},
{CL_INTENSITY, CL_FLOAT},
{CL_A, CL_UNORM_INT16},
{CL_A, CL_HALF_FLOAT},
{CL_A, CL_FLOAT}};
template <>
bool ClHwHelperHw<Family>::allowImageCompression(cl_image_format format) const {
for (auto &referenceFormat : incompressibleFormats) {
if (format.image_channel_data_type == referenceFormat.image_channel_data_type &&
format.image_channel_order == referenceFormat.image_channel_order) {
return false;
}
}
return true;
}
template class ClHwHelperHw<Family>;
} // namespace NEO

33
opencl/source/xe_hpg_core/command_queue_xe_hpg_core.cpp Normal file
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@ -0,0 +1,33 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/helpers/populate_factory.h"
#include "shared/source/memory_manager/unified_memory_manager.h"
#include "opencl/source/command_queue/command_queue_hw.h"
#include "opencl/source/command_queue/enqueue_resource_barrier.h"
#include "enqueue_init_dispatch_globals.h"
namespace NEO {
using Family = XE_HPG_COREFamily;
static auto gfxCore = IGFX_XE_HPG_CORE;
} // namespace NEO
#include "opencl/source/command_queue/command_queue_hw_xehp_and_later.inl"
namespace NEO {
template <>
void populateFactoryTable<CommandQueueHw<Family>>() {
extern CommandQueueCreateFunc commandQueueFactory[IGFX_MAX_CORE];
commandQueueFactory[gfxCore] = CommandQueueHw<Family>::create;
}
} // namespace NEO
template class NEO::CommandQueueHw<NEO::Family>;

11
opencl/source/xe_hpg_core/definitions/gtpin_setup_xe_hpg_core.inl Normal file
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@ -0,0 +1,11 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
template <>
uint32_t GTPinHwHelperHw<Family>::getGenVersion() {
return gtpin::GTPIN_GEN_INVALID;
}

38
opencl/source/xe_hpg_core/enable_family_full_ocl_xe_hpg_core.cpp Normal file
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@ -0,0 +1,38 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/command_stream/aub_command_stream_receiver_hw.h"
#include "shared/source/command_stream/command_stream_receiver_hw.h"
#include "shared/source/command_stream/tbx_command_stream_receiver_hw.h"
#include "shared/source/helpers/populate_factory.h"
#include "opencl/source/command_queue/command_queue_hw.h"
#include "opencl/source/device_queue/device_queue_hw.h"
#include "opencl/source/helpers/cl_hw_helper.h"
#include "opencl/source/mem_obj/buffer.h"
#include "opencl/source/mem_obj/image.h"
#include "opencl/source/sampler/sampler.h"
namespace NEO {
typedef XE_HPG_COREFamily Family;
struct EnableOCLXeHpgCore {
EnableOCLXeHpgCore() {
populateFactoryTable<AUBCommandStreamReceiverHw<Family>>();
populateFactoryTable<BufferHw<Family>>();
populateFactoryTable<ClHwHelperHw<Family>>();
populateFactoryTable<CommandQueueHw<Family>>();
populateFactoryTable<CommandStreamReceiverHw<Family>>();
populateFactoryTable<ImageHw<Family>>();
populateFactoryTable<SamplerHw<Family>>();
populateFactoryTable<TbxCommandStreamReceiverHw<Family>>();
}
};
static EnableOCLXeHpgCore enable;
} // namespace NEO

19
opencl/source/xe_hpg_core/gpgpu_walker_xe_hpg_core.cpp Normal file
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@ -0,0 +1,19 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "opencl/source/command_queue/gpgpu_walker_xehp_and_later.inl"
#include "opencl/source/command_queue/hardware_interface_xehp_and_later.inl"
namespace NEO {
template class GpgpuWalkerHelper<XE_HPG_COREFamily>;
template class HardwareInterface<XE_HPG_COREFamily>;
template struct EnqueueOperation<XE_HPG_COREFamily>;
} // namespace NEO

33
opencl/source/xe_hpg_core/gtpin_setup_xe_hpg_core.cpp Normal file
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@ -0,0 +1,33 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "opencl/source/gtpin/gtpin_hw_helper.h"
#include "opencl/source/gtpin/gtpin_hw_helper.inl"
#include "opencl/source/gtpin/gtpin_hw_helper_xehp_and_later.inl"
#include "ocl_igc_shared/gtpin/gtpin_ocl_interface.h"
namespace NEO {
extern GTPinHwHelper *gtpinHwHelperFactory[IGFX_MAX_CORE];
typedef XE_HPG_COREFamily Family;
static const auto gfxFamily = IGFX_XE_HPG_CORE;
template class GTPinHwHelperHw<Family>;
struct GTPinEnableXeHpgCore {
GTPinEnableXeHpgCore() {
gtpinHwHelperFactory[gfxFamily] = &GTPinHwHelperHw<Family>::get();
}
};
#include "gtpin_setup_xe_hpg_core.inl"
static GTPinEnableXeHpgCore gtpinEnable;
} // namespace NEO

19
opencl/source/xe_hpg_core/hardware_commands_helper_xe_hpg_core.cpp Normal file
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@ -0,0 +1,19 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/helpers/cache_flush_xehp_and_later.inl"
#include "shared/source/xe_hpg_core/hw_cmds.h"
#include "opencl/source/helpers/hardware_commands_helper.h"
#include "opencl/source/helpers/hardware_commands_helper_base.inl"
#include "opencl/source/helpers/hardware_commands_helper_xehp_and_later.inl"
namespace NEO {
using FamilyType = XE_HPG_COREFamily;
template struct HardwareCommandsHelper<FamilyType>;
} // namespace NEO

29
opencl/source/xe_hpg_core/image_xe_hpg_core.cpp Normal file
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@ -0,0 +1,29 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/device/device.h"
#include "shared/source/gmm_helper/client_context/gmm_client_context.h"
#include "shared/source/xe_hpg_core/hw_cmds.h"
#include "opencl/source/context/context.h"
#include "opencl/source/mem_obj/image.inl"
namespace NEO {
using Family = XE_HPG_COREFamily;
static auto gfxCore = IGFX_XE_HPG_CORE;
} // namespace NEO
#include "opencl/source/mem_obj/image_xehp_and_later.inl"
namespace NEO {
// clang-format off
#include "opencl/source/mem_obj/image_tgllp_and_later.inl"
#include "opencl/source/mem_obj/image_factory_init.inl"
// clang-format on
} // namespace NEO

17
opencl/source/xe_hpg_core/sampler_xe_hpg_core.cpp Normal file
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@ -0,0 +1,17 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/xe_hpg_core/hw_cmds_base.h"
using Family = NEO::XE_HPG_COREFamily;
constexpr static auto gfxCore = IGFX_XE_HPG_CORE;
#include "opencl/source/sampler/sampler.h"
#include "opencl/source/sampler/sampler.inl"
namespace NEO {
#include "opencl/source/sampler/sampler_factory_init.inl"
} // namespace NEO

1
shared/source/aub_mem_dump/definitions/aub_services.h
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@ -105,6 +105,7 @@ struct CmdServicesMemTraceVersion {
Adls = 37,
XeHP_SDV = 29,
Adlp = 34,
Dg2 = 36,
};
};
struct RecordingMethodValues {

6
shared/source/command_container/CMakeLists.txt
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@ -30,6 +30,12 @@ if(SUPPORT_XEHP_AND_LATER)
)
endif()
if(SUPPORT_DG2_AND_LATER)
list(APPEND NEO_CORE_COMMAND_CONTAINER
${CMAKE_CURRENT_SOURCE_DIR}/command_encoder_xe_hpg_core_and_later.inl
)
endif()
set_property(GLOBAL PROPERTY NEO_CORE_COMMAND_CONTAINER ${NEO_CORE_COMMAND_CONTAINER})
add_subdirectories()

31
shared/source/command_container/command_encoder_xe_hpg_core_and_later.inl Normal file
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@ -0,0 +1,31 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/command_container/command_encoder.h"
#include "shared/source/helpers/hw_info.h"
#include "hw_cmds.h"
namespace NEO {
template <>
void EncodeSurfaceState<Family>::encodeExtraCacheSettings(R_SURFACE_STATE *surfaceState, const HardwareInfo &hwInfo) {
surfaceState->setL1CachePolicyL1CacheControl(R_SURFACE_STATE::L1_CACHE_POLICY_WBP);
if (DebugManager.flags.OverrideL1CacheControlInSurfaceState.get() != -1) {
surfaceState->setL1CachePolicyL1CacheControl(static_cast<R_SURFACE_STATE::L1_CACHE_POLICY>(DebugManager.flags.OverrideL1CacheControlInSurfaceState.get()));
}
}
template <typename GfxFamily>
void EncodeEnableRayTracing<GfxFamily>::programEnableRayTracing(LinearStream &commandStream, GraphicsAllocation &backBuffer) {
auto cmd = GfxFamily::cmd3dStateBtd;
cmd.getBtdStateBody().setPerDssMemoryBackedBufferSize(static_cast<typename GfxFamily::_3DSTATE_BTD_BODY::PER_DSS_MEMORY_BACKED_BUFFER_SIZE>(RayTracingHelper::getMemoryBackedFifoSizeToPatch()));
cmd.getBtdStateBody().setMemoryBackedBufferBasePointer(backBuffer.getGpuAddress());
*commandStream.getSpaceForCmd<typename GfxFamily::_3DSTATE_BTD>() = cmd;
}
} // namespace NEO

6
shared/source/command_stream/CMakeLists.txt
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@ -72,5 +72,11 @@ if(SUPPORT_XEHP_AND_LATER)
)
endif()
if(SUPPORT_DG2_AND_LATER)
list(APPEND NEO_CORE_COMMAND_STREAM
${CMAKE_CURRENT_SOURCE_DIR}/command_stream_receiver_hw_dg2_and_later.inl
)
endif()
set_property(GLOBAL PROPERTY NEO_CORE_COMMAND_STREAM ${NEO_CORE_COMMAND_STREAM})
add_subdirectories()

64
shared/source/command_stream/command_stream_receiver_hw_dg2_and_later.inl Normal file
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@ -0,0 +1,64 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/command_stream/command_stream_receiver_hw.h"
#include "shared/source/command_stream/device_command_stream.h"
#include "shared/source/helpers/ray_tracing_helper.h"
#include "shared/source/os_interface/hw_info_config.h"
namespace NEO {
using _3DSTATE_BTD = typename Family::_3DSTATE_BTD;
using _3DSTATE_BTD_BODY = typename Family::_3DSTATE_BTD_BODY;
using PIPE_CONTROL = typename Family::PIPE_CONTROL;
template <typename GfxFamily>
inline void CommandStreamReceiverHw<GfxFamily>::setPipeControlPriorToNonPipelinedStateCommandExtraProperties(PipeControlArgs &args) {
args.unTypedDataPortCacheFlush = true;
}
template <>
void CommandStreamReceiverHw<Family>::programPerDssBackedBuffer(LinearStream &commandStream, Device &device, DispatchFlags &dispatchFlags) {
if (dispatchFlags.usePerDssBackedBuffer && !isPerDssBackedBufferSent) {
DEBUG_BREAK_IF(perDssBackedBuffer == nullptr);
auto _3dStateBtd = commandStream.getSpaceForCmd<_3DSTATE_BTD>();
_3DSTATE_BTD cmd = Family::cmd3dStateBtd;
cmd.getBtdStateBody().setPerDssMemoryBackedBufferSize(static_cast<_3DSTATE_BTD_BODY::PER_DSS_MEMORY_BACKED_BUFFER_SIZE>(RayTracingHelper::getMemoryBackedFifoSizeToPatch()));
cmd.getBtdStateBody().setMemoryBackedBufferBasePointer(perDssBackedBuffer->getGpuAddress());
*_3dStateBtd = cmd;
isPerDssBackedBufferSent = true;
}
}
template <>
size_t CommandStreamReceiverHw<Family>::getCmdSizeForPerDssBackedBuffer(const HardwareInfo &hwInfo) {
size_t size = sizeof(_3DSTATE_BTD);
auto hwInfoConfig = HwInfoConfig::get(hwInfo.platform.eProductFamily);
if (hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs())) {
size += sizeof(typename Family::PIPE_CONTROL);
}
return size;
}
template <typename GfxFamily>
inline void CommandStreamReceiverHw<GfxFamily>::addPipeControlBefore3dState(LinearStream &commandStream, DispatchFlags &dispatchFlags) {
auto &hwInfo = peekHwInfo();
auto hwInfoConfig = HwInfoConfig::get(hwInfo.platform.eProductFamily);
PipeControlArgs args(true);
if (hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs()) && dispatchFlags.usePerDssBackedBuffer && !isPerDssBackedBufferSent) {
DEBUG_BREAK_IF(perDssBackedBuffer == nullptr);
addPipeControlPriorToNonPipelinedStateCommand(commandStream, args);
}
}
} // namespace NEO

3
shared/source/gen_common/aub_mapper.h
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@ -21,3 +21,6 @@
#ifdef SUPPORT_XE_HP_CORE
#include "shared/source/xe_hp_core/aub_mapper.h"
#endif
#ifdef SUPPORT_XE_HPG_CORE
#include "shared/source/xe_hpg_core/aub_mapper.h"
#endif

7487
shared/source/generated/xe_hpg_core/hw_cmds_generated_xe_hpg_core.inl Normal file
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File diff suppressed because it is too large Load Diff

6
shared/source/helpers/CMakeLists.txt
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@ -144,6 +144,12 @@ if(SUPPORT_XEHP_AND_LATER)
)
endif()
if(SUPPORT_DG2_AND_LATER)
list(APPEND NEO_CORE_HELPERS
${CMAKE_CURRENT_SOURCE_DIR}/hw_helper_dg2_and_later.inl
)
endif()
set(NEO_CORE_HELPERS_GMM_CALLBACKS_WINDOWS
${CMAKE_CURRENT_SOURCE_DIR}/windows/gmm_callbacks.cpp
${CMAKE_CURRENT_SOURCE_DIR}/windows/gmm_callbacks.h

3
shared/source/helpers/definitions/hw_cmds.h
View File

@ -21,3 +21,6 @@
#ifdef SUPPORT_XE_HP_CORE
#include "shared/source/xe_hp_core/hw_cmds.h"
#endif
#ifdef SUPPORT_XE_HPG_CORE
#include "shared/source/xe_hpg_core/hw_cmds.h"
#endif

61
shared/source/helpers/hw_helper_dg2_and_later.inl Normal file
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@ -0,0 +1,61 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/command_container/command_encoder.h"
#include "shared/source/helpers/hw_helper.h"
#include "pipe_control_args.h"
namespace NEO {
template <typename GfxFamily>
inline void MemorySynchronizationCommands<GfxFamily>::setPipeControlExtraProperties(PIPE_CONTROL &pipeControl, PipeControlArgs &args) {
pipeControl.setHdcPipelineFlush(args.hdcPipelineFlush);
pipeControl.setUnTypedDataPortCacheFlush(args.unTypedDataPortCacheFlush);
pipeControl.setCompressionControlSurfaceCcsFlush(args.compressionControlSurfaceCcsFlush);
pipeControl.setWorkloadPartitionIdOffsetEnable(args.workloadPartitionOffset);
pipeControl.setAmfsFlushEnable(args.amfsFlushEnable);
if (DebugManager.flags.FlushAllCaches.get()) {
pipeControl.setHdcPipelineFlush(true);
pipeControl.setUnTypedDataPortCacheFlush(true);
pipeControl.setCompressionControlSurfaceCcsFlush(true);
}
if (DebugManager.flags.DoNotFlushCaches.get()) {
pipeControl.setHdcPipelineFlush(false);
pipeControl.setUnTypedDataPortCacheFlush(false);
pipeControl.setCompressionControlSurfaceCcsFlush(false);
}
}
template <typename GfxFamily>
inline void MemorySynchronizationCommands<GfxFamily>::setPostSyncExtraProperties(PipeControlArgs &args, const HardwareInfo &hwInfo) {
if (hwInfo.featureTable.ftrLocalMemory) {
args.hdcPipelineFlush = true;
args.unTypedDataPortCacheFlush = true;
}
}
template <typename GfxFamily>
inline void MemorySynchronizationCommands<GfxFamily>::setCacheFlushExtraProperties(PipeControlArgs &args) {
args.hdcPipelineFlush = true;
args.unTypedDataPortCacheFlush = true;
}
template <>
void MemorySynchronizationCommands<Family>::setPipeControlWAFlags(PIPE_CONTROL &pipeControl) {
pipeControl.setCommandStreamerStallEnable(true);
pipeControl.setHdcPipelineFlush(true);
pipeControl.setUnTypedDataPortCacheFlush(true);
}
template <>
bool HwHelperHw<Family>::additionalPipeControlArgsRequired() const {
return true;
}
} // namespace NEO

4
shared/source/os_interface/CMakeLists.txt
View File

@ -48,5 +48,9 @@ if(SUPPORT_XEHP_AND_LATER)
list(APPEND NEO_CORE_OS_INTERFACE ${CMAKE_CURRENT_SOURCE_DIR}/hw_info_config_xehp_and_later.inl)
endif()
if(SUPPORT_DG2_AND_LATER)
list(APPEND NEO_CORE_OS_INTERFACE ${CMAKE_CURRENT_SOURCE_DIR}/hw_info_config_dg2_and_later.inl)
endif()
set_property(GLOBAL PROPERTY NEO_CORE_OS_INTERFACE ${NEO_CORE_OS_INTERFACE})
add_subdirectories()

17
shared/source/os_interface/hw_info_config_dg2_and_later.inl Normal file
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@ -0,0 +1,17 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/os_interface/hw_info_config.h"
namespace NEO {
template <PRODUCT_FAMILY gfxProduct>
bool HwInfoConfigHw<gfxProduct>::heapInLocalMem(const HardwareInfo &hwInfo) const {
return true;
}
} // namespace NEO

9
shared/source/xe_hpg_core/CMakeLists.txt Normal file
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@ -0,0 +1,9 @@
#
# Copyright (C) 2021 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
if(SUPPORT_XE_HPG_CORE)
add_subdirectories()
endif()

25
shared/source/xe_hpg_core/aub_command_stream_receiver_xe_hpg_core.cpp Normal file
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@ -0,0 +1,25 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/command_stream/aub_command_stream_receiver_hw_xehp_and_later.inl"
#include "shared/source/helpers/array_count.h"
#include "shared/source/helpers/populate_factory.h"
namespace NEO {
typedef XE_HPG_COREFamily Family;
static auto gfxCore = IGFX_XE_HPG_CORE;
template <>
void populateFactoryTable<AUBCommandStreamReceiverHw<Family>>() {
extern AubCommandStreamReceiverCreateFunc aubCommandStreamReceiverFactory[IGFX_MAX_CORE];
UNRECOVERABLE_IF(!isInRange(gfxCore, aubCommandStreamReceiverFactory));
aubCommandStreamReceiverFactory[gfxCore] = AUBCommandStreamReceiverHw<Family>::create;
}
template class AUBCommandStreamReceiverHw<Family>;
} // namespace NEO

30
shared/source/xe_hpg_core/aub_mapper.h Normal file
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@ -0,0 +1,30 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "shared/source/aub/aub_mapper_base.h"
#include "shared/source/helpers/constants.h"
#include "engine_node.h"
namespace NEO {
struct XE_HPG_COREFamily;
template <>
struct AUBFamilyMapper<XE_HPG_COREFamily> {
enum { device = AubMemDump::DeviceValues::Dg2 };
using AubTraits = AubMemDump::Traits<device, MemoryConstants::GfxAddressBits>;
static const AubMemDump::LrcaHelper *const csTraits[aub_stream::NUM_ENGINES];
static const MMIOList globalMMIO;
static const MMIOList *perEngineMMIO[aub_stream::NUM_ENGINES];
typedef AubMemDump::AubDump<AubTraits> AUB;
};
} // namespace NEO

20
shared/source/xe_hpg_core/aub_mem_dump_xe_hpg_core.cpp Normal file
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@ -0,0 +1,20 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/aub/aub_helper_xehp_and_later.inl"
#include "aub_mem_dump.h"
namespace NEO {
struct XE_HPG_COREFamily;
using Family = NEO::XE_HPG_COREFamily;
constexpr static auto deviceValue = AubMemDump::DeviceValues::Dg2;
template class AubHelperHw<Family>;
} // namespace NEO
#include "shared/source/aub_mem_dump/aub_mem_dump_xehp_and_later.inl"

191
shared/source/xe_hpg_core/command_encoder_xe_hpg_core.cpp Normal file
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@ -0,0 +1,191 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/command_container/command_encoder.h"
#include "shared/source/command_container/command_encoder.inl"
#include "shared/source/command_container/command_encoder_xehp_and_later.inl"
#include "shared/source/command_container/encode_compute_mode_tgllp_and_later.inl"
#include "shared/source/command_stream/stream_properties.h"
#include "shared/source/os_interface/hw_info_config.h"
#include "shared/source/xe_hpg_core/hw_cmds_base.h"
namespace NEO {
using Family = XE_HPG_COREFamily;
}
#include "shared/source/command_container/command_encoder_xe_hpg_core_and_later.inl"
#include "shared/source/command_container/image_surface_state/compression_params_tgllp_and_later.inl"
#include "shared/source/command_container/image_surface_state/compression_params_xehp_and_later.inl"
namespace NEO {
template <>
void EncodeDispatchKernel<Family>::adjustTimestampPacket(WALKER_TYPE &walkerCmd, const HardwareInfo &hwInfo) {
auto &postSyncData = walkerCmd.getPostSync();
postSyncData.setDataportSubsliceCacheFlush(true);
}
template <>
void EncodeDispatchKernel<Family>::appendAdditionalIDDFields(INTERFACE_DESCRIPTOR_DATA *pInterfaceDescriptor, const HardwareInfo &hwInfo, const uint32_t threadsPerThreadGroup, uint32_t slmTotalSize, SlmPolicy slmPolicy) {
using PREFERRED_SLM_SIZE_OVERRIDE = typename Family::INTERFACE_DESCRIPTOR_DATA::PREFERRED_SLM_SIZE_OVERRIDE;
using PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS = typename Family::INTERFACE_DESCRIPTOR_DATA::PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS;
const uint32_t threadsPerDssCount = hwInfo.gtSystemInfo.ThreadCount / hwInfo.gtSystemInfo.DualSubSliceCount;
const uint32_t workGroupCountPerDss = threadsPerDssCount / threadsPerThreadGroup;
const uint32_t workgroupSlmSize = HwHelperHw<Family>::get().alignSlmSize(slmTotalSize);
uint32_t slmSize = 0u;
switch (slmPolicy) {
case SlmPolicy::SlmPolicyLargeData:
slmSize = workgroupSlmSize;
break;
case SlmPolicy::SlmPolicyLargeSlm:
default:
slmSize = workgroupSlmSize * workGroupCountPerDss;
break;
}
struct SizeToPreferredSlmValue {
uint32_t upperLimit;
PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS valueToProgram;
};
const std::array<SizeToPreferredSlmValue, 6> ranges = {{
// upper limit, retVal
{0, PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS::PREFERRED_SLM_SIZE_IS_0K},
{16 * KB, PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS::PREFERRED_SLM_SIZE_IS_16K},
{32 * KB, PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS::PREFERRED_SLM_SIZE_IS_32K},
{64 * KB, PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS::PREFERRED_SLM_SIZE_IS_64K},
{96 * KB, PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS::PREFERRED_SLM_SIZE_IS_96K},
}};
auto programmableIdPreferredSlmSize = PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS::PREFERRED_SLM_SIZE_IS_128K;
for (auto &range : ranges) {
if (slmSize <= range.upperLimit) {
programmableIdPreferredSlmSize = range.valueToProgram;
break;
}
}
pInterfaceDescriptor->setPreferredSlmSizeOverride(PREFERRED_SLM_SIZE_OVERRIDE::PREFERRED_SLM_SIZE_OVERRIDE_IS_ENABLED);
if (HwInfoConfig::get(hwInfo.platform.eProductFamily)->isAllocationSizeAdjustmentRequired(hwInfo)) {
pInterfaceDescriptor->setPreferredSlmAllocationSizePerDss(PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS::PREFERRED_SLM_SIZE_IS_128K);
} else {
pInterfaceDescriptor->setPreferredSlmAllocationSizePerDss(programmableIdPreferredSlmSize);
}
if (DebugManager.flags.OverridePreferredSlmAllocationSizePerDss.get() != -1) {
auto toProgram =
static_cast<PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS>(DebugManager.flags.OverridePreferredSlmAllocationSizePerDss.get());
pInterfaceDescriptor->setPreferredSlmAllocationSizePerDss(toProgram);
}
}
template <>
void EncodeDispatchKernel<Family>::adjustInterfaceDescriptorData(INTERFACE_DESCRIPTOR_DATA &interfaceDescriptor, const HardwareInfo &hwInfo) {
const auto &hwInfoConfig = *HwInfoConfig::get(hwInfo.platform.eProductFamily);
if (hwInfoConfig.isDisableOverdispatchAvailable(hwInfo)) {
if (interfaceDescriptor.getNumberOfThreadsInGpgpuThreadGroup() == 1) {
interfaceDescriptor.setThreadGroupDispatchSize(2u);
} else {
interfaceDescriptor.setThreadGroupDispatchSize(3u);
}
}
if (DebugManager.flags.ForceThreadGroupDispatchSize.get() != -1) {
interfaceDescriptor.setThreadGroupDispatchSize(DebugManager.flags.ForceThreadGroupDispatchSize.get());
}
}
template <>
void EncodeDispatchKernel<Family>::programBarrierEnable(INTERFACE_DESCRIPTOR_DATA &interfaceDescriptor, uint32_t value, const HardwareInfo &hwInfo) {
interfaceDescriptor.setNumberOfBarriers(value);
}
template <>
void EncodeDispatchKernel<Family>::encodeAdditionalWalkerFields(const HardwareInfo &hwInfo, WALKER_TYPE &walkerCmd) {
if (HwInfoConfig::get(hwInfo.platform.eProductFamily)->isPrefetchDisablingRequired(hwInfo)) {
walkerCmd.setL3PrefetchDisable(true);
}
if (DebugManager.flags.ForceL3PrefetchForComputeWalker.get() != -1) {
walkerCmd.setL3PrefetchDisable(!DebugManager.flags.ForceL3PrefetchForComputeWalker.get());
}
}
template <>
void EncodeComputeMode<Family>::adjustComputeMode(LinearStream &csr, void *const stateComputeModePtr, StateComputeModeProperties &properties, const HardwareInfo &hwInfo) {
using STATE_COMPUTE_MODE = typename Family::STATE_COMPUTE_MODE;
using FORCE_NON_COHERENT = typename STATE_COMPUTE_MODE::FORCE_NON_COHERENT;
using PIXEL_ASYNC_COMPUTE_THREAD_LIMIT = typename STATE_COMPUTE_MODE::PIXEL_ASYNC_COMPUTE_THREAD_LIMIT;
using Z_PASS_ASYNC_COMPUTE_THREAD_LIMIT = typename STATE_COMPUTE_MODE::Z_PASS_ASYNC_COMPUTE_THREAD_LIMIT;
STATE_COMPUTE_MODE stateComputeMode = (stateComputeModePtr != nullptr) ? *(static_cast<STATE_COMPUTE_MODE *>(stateComputeModePtr))
: Family::cmdInitStateComputeMode;
auto maskBits = stateComputeMode.getMaskBits();
if (properties.zPassAsyncComputeThreadLimit.isDirty) {
auto limitValue = static_cast<Z_PASS_ASYNC_COMPUTE_THREAD_LIMIT>(properties.zPassAsyncComputeThreadLimit.value);
stateComputeMode.setZPassAsyncComputeThreadLimit(limitValue);
maskBits |= Family::stateComputeModeZPassAsyncComputeThreadLimitMask;
}
if (properties.pixelAsyncComputeThreadLimit.isDirty) {
auto limitValue = static_cast<PIXEL_ASYNC_COMPUTE_THREAD_LIMIT>(properties.pixelAsyncComputeThreadLimit.value);
stateComputeMode.setPixelAsyncComputeThreadLimit(limitValue);
maskBits |= Family::stateComputeModePixelAsyncComputeThreadLimitMask;
}
if (properties.largeGrfMode.isDirty) {
stateComputeMode.setLargeGrfMode(properties.largeGrfMode.value);
maskBits |= Family::stateComputeModeLargeGrfModeMask;
}
stateComputeMode.setMaskBits(maskBits);
HwInfoConfig::get(hwInfo.platform.eProductFamily)->setForceNonCoherent(&stateComputeMode, properties);
auto buffer = csr.getSpaceForCmd<STATE_COMPUTE_MODE>();
*buffer = stateComputeMode;
}
template <>
void EncodeSurfaceState<Family>::appendParamsForImageFromBuffer(R_SURFACE_STATE *surfaceState) {
const auto ccsMode = R_SURFACE_STATE::AUXILIARY_SURFACE_MODE::AUXILIARY_SURFACE_MODE_AUX_CCS_E;
if (ccsMode == surfaceState->getAuxiliarySurfaceMode() && R_SURFACE_STATE::SURFACE_TYPE::SURFACE_TYPE_SURFTYPE_2D == surfaceState->getSurfaceType()) {
if (DebugManager.flags.DecompressInL3ForImage2dFromBuffer.get() != 0) {
surfaceState->setAuxiliarySurfaceMode(AUXILIARY_SURFACE_MODE::AUXILIARY_SURFACE_MODE_AUX_NONE);
surfaceState->setDecompressInL3(1);
surfaceState->setMemoryCompressionEnable(1);
surfaceState->setMemoryCompressionType(R_SURFACE_STATE::MEMORY_COMPRESSION_TYPE::MEMORY_COMPRESSION_TYPE_3D_COMPRESSION);
}
}
}
template struct EncodeDispatchKernel<Family>;
template struct EncodeStates<Family>;
template struct EncodeMath<Family>;
template struct EncodeMathMMIO<Family>;
template struct EncodeIndirectParams<Family>;
template struct EncodeSetMMIO<Family>;
template struct EncodeMediaInterfaceDescriptorLoad<Family>;
template struct EncodeStateBaseAddress<Family>;
template struct EncodeStoreMMIO<Family>;
template struct EncodeSurfaceState<Family>;
template struct EncodeComputeMode<Family>;
template struct EncodeAtomic<Family>;
template struct EncodeSempahore<Family>;
template struct EncodeBatchBufferStartOrEnd<Family>;
template struct EncodeMiFlushDW<Family>;
template struct EncodeMemoryPrefetch<Family>;
template struct EncodeMiArbCheck<Family>;
template struct EncodeWA<Family>;
template struct EncodeEnableRayTracing<Family>;
template struct EncodeNoop<Family>;
} // namespace NEO

97
shared/source/xe_hpg_core/command_stream_receiver_hw_xe_hpg_core.cpp Normal file
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@ -0,0 +1,97 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/xe_hpg_core/hw_cmds.h"
#include "shared/source/xe_hpg_core/hw_info.h"
using Family = NEO::XE_HPG_COREFamily;
#include "shared/source/command_stream/command_stream_receiver_hw_dg2_and_later.inl"
#include "shared/source/command_stream/command_stream_receiver_hw_tgllp_and_later.inl"
#include "shared/source/command_stream/command_stream_receiver_hw_xehp_and_later.inl"
#include "shared/source/helpers/blit_commands_helper_xehp_and_later.inl"
#include "shared/source/helpers/populate_factory.h"
#include "shared/source/os_interface/hw_info_config.h"
namespace NEO {
static auto gfxCore = IGFX_XE_HPG_CORE;
template <>
bool ImplicitFlushSettings<Family>::defaultSettingForNewResource = false;
template <>
bool ImplicitFlushSettings<Family>::defaultSettingForGpuIdle = false;
template class ImplicitFlushSettings<Family>;
template <>
void populateFactoryTable<CommandStreamReceiverHw<Family>>() {
extern CommandStreamReceiverCreateFunc commandStreamReceiverFactory[2 * IGFX_MAX_CORE];
commandStreamReceiverFactory[gfxCore] = DeviceCommandStreamReceiver<Family>::create;
}
template <>
MemoryCompressionState CommandStreamReceiverHw<Family>::getMemoryCompressionState(bool auxTranslationRequired, const HardwareInfo &hwInfo) const {
auto memoryCompressionState = MemoryCompressionState::NotApplicable;
const auto &hwInfoConfig = *HwInfoConfig::get(hwInfo.platform.eProductFamily);
if (hwInfoConfig.allowStatelessCompression(hwInfo)) {
memoryCompressionState = auxTranslationRequired ? MemoryCompressionState::Disabled : MemoryCompressionState::Enabled;
}
return memoryCompressionState;
}
template <>
void CommandStreamReceiverHw<Family>::programAdditionalStateBaseAddress(LinearStream &csr, typename Family::STATE_BASE_ADDRESS &cmd, Device &device) {
using STATE_BASE_ADDRESS = Family::STATE_BASE_ADDRESS;
auto &hwInfo = *device.getRootDeviceEnvironment().getHardwareInfo();
auto &hwInfoConfig = *HwInfoConfig::get(hwInfo.platform.eProductFamily);
if (hwInfoConfig.isAdditionalStateBaseAddressWARequired(hwInfo)) {
auto pCmd = static_cast<STATE_BASE_ADDRESS *>(csr.getSpace(sizeof(STATE_BASE_ADDRESS)));
*pCmd = cmd;
}
}
template class CommandStreamReceiverHw<Family>;
template struct BlitCommandsHelper<Family>;
const Family::COMPUTE_WALKER Family::cmdInitGpgpuWalker = Family::COMPUTE_WALKER::sInit();
const Family::CFE_STATE Family::cmdInitCfeState = Family::CFE_STATE::sInit();
const Family::INTERFACE_DESCRIPTOR_DATA Family::cmdInitInterfaceDescriptorData = Family::INTERFACE_DESCRIPTOR_DATA::sInit();
const Family::MI_BATCH_BUFFER_START Family::cmdInitBatchBufferStart = Family::MI_BATCH_BUFFER_START::sInit();
const Family::MI_BATCH_BUFFER_END Family::cmdInitBatchBufferEnd = Family::MI_BATCH_BUFFER_END::sInit();
const Family::PIPE_CONTROL Family::cmdInitPipeControl = Family::PIPE_CONTROL::sInit();
const Family::STATE_COMPUTE_MODE Family::cmdInitStateComputeMode = Family::STATE_COMPUTE_MODE::sInit();
const Family::_3DSTATE_BINDING_TABLE_POOL_ALLOC Family::cmdInitStateBindingTablePoolAlloc =
Family::_3DSTATE_BINDING_TABLE_POOL_ALLOC::sInit();
const Family::MI_SEMAPHORE_WAIT Family::cmdInitMiSemaphoreWait = Family::MI_SEMAPHORE_WAIT::sInit();
const Family::RENDER_SURFACE_STATE Family::cmdInitRenderSurfaceState = Family::RENDER_SURFACE_STATE::sInit();
const Family::POSTSYNC_DATA Family::cmdInitPostSyncData = Family::POSTSYNC_DATA::sInit();
const Family::MI_SET_PREDICATE Family::cmdInitSetPredicate = Family::MI_SET_PREDICATE::sInit();
const Family::MI_LOAD_REGISTER_IMM Family::cmdInitLoadRegisterImm = Family::MI_LOAD_REGISTER_IMM::sInit();
const Family::MI_LOAD_REGISTER_REG Family::cmdInitLoadRegisterReg = Family::MI_LOAD_REGISTER_REG::sInit();
const Family::MI_LOAD_REGISTER_MEM Family::cmdInitLoadRegisterMem = Family::MI_LOAD_REGISTER_MEM::sInit();
const Family::MI_STORE_DATA_IMM Family::cmdInitStoreDataImm = Family::MI_STORE_DATA_IMM::sInit();
const Family::MI_STORE_REGISTER_MEM Family::cmdInitStoreRegisterMem = Family::MI_STORE_REGISTER_MEM::sInit();
const Family::MI_NOOP Family::cmdInitNoop = Family::MI_NOOP::sInit();
const Family::MI_REPORT_PERF_COUNT Family::cmdInitReportPerfCount = Family::MI_REPORT_PERF_COUNT::sInit();
const Family::MI_ATOMIC Family::cmdInitAtomic = Family::MI_ATOMIC::sInit();
const Family::PIPELINE_SELECT Family::cmdInitPipelineSelect = Family::PIPELINE_SELECT::sInit();
const Family::MI_ARB_CHECK Family::cmdInitArbCheck = Family::MI_ARB_CHECK::sInit();
const Family::STATE_BASE_ADDRESS Family::cmdInitStateBaseAddress = Family::STATE_BASE_ADDRESS::sInit();
const Family::MEDIA_SURFACE_STATE Family::cmdInitMediaSurfaceState = Family::MEDIA_SURFACE_STATE::sInit();
const Family::SAMPLER_STATE Family::cmdInitSamplerState = Family::SAMPLER_STATE::sInit();
const Family::BINDING_TABLE_STATE Family::cmdInitBindingTableState = Family::BINDING_TABLE_STATE::sInit();
const Family::MI_USER_INTERRUPT Family::cmdInitUserInterrupt = Family::MI_USER_INTERRUPT::sInit();
const Family::MI_CONDITIONAL_BATCH_BUFFER_END cmdInitConditionalBatchBufferEnd = Family::MI_CONDITIONAL_BATCH_BUFFER_END::sInit();
const Family::L3_CONTROL Family::cmdInitL3Control = Family::L3_CONTROL::sInit();
const Family::L3_FLUSH_ADDRESS_RANGE Family::cmdInitL3FlushAddressRange = Family::L3_FLUSH_ADDRESS_RANGE::sInit();
const Family::MI_FLUSH_DW Family::cmdInitMiFlushDw = Family::MI_FLUSH_DW::sInit();
const Family::XY_BLOCK_COPY_BLT Family::cmdInitXyCopyBlt = Family::XY_BLOCK_COPY_BLT::sInit();
const Family::XY_FAST_COLOR_BLT Family::cmdInitXyColorBlt = Family::XY_FAST_COLOR_BLT::sInit();
const Family::_3DSTATE_BTD Family::cmd3dStateBtd = Family::_3DSTATE_BTD::sInit();
const Family::_3DSTATE_BTD_BODY Family::cmd3dStateBtdBody = Family::_3DSTATE_BTD_BODY::sInit();
const Family::STATE_SIP Family::cmdInitStateSip = Family::STATE_SIP::sInit();
} // namespace NEO

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/command_stream/command_stream_receiver_simulated_common_hw_xehp_and_later.inl"
namespace NEO {
typedef XE_HPG_COREFamily Family;
template class CommandStreamReceiverSimulatedCommonHw<Family>;
} // namespace NEO

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/command_stream/device_command_stream.h"
#include "create_command_stream_receiver.inl"
namespace NEO {
template <>
CommandStreamReceiver *createDeviceCommandStreamReceiver<XE_HPG_COREFamily>(bool withAubDump,
ExecutionEnvironment &executionEnvironment,
uint32_t rootDeviceIndex,
const DeviceBitfield deviceBitfield) {
return createCommandStreamReceiver<XE_HPG_COREFamily>(withAubDump, executionEnvironment, rootDeviceIndex, deviceBitfield);
}
} // namespace NEO

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
const HardwareInfo DG2::hwInfo = DG2_CONFIG::hwInfo;
const uint64_t DG2::defaultHardwareInfoConfig = 0;
void setupDG2HardwareInfoImpl(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig) {
if (hwInfoConfig == 0x0) {
// Default config
DG2_2x4x16::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable);
} else {
UNRECOVERABLE_IF(true);
}
}
void (*DG2::setupHardwareInfo)(HardwareInfo *, bool, const uint64_t) = setupDG2HardwareInfoImpl;

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/helpers/hw_helper.h"
#include "shared/source/xe_hpg_core/hw_cmds.h"
namespace NEO {
extern HwHelper *hwHelperFactory[IGFX_MAX_CORE];
typedef XE_HPG_COREFamily Family;
static auto gfxFamily = IGFX_XE_HPG_CORE;
struct EnableCoreXeHpgCore {
EnableCoreXeHpgCore() {
hwHelperFactory[gfxFamily] = &HwHelperHw<Family>::get();
}
};
static EnableCoreXeHpgCore enable;
} // namespace NEO

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/os_interface/hw_info_config.h"
#include "shared/source/xe_hpg_core/hw_cmds.h"
namespace NEO {
static EnableProductHwInfoConfig<IGFX_DG2> enableDG2;
} // namespace NEO

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/helpers/compiler_hw_info_config_base.inl"
#include "shared/source/helpers/compiler_hw_info_config_bdw_and_later.inl"
#include "shared/source/helpers/enable_product.inl"
#include "shared/source/os_interface/hw_info_config.h"
#include "shared/source/xe_hpg_core/hw_cmds.h"
namespace NEO {
#ifdef SUPPORT_DG2
static EnableGfxProductHw<IGFX_DG2> enableGfxProductHwDG2;
static EnableCompilerHwInfoConfig<IGFX_DG2> enableCompilerHwInfoConfigDG2;
#endif
} // namespace NEO

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/command_stream/experimental_command_buffer.inl"
namespace NEO {
typedef XE_HPG_COREFamily GfxFamily;
template void ExperimentalCommandBuffer::injectBufferStart<GfxFamily>(LinearStream &parentStream, size_t cmdBufferOffset);
template size_t ExperimentalCommandBuffer::getRequiredInjectionSize<GfxFamily>() noexcept;
template size_t ExperimentalCommandBuffer::programExperimentalCommandBuffer<GfxFamily>();
template size_t ExperimentalCommandBuffer::getTotalExperimentalSize<GfxFamily>() noexcept;
template void ExperimentalCommandBuffer::addTimeStampPipeControl<GfxFamily>();
template size_t ExperimentalCommandBuffer::getTimeStampPipeControlSize<GfxFamily>() noexcept;
template void ExperimentalCommandBuffer::addExperimentalCommands<GfxFamily>();
template size_t ExperimentalCommandBuffer::getExperimentalCommandsSize<GfxFamily>() noexcept;
} // namespace NEO

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "shared/source/xe_hpg_core/hw_cmds_base.h"
#ifdef SUPPORT_DG2
#include "hw_cmds_dg2.h"
#endif

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "shared/source/commands/bxml_generator_glue.h"
#include "shared/source/helpers/debug_helpers.h"
#include "shared/source/xe_hpg_core/hw_info.h"
#include "igfxfmid.h"
#include <cstddef>
#include <type_traits>
template <class T>
struct CmdParse;
namespace NEO {
struct XE_HPG_CORE {
#include "shared/source/generated/xe_hpg_core/hw_cmds_generated_xe_hpg_core.inl"
static constexpr uint32_t stateComputeModeZPassAsyncComputeThreadLimitMask = 0b111u;
static constexpr uint32_t stateComputeModeForceNonCoherentMask = (0b11u << 3);
static constexpr uint32_t stateComputeModePixelAsyncComputeThreadLimitMask = (0b111u << 7);
static constexpr uint32_t stateComputeModeLargeGrfModeMask = (1u << 15);
static constexpr bool isUsingL3Control = true;
struct DataPortBindlessSurfaceExtendedMessageDescriptor {
union {
struct {
uint32_t bindlessSurfaceOffset : 25;
uint32_t reserved : 6;
};
uint32_t packed;
};
DataPortBindlessSurfaceExtendedMessageDescriptor() {
packed = 0;
}
void setBindlessSurfaceOffset(uint32_t offsetInBindlessSurfaceHeapInBytes) {
bindlessSurfaceOffset = offsetInBindlessSurfaceHeapInBytes >> 6;
}
uint32_t getBindlessSurfaceOffsetToPatch() {
return bindlessSurfaceOffset << 6;
}
};
static_assert(sizeof(DataPortBindlessSurfaceExtendedMessageDescriptor) == sizeof(DataPortBindlessSurfaceExtendedMessageDescriptor::packed), "");
};
struct XE_HPG_COREFamily : public XE_HPG_CORE {
using PARSE = CmdParse<XE_HPG_COREFamily>;
using GfxFamily = XE_HPG_COREFamily;
using WALKER_TYPE = COMPUTE_WALKER;
using VFE_STATE_TYPE = CFE_STATE;
using XY_COPY_BLT = typename GfxFamily::XY_BLOCK_COPY_BLT;
using XY_COLOR_BLT = typename GfxFamily::XY_FAST_COLOR_BLT;
using MI_STORE_REGISTER_MEM_CMD = typename GfxFamily::MI_STORE_REGISTER_MEM;
using TimestampPacketType = uint32_t;
static const COMPUTE_WALKER cmdInitGpgpuWalker;
static const CFE_STATE cmdInitCfeState;
static const INTERFACE_DESCRIPTOR_DATA cmdInitInterfaceDescriptorData;
static const MI_BATCH_BUFFER_END cmdInitBatchBufferEnd;
static const MI_BATCH_BUFFER_START cmdInitBatchBufferStart;
static const PIPE_CONTROL cmdInitPipeControl;
static const STATE_COMPUTE_MODE cmdInitStateComputeMode;
static const _3DSTATE_BINDING_TABLE_POOL_ALLOC cmdInitStateBindingTablePoolAlloc;
static const MI_SEMAPHORE_WAIT cmdInitMiSemaphoreWait;
static const RENDER_SURFACE_STATE cmdInitRenderSurfaceState;
static const POSTSYNC_DATA cmdInitPostSyncData;
static const MI_SET_PREDICATE cmdInitSetPredicate;
static const MI_LOAD_REGISTER_IMM cmdInitLoadRegisterImm;
static const MI_LOAD_REGISTER_REG cmdInitLoadRegisterReg;
static const MI_LOAD_REGISTER_MEM cmdInitLoadRegisterMem;
static const MI_STORE_DATA_IMM cmdInitStoreDataImm;
static const MI_STORE_REGISTER_MEM cmdInitStoreRegisterMem;
static const MI_NOOP cmdInitNoop;
static const MI_REPORT_PERF_COUNT cmdInitReportPerfCount;
static const MI_ATOMIC cmdInitAtomic;
static const PIPELINE_SELECT cmdInitPipelineSelect;
static const MI_ARB_CHECK cmdInitArbCheck;
static const STATE_BASE_ADDRESS cmdInitStateBaseAddress;
static const MEDIA_SURFACE_STATE cmdInitMediaSurfaceState;
static const SAMPLER_STATE cmdInitSamplerState;
static const BINDING_TABLE_STATE cmdInitBindingTableState;
static const MI_USER_INTERRUPT cmdInitUserInterrupt;
static const MI_CONDITIONAL_BATCH_BUFFER_END cmdInitConditionalBatchBufferEnd;
static const L3_CONTROL cmdInitL3Control;
static const L3_FLUSH_ADDRESS_RANGE cmdInitL3FlushAddressRange;
static const MI_FLUSH_DW cmdInitMiFlushDw;
static const XY_BLOCK_COPY_BLT cmdInitXyCopyBlt;
static const XY_FAST_COLOR_BLT cmdInitXyColorBlt;
static const _3DSTATE_BTD cmd3dStateBtd;
static const _3DSTATE_BTD_BODY cmd3dStateBtdBody;
static const STATE_SIP cmdInitStateSip;
static constexpr bool supportsCmdSet(GFXCORE_FAMILY cmdSetBaseFamily) {
return cmdSetBaseFamily == IGFX_XE_HP_CORE;
}
};
} // namespace NEO

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "shared/source/xe_hpg_core/hw_cmds_base.h"
namespace NEO {
struct DG2 : public XE_HPG_COREFamily {
static const PLATFORM platform;
static const HardwareInfo hwInfo;
static const uint64_t defaultHardwareInfoConfig;
static FeatureTable featureTable;
static WorkaroundTable workaroundTable;
// Initial non-zero values for unit tests
static const uint32_t threadsPerEu = 8;
static const uint32_t maxEuPerSubslice = 16;
static const uint32_t maxSlicesSupported = 8;
static const uint32_t maxSubslicesSupported = 32;
static const uint32_t maxDualSubslicesSupported = 32;
static const RuntimeCapabilityTable capabilityTable;
static void (*setupHardwareInfo)(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig);
static void setupFeatureAndWorkaroundTable(HardwareInfo *hwInfo);
};
class DG2_CONFIG : public DG2 {
public:
static void setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable);
static void setupHardwareInfoMultiTile(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, bool setupMultiTile);
static const HardwareInfo hwInfo;
private:
static GT_SYSTEM_INFO gtSystemInfo;
};
#include "hw_cmds_dg2.inl"
} // namespace NEO

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/xe_hpg_core/aub_mapper.h"
#include "shared/source/xe_hpg_core/hw_cmds.h"
using Family = NEO::XE_HPG_COREFamily;
#include "shared/source/helpers/constants.h"
#include "shared/source/helpers/extra_allocation_data_xehp_and_later.inl"
#include "shared/source/helpers/flat_batch_buffer_helper_hw.inl"
#include "shared/source/helpers/hw_helper_base.inl"
#include "shared/source/helpers/hw_helper_dg2_and_later.inl"
#include "shared/source/helpers/hw_helper_tgllp_and_later.inl"
#include "shared/source/helpers/hw_helper_xehp_and_later.inl"
namespace NEO {
template <>
const AuxTranslationMode HwHelperHw<Family>::defaultAuxTranslationMode = AuxTranslationMode::Blit;
template <>
uint32_t HwHelperHw<Family>::getMetricsLibraryGenId() const {
return static_cast<uint32_t>(MetricsLibraryApi::ClientGen::XeHPG);
}
template <>
void HwHelperHw<Family>::adjustDefaultEngineType(HardwareInfo *pHwInfo) {
if (!pHwInfo->featureTable.ftrCCSNode) {
pHwInfo->capabilityTable.defaultEngineType = aub_stream::ENGINE_RCS;
}
if (HwInfoConfig::get(pHwInfo->platform.eProductFamily)->isDefaultEngineTypeAdjustmentRequired(*pHwInfo)) {
pHwInfo->capabilityTable.defaultEngineType = aub_stream::ENGINE_RCS;
}
}
template <>
inline bool HwHelperHw<Family>::isSpecialWorkgroupSizeRequired(const HardwareInfo &hwInfo, bool isSimulation) const {
if (DebugManager.flags.ForceWorkgroupSize1x1x1.get() != -1) {
return static_cast<bool>(DebugManager.flags.ForceWorkgroupSize1x1x1.get());
} else {
return false;
}
}
template <>
bool HwHelperHw<Family>::is1MbAlignmentSupported(const HardwareInfo &hwInfo, bool isCompressionEnabled) const {
return !hwInfo.workaroundTable.waAuxTable64KGranular && isCompressionEnabled;
}
template <>
void HwHelperHw<Family>::setL1CachePolicy(bool useL1Cache, typename Family::RENDER_SURFACE_STATE *surfaceState, const HardwareInfo *hwInfo) {
if (useL1Cache) {
surfaceState->setL1CachePolicyL1CacheControl(Family::RENDER_SURFACE_STATE::L1_CACHE_POLICY_WB);
}
}
template <>
bool HwHelperHw<Family>::isBankOverrideRequired(const HardwareInfo &hwInfo) const {
bool forceOverrideMemoryBankIndex = false;
if (DebugManager.flags.ForceMemoryBankIndexOverride.get() != -1) {
forceOverrideMemoryBankIndex = static_cast<bool>(DebugManager.flags.ForceMemoryBankIndexOverride.get());
}
return forceOverrideMemoryBankIndex;
}
template <>
const StackVec<uint32_t, 6> HwHelperHw<Family>::getThreadsPerEUConfigs() const {
return {4, 8};
}
template <>
std::string HwHelperHw<Family>::getExtensions() const {
std::string extensions;
extensions += "cl_intel_create_buffer_with_properties ";
extensions += "cl_intel_dot_accumulate ";
extensions += "cl_intel_subgroup_local_block_io ";
return extensions;
}
template <>
bool HwHelperHw<Family>::isBufferSizeSuitableForRenderCompression(const size_t size, const HardwareInfo &hwInfo) const {
if (DebugManager.flags.OverrideBufferSuitableForRenderCompression.get() != -1) {
return !!DebugManager.flags.OverrideBufferSuitableForRenderCompression.get();
}
if (HwInfoConfig::get(hwInfo.platform.eProductFamily)->allowStatelessCompression(hwInfo)) {
return true;
} else {
return false;
}
}
template <>
uint32_t HwHelperHw<Family>::computeSlmValues(const HardwareInfo &hwInfo, uint32_t slmSize) {
using SHARED_LOCAL_MEMORY_SIZE = typename Family::INTERFACE_DESCRIPTOR_DATA::SHARED_LOCAL_MEMORY_SIZE;
auto slmValue = std::max(slmSize, 1024u);
slmValue = Math::nextPowerOfTwo(slmValue);
slmValue = Math::getMinLsbSet(slmValue);
slmValue = slmValue - 9;
DEBUG_BREAK_IF(slmValue > 7);
slmValue *= !!slmSize;
return slmValue;
}
template class HwHelperHw<Family>;
template class FlatBatchBufferHelperHw<Family>;
template struct MemorySynchronizationCommands<Family>;
template struct LriHelper<Family>;
} // namespace NEO

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#ifdef SUPPORT_DG2
#include "hw_info_dg2.h"
#endif

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/aub_mem_dump/definitions/aub_services.h"
#include "shared/source/debug_settings/debug_settings_manager.h"
#include "shared/source/helpers/constants.h"
#include "shared/source/xe_hpg_core/hw_cmds.h"
#include "engine_node.h"
namespace NEO {
const char *HwMapper<IGFX_DG2>::abbreviation = "dg2";
bool isSimulationDG2(unsigned short deviceId) {
return false;
};
const PLATFORM DG2::platform = {
IGFX_DG2,
PCH_UNKNOWN,
IGFX_XE_HPG_CORE,
IGFX_XE_HPG_CORE,
PLATFORM_NONE, // default init
0, // usDeviceID
0, // usRevId. 0 sets the stepping to A0
0, // usDeviceID_PCH
0, // usRevId_PCH
GTTYPE_UNDEFINED};
const RuntimeCapabilityTable DG2::capabilityTable{
EngineDirectSubmissionInitVec{
{aub_stream::ENGINE_RCS, {true, false, false, true}},
{aub_stream::ENGINE_CCS, {true, false, false, true}},
{aub_stream::ENGINE_CCS1, {true, false, true, true}},
{aub_stream::ENGINE_CCS2, {true, false, true, true}},
{aub_stream::ENGINE_CCS3, {true, false, true, true}}}, // directSubmissionEngines
{0, 0, 0, false, false, false}, // kmdNotifyProperties
MemoryConstants::max48BitAddress, // gpuAddressSpace
0, // sharedSystemMemCapabilities
83.333, // defaultProfilingTimerResolution
MemoryConstants::pageSize, // requiredPreemptionSurfaceSize
&isSimulationDG2, // isSimulation
PreemptionMode::ThreadGroup, // defaultPreemptionMode
aub_stream::ENGINE_CCS, // defaultEngineType
0, // maxRenderFrequency
30, // clVersionSupport
CmdServicesMemTraceVersion::DeviceValues::Dg2, // aubDeviceId
0, // extraQuantityThreadsPerEU
64, // slmSize
sizeof(DG2::GRF), // grfSize
36u, // timestampValidBits
32u, // kernelTimestampValidBits
false, // blitterOperationsSupported
true, // ftrSupportsInteger64BitAtomics
false, // ftrSupportsFP64
true, // ftrSupports64BitMath
true, // ftrSvm
false, // ftrSupportsCoherency
false, // ftrSupportsVmeAvcTextureSampler
false, // ftrSupportsVmeAvcPreemption
false, // ftrRenderCompressedBuffers
false, // ftrRenderCompressedImages
true, // ftr64KBpages
true, // instrumentationEnabled
"dg2", // platformType
"", // deviceName
true, // sourceLevelDebuggerSupported
false, // supportsVme
true, // supportCacheFlushAfterWalker
true, // supportsImages
false, // supportsDeviceEnqueue
false, // supportsPipes
true, // supportsOcl21Features
false, // supportsOnDemandPageFaults
false, // supportsIndependentForwardProgress
false, // hostPtrTrackingEnabled
true, // levelZeroSupported
false, // isIntegratedDevice
true, // supportsMediaBlock
true // fusedEuEnabled
};
WorkaroundTable DG2::workaroundTable = {};
FeatureTable DG2::featureTable = {};
void DG2::setupFeatureAndWorkaroundTable(HardwareInfo *hwInfo) {
FeatureTable *featureTable = &hwInfo->featureTable;
WorkaroundTable *workaroundTable = &hwInfo->workaroundTable;
featureTable->ftrL3IACoherency = true;
featureTable->ftrFlatPhysCCS = true;
featureTable->ftrPPGTT = true;
featureTable->ftrSVM = true;
featureTable->ftrIA32eGfxPTEs = true;
featureTable->ftrStandardMipTailFormat = true;
featureTable->ftrTranslationTable = true;
featureTable->ftrUserModeTranslationTable = true;
featureTable->ftrTileMappedResource = true;
featureTable->ftrEnableGuC = true;
featureTable->ftrFbc = true;
featureTable->ftrFbc2AddressTranslation = true;
featureTable->ftrFbcBlitterTracking = true;
featureTable->ftrAstcHdr2D = true;
featureTable->ftrAstcLdr2D = true;
featureTable->ftr3dMidBatchPreempt = true;
featureTable->ftrGpGpuMidBatchPreempt = true;
featureTable->ftrGpGpuThreadGroupLevelPreempt = true;
featureTable->ftrPerCtxtPreemptionGranularityControl = true;
featureTable->ftrTileY = false;
featureTable->ftrLocalMemory = true;
featureTable->ftrLinearCCS = true;
featureTable->ftrE2ECompression = true;
featureTable->ftrCCSNode = true;
featureTable->ftrCCSRing = true;
featureTable->ftrCCSMultiInstance = true;
featureTable->ftrUnified3DMediaCompressionFormats = true;
workaroundTable->wa4kAlignUVOffsetNV12LinearSurface = true;
workaroundTable->waEnablePreemptionGranularityControlByUMD = true;
};
const HardwareInfo DG2_CONFIG::hwInfo = {
&DG2::platform,
&DG2::featureTable,
&DG2::workaroundTable,
&DG2_CONFIG::gtSystemInfo,
DG2::capabilityTable,
};
GT_SYSTEM_INFO DG2_CONFIG::gtSystemInfo = {0};
void DG2_CONFIG::setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable) {
DG2_CONFIG::setupHardwareInfoMultiTile(hwInfo, setupFeatureTableAndWorkaroundTable, false);
}
void DG2_CONFIG::setupHardwareInfoMultiTile(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, bool setupMultiTile) {
GT_SYSTEM_INFO *gtSysInfo = &hwInfo->gtSystemInfo;
gtSysInfo->CsrSizeInMb = 8;
gtSysInfo->IsL3HashModeEnabled = false;
gtSysInfo->IsDynamicallyPopulated = false;
if (setupFeatureTableAndWorkaroundTable) {
DG2::setupFeatureAndWorkaroundTable(hwInfo);
}
};
#include "hw_info_setup_dg2.inl"
} // namespace NEO

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "shared/source/xe_hpg_core/hw_info_xe_hpg_core.h"
namespace NEO {
struct DG2;
template <>
struct HwMapper<IGFX_DG2> {
enum { gfxFamily = IGFX_XE_HPG_CORE };
static const char *abbreviation;
typedef GfxFamilyMapper<static_cast<GFXCORE_FAMILY>(gfxFamily)>::GfxFamily GfxFamily;
typedef DG2 GfxProduct;
};
} // namespace NEO

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/xe_hpg_core/hw_info_xe_hpg_core.h"
namespace NEO {
const char *GfxFamilyMapper<IGFX_XE_HPG_CORE>::name = "XE_HPG_CORE";
} // namespace NEO

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "shared/source/helpers/hw_info.h"
namespace NEO {
struct XE_HPG_COREFamily;
template <>
struct GfxFamilyMapper<IGFX_XE_HPG_CORE> {
typedef XE_HPG_COREFamily GfxFamily;
static const char *name;
};
} // namespace NEO

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shared/source/xe_hpg_core/image_core_xe_hpg_core.cpp Normal file
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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/image/image_surface_state.h"
#include "shared/source/xe_hpg_core/hw_cmds_base.h"
namespace NEO {
using Family = XE_HPG_COREFamily;
template <>
void setFilterMode<Family>(Family::RENDER_SURFACE_STATE *surfaceState, const HardwareInfo *hwInfo) {
surfaceState->setDisallowLowQualityFlitering(false);
}
// clang-format off
#include "shared/source/image/image_skl_and_later.inl"
// clang-format on
} // namespace NEO

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/command_container/implicit_scaling.h"
#include "shared/source/command_container/implicit_scaling_xehp_and_later.inl"
namespace NEO {
using Family = XE_HPG_COREFamily;
template <>
bool ImplicitScalingDispatch<Family>::pipeControlStallRequired = true;
template struct ImplicitScalingDispatch<Family>;
} // namespace NEO

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/command_stream/command_stream_receiver_with_aub_dump.inl"
#include "shared/source/os_interface/linux/device_command_stream.inl"
#include "shared/source/os_interface/linux/drm_command_stream.inl"
#include "shared/source/os_interface/linux/drm_command_stream_xehp_and_later.inl"
namespace NEO {
template class DeviceCommandStreamReceiver<XE_HPG_COREFamily>;
template class DrmCommandStreamReceiver<XE_HPG_COREFamily>;
template class CommandStreamReceiverWithAUBDump<DrmCommandStreamReceiver<XE_HPG_COREFamily>>;
} // namespace NEO

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/direct_submission/direct_submission_hw.inl"
#include "shared/source/direct_submission/direct_submission_prefetch_mitigation_xe_hp_core_and_later.inl"
#include "shared/source/direct_submission/direct_submission_prefetcher_xe_hp_core_and_later.inl"
#include "shared/source/direct_submission/direct_submission_xe_hp_core_and_later.inl"
#include "shared/source/direct_submission/dispatchers/blitter_dispatcher.inl"
#include "shared/source/direct_submission/dispatchers/dispatcher.inl"
#include "shared/source/direct_submission/dispatchers/render_dispatcher.inl"
#include "shared/source/direct_submission/linux/drm_direct_submission.inl"
#include "hw_cmds.h"
namespace NEO {
using GfxFamily = XE_HPG_COREFamily;
template class Dispatcher<GfxFamily>;
template class BlitterDispatcher<GfxFamily>;
template class RenderDispatcher<GfxFamily>;
template class DirectSubmissionHw<GfxFamily, BlitterDispatcher<GfxFamily>>;
template class DirectSubmissionHw<GfxFamily, RenderDispatcher<GfxFamily>>;
template class DrmDirectSubmission<GfxFamily, BlitterDispatcher<GfxFamily>>;
template class DrmDirectSubmission<GfxFamily, RenderDispatcher<GfxFamily>>;
} // namespace NEO

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/command_stream/stream_properties.h"
#include "shared/source/debug_settings/debug_settings_manager.h"
#include "shared/source/helpers/hw_info.h"
#include "shared/source/kernel/kernel_properties.h"
#include "shared/source/os_interface/hw_info_config.h"
#include "shared/source/os_interface/hw_info_config.inl"
#include "shared/source/os_interface/hw_info_config_dg2_and_later.inl"
#include "shared/source/os_interface/hw_info_config_xehp_and_later.inl"
namespace NEO {
constexpr static auto gfxProduct = IGFX_DG2;
#include "shared/source/xe_hpg_core/os_agnostic_hw_info_config_dg2.inl"
#include "shared/source/xe_hpg_core/os_agnostic_hw_info_config_xe_hpg_core.inl"
template <>
int HwInfoConfigHw<gfxProduct>::configureHardwareCustom(HardwareInfo *hwInfo, OSInterface *osIface) {
if (allowRenderCompression(*hwInfo)) {
enableRenderCompression(hwInfo);
}
enableBlitterOperationsSupport(hwInfo);
auto &kmdNotifyProperties = hwInfo->capabilityTable.kmdNotifyProperties;
kmdNotifyProperties.enableKmdNotify = true;
kmdNotifyProperties.delayKmdNotifyMicroseconds = 20;
return 0;
}
template class HwInfoConfigHw<gfxProduct>;
} // namespace NEO

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
template <>
void HwInfoConfigHw<gfxProduct>::adjustSamplerState(void *sampler, const HardwareInfo &hwInfo) {
using SAMPLER_STATE = typename XE_HPG_COREFamily::SAMPLER_STATE;
auto samplerState = reinterpret_cast<SAMPLER_STATE *>(sampler);
if (DebugManager.flags.ForceSamplerLowFilteringPrecision.get()) {
samplerState->setLowQualityFilter(SAMPLER_STATE::LOW_QUALITY_FILTER_ENABLE);
}
HwHelper &hwHelper = HwHelper::get(hwInfo.platform.eRenderCoreFamily);
auto isMirrorAddressMode = SAMPLER_STATE::TEXTURE_COORDINATE_MODE_MIRROR == samplerState->getTcxAddressControlMode();
auto isNearestFilter = SAMPLER_STATE::MIN_MODE_FILTER_NEAREST == samplerState->getMinModeFilter();
if (isNearestFilter && isMirrorAddressMode && hwHelper.isWorkaroundRequired(REVISION_A0, REVISION_C, hwInfo)) {
samplerState->setRAddressMinFilterRoundingEnable(true);
samplerState->setRAddressMagFilterRoundingEnable(true);
}
}
template <>
uint32_t HwInfoConfigHw<gfxProduct>::getHwRevIdFromStepping(uint32_t stepping, const HardwareInfo &hwInfo) const {
switch (stepping) {
case REVISION_A0:
return 0x0;
case REVISION_A1:
return 0x1;
case REVISION_B:
return 0x4;
case REVISION_C:
return 0x8;
}
return CommonConstants::invalidStepping;
}
template <>
uint32_t HwInfoConfigHw<gfxProduct>::getSteppingFromHwRevId(const HardwareInfo &hwInfo) const {
switch (hwInfo.platform.usRevId) {
case 0x0:
return REVISION_A0;
case 0x1:
return REVISION_A1;
case 0x4:
return REVISION_B;
case 0x8:
return REVISION_C;
}
return CommonConstants::invalidStepping;
}
template <>
bool HwInfoConfigHw<gfxProduct>::isAdditionalStateBaseAddressWARequired(const HardwareInfo &hwInfo) const {
uint32_t stepping = getSteppingFromHwRevId(hwInfo);
if (stepping <= REVISION_B) {
return true;
} else {
return false;
}
}
template <>
bool HwInfoConfigHw<gfxProduct>::isMaxThreadsForWorkgroupWARequired(const HardwareInfo &hwInfo) const {
uint32_t stepping = getSteppingFromHwRevId(hwInfo);
return REVISION_A0 == stepping;
}
template <>
void HwInfoConfigHw<gfxProduct>::setForceNonCoherent(void *const statePtr, const StateComputeModeProperties &properties) {
using STATE_COMPUTE_MODE = typename XE_HPG_COREFamily::STATE_COMPUTE_MODE;
using FORCE_NON_COHERENT = typename STATE_COMPUTE_MODE::FORCE_NON_COHERENT;
if (properties.isCoherencyRequired.isDirty) {
STATE_COMPUTE_MODE &stateComputeMode = *static_cast<STATE_COMPUTE_MODE *>(statePtr);
FORCE_NON_COHERENT coherencyValue = !properties.isCoherencyRequired.value ? FORCE_NON_COHERENT::FORCE_NON_COHERENT_FORCE_GPU_NON_COHERENT
: FORCE_NON_COHERENT::FORCE_NON_COHERENT_FORCE_DISABLED;
stateComputeMode.setForceNonCoherent(coherencyValue);
auto mask = stateComputeMode.getMaskBits();
mask |= XE_HPG_COREFamily::stateComputeModeForceNonCoherentMask;
stateComputeMode.setMaskBits(mask);
}
}
template <>
bool HwInfoConfigHw<gfxProduct>::isDefaultEngineTypeAdjustmentRequired(const HardwareInfo &hwInfo) const {
return HwHelper::get(hwInfo.platform.eRenderCoreFamily).isWorkaroundRequired(REVISION_A0, REVISION_B, hwInfo);
}
template <>
bool HwInfoConfigHw<gfxProduct>::isDisableOverdispatchAvailable(const HardwareInfo &hwInfo) const {
return getSteppingFromHwRevId(hwInfo) >= REVISION_B;
}
template <>
bool HwInfoConfigHw<gfxProduct>::allowRenderCompression(const HardwareInfo &hwInfo) const {
if (HwHelper::get(hwInfo.platform.eRenderCoreFamily).isWorkaroundRequired(REVISION_A0, REVISION_A1, hwInfo) &&
(hwInfo.gtSystemInfo.EUCount != 128)) {
return false;
}
return true;
}
template <>
LocalMemoryAccessMode HwInfoConfigHw<gfxProduct>::getDefaultLocalMemoryAccessMode(const HardwareInfo &hwInfo) const {
if (HwHelper::get(hwInfo.platform.eRenderCoreFamily).isWorkaroundRequired(REVISION_A0, REVISION_B, hwInfo)) {
return LocalMemoryAccessMode::CpuAccessDisallowed;
}
return LocalMemoryAccessMode::Default;
}
template <>
bool HwInfoConfigHw<gfxProduct>::isAllocationSizeAdjustmentRequired(const HardwareInfo &hwInfo) const {
return HwHelper::get(hwInfo.platform.eRenderCoreFamily).isWorkaroundRequired(REVISION_A0, REVISION_B, hwInfo);
}
template <>
bool HwInfoConfigHw<gfxProduct>::isPrefetchDisablingRequired(const HardwareInfo &hwInfo) const {
return HwHelper::get(hwInfo.platform.eRenderCoreFamily).isWorkaroundRequired(REVISION_A0, REVISION_B, hwInfo);
}
template <>
bool HwInfoConfigHw<gfxProduct>::isPipeControlPriorToNonPipelinedStateCommandsWARequired(const HardwareInfo &hwInfo, bool isRcs) const {
bool required = hwInfo.gtSystemInfo.CCSInfo.NumberOfCCSEnabled > 1 && !isRcs;
if (DebugManager.flags.ProgramPipeControlPriorToNonPipelinedStateCommand.get() != -1) {
required = DebugManager.flags.ProgramPipeControlPriorToNonPipelinedStateCommand.get();
}
return required;
}
template <>
bool HwInfoConfigHw<gfxProduct>::isBlitterForImagesSupported() const {
return true;
}
template <>
bool HwInfoConfigHw<gfxProduct>::isTile64With3DSurfaceOnBCSSupported(const HardwareInfo &hwInfo) const {
return getSteppingFromHwRevId(hwInfo) >= REVISION_C;
}

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
template <>
void HwInfoConfigHw<gfxProduct>::getKernelExtendedProperties(uint32_t *fp16, uint32_t *fp32, uint32_t *fp64) {
*fp16 = 0u;
*fp32 = FP_ATOMIC_EXT_FLAG_GLOBAL_ADD;
*fp64 = 0u;
}

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shared/source/xe_hpg_core/preamble_xe_hpg_core.cpp Normal file
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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
namespace NEO {
struct XE_HPG_COREFamily;
using Family = XE_HPG_COREFamily;
} // namespace NEO
#include "shared/source/helpers/preamble_xehp_and_later.inl"
namespace NEO {
template <>
void PreambleHelper<Family>::appendProgramVFEState(const HardwareInfo &hwInfo, const StreamProperties &streamProperties, void *cmd) {
auto command = static_cast<typename Family::CFE_STATE *>(cmd);
command->setComputeOverdispatchDisable(streamProperties.frontEndState.disableOverdispatch.value == 1);
command->setSingleSliceDispatchCcsMode(streamProperties.frontEndState.singleSliceDispatchCcsMode.value == 1);
if (DebugManager.flags.CFEComputeOverdispatchDisable.get() != -1) {
command->setComputeOverdispatchDisable(DebugManager.flags.CFEComputeOverdispatchDisable.get());
}
if (DebugManager.flags.CFESingleSliceDispatchCCSMode.get() != -1) {
command->setSingleSliceDispatchCcsMode(DebugManager.flags.CFESingleSliceDispatchCCSMode.get());
}
}
template <>
bool PreambleHelper<Family>::isSystolicModeConfigurable(const HardwareInfo &hwInfo) {
return true;
}
template <>
bool PreambleHelper<Family>::isSpecialPipelineSelectModeChanged(bool lastSpecialPipelineSelectMode, bool newSpecialPipelineSelectMode,
const HardwareInfo &hwInfo) {
return lastSpecialPipelineSelectMode != newSpecialPipelineSelectMode;
}
template struct PreambleHelper<Family>;
} // namespace NEO

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/command_stream/preemption.h"
#include "shared/source/command_stream/preemption.inl"
namespace NEO {
using GfxFamily = XE_HPG_COREFamily;
#include "shared/source/command_stream/preemption_xehp_and_later.inl"
template void PreemptionHelper::programCmdStream<GfxFamily>(LinearStream &cmdStream, PreemptionMode newPreemptionMode,
PreemptionMode oldPreemptionMode, GraphicsAllocation *preemptionCsr);
template size_t PreemptionHelper::getRequiredCmdStreamSize<GfxFamily>(PreemptionMode newPreemptionMode, PreemptionMode oldPreemptionMode);
template size_t PreemptionHelper::getPreemptionWaCsSize<GfxFamily>(const Device &device);
template void PreemptionHelper::applyPreemptionWaCmdsBegin<GfxFamily>(LinearStream *pCommandStream, const Device &device);
template void PreemptionHelper::applyPreemptionWaCmdsEnd<GfxFamily>(LinearStream *pCommandStream, const Device &device);
template void PreemptionHelper::programInterfaceDescriptorDataPreemption<GfxFamily>(INTERFACE_DESCRIPTOR_DATA<GfxFamily> *idd, PreemptionMode preemptionMode);
} // namespace NEO

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shared/source/xe_hpg_core/state_base_address_xe_hpg_core.cpp Normal file
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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/helpers/state_base_address_xehp_and_later.inl"
namespace NEO {
template <>
void StateBaseAddressHelper<XE_HPG_COREFamily>::appendExtraCacheSettings(STATE_BASE_ADDRESS *stateBaseAddress, GmmHelper *gmmHelper) {
stateBaseAddress->setL1CachePolicyL1CacheControl(STATE_BASE_ADDRESS::L1_CACHE_POLICY_WBP);
if (DebugManager.flags.ForceStatelessL1CachingPolicy.get() != -1) {
stateBaseAddress->setL1CachePolicyL1CacheControl(static_cast<typename STATE_BASE_ADDRESS::L1_CACHE_POLICY>(DebugManager.flags.ForceStatelessL1CachingPolicy.get()));
}
}
template struct StateBaseAddressHelper<XE_HPG_COREFamily>;
} // namespace NEO

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shared/source/xe_hpg_core/state_compute_mode_helper_xe_hpg_core.cpp Normal file
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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/helpers/state_compute_mode_helper.h"
namespace NEO {
template <>
bool StateComputeModeHelper<XE_HPG_COREFamily>::isStateComputeModeRequired(const CsrSizeRequestFlags &csrSizeRequestFlags, bool isThreadArbitionPolicyProgrammed) {
return csrSizeRequestFlags.coherencyRequestChanged || csrSizeRequestFlags.numGrfRequiredChanged;
}
} // namespace NEO

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/command_stream/command_stream_receiver_with_aub_dump.inl"
#include "shared/source/command_stream/tbx_command_stream_receiver_hw.h"
#include "shared/source/command_stream/tbx_command_stream_receiver_hw.inl"
#include "shared/source/helpers/array_count.h"
#include "shared/source/helpers/populate_factory.h"
#include "shared/source/memory_manager/memory_banks.h"
#include "shared/source/memory_manager/memory_pool.h"
#include "shared/source/xe_hpg_core/hw_cmds.h"
namespace NEO {
typedef XE_HPG_COREFamily Family;
static auto gfxCore = IGFX_XE_HPG_CORE;
template <>
void populateFactoryTable<TbxCommandStreamReceiverHw<Family>>() {
extern TbxCommandStreamReceiverCreateFunc tbxCommandStreamReceiverFactory[IGFX_MAX_CORE];
UNRECOVERABLE_IF(!isInRange(gfxCore, tbxCommandStreamReceiverFactory));
tbxCommandStreamReceiverFactory[gfxCore] = TbxCommandStreamReceiverHw<Family>::create;
}
#include "shared/source/command_stream/tbx_command_stream_receiver_xehp_and_later.inl"
template class TbxCommandStreamReceiverHw<Family>;
template class CommandStreamReceiverWithAUBDump<TbxCommandStreamReceiverHw<Family>>;
} // namespace NEO

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shared/source/xe_hpg_core/windows/command_stream_receiver_xe_hpg_core.cpp Normal file
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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/command_stream/command_stream_receiver_with_aub_dump.inl"
#include "shared/source/os_interface/windows/device_command_stream.inl"
#include "shared/source/os_interface/windows/wddm_device_command_stream.inl"
namespace NEO {
template class DeviceCommandStreamReceiver<XE_HPG_COREFamily>;
template class WddmCommandStreamReceiver<XE_HPG_COREFamily>;
template class CommandStreamReceiverWithAUBDump<WddmCommandStreamReceiver<XE_HPG_COREFamily>>;
} // namespace NEO

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/direct_submission/direct_submission_hw.inl"
#include "shared/source/direct_submission/direct_submission_prefetch_mitigation_xe_hp_core_and_later.inl"
#include "shared/source/direct_submission/direct_submission_prefetcher_xe_hp_core_and_later.inl"
#include "shared/source/direct_submission/direct_submission_xe_hp_core_and_later.inl"
#include "shared/source/direct_submission/dispatchers/blitter_dispatcher.inl"
#include "shared/source/direct_submission/dispatchers/dispatcher.inl"
#include "shared/source/direct_submission/dispatchers/render_dispatcher.inl"
#include "shared/source/direct_submission/windows/wddm_direct_submission.inl"
#include "hw_cmds.h"
namespace NEO {
using GfxFamily = XE_HPG_COREFamily;
template class Dispatcher<GfxFamily>;
template class BlitterDispatcher<GfxFamily>;
template class RenderDispatcher<GfxFamily>;
template class DirectSubmissionHw<GfxFamily, BlitterDispatcher<GfxFamily>>;
template class DirectSubmissionHw<GfxFamily, RenderDispatcher<GfxFamily>>;
template class WddmDirectSubmission<GfxFamily, BlitterDispatcher<GfxFamily>>;
template class WddmDirectSubmission<GfxFamily, RenderDispatcher<GfxFamily>>;
} // namespace NEO

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shared/source/xe_hpg_core/windows/gmm_callbacks_xe_hpg_core.cpp Normal file
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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/helpers/windows/gmm_callbacks_tgllp_and_later.inl"
#include "shared/source/xe_hpg_core/hw_cmds.h"
namespace NEO {
template struct DeviceCallbacks<XE_HPG_COREFamily>;
template struct TTCallbacks<XE_HPG_COREFamily>;
} // namespace NEO

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/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/command_stream/stream_properties.h"
#include "shared/source/debug_settings/debug_settings_manager.h"
#include "shared/source/helpers/hw_info.h"
#include "shared/source/kernel/kernel_properties.h"
#include "shared/source/os_interface/hw_info_config.h"
#include "shared/source/os_interface/hw_info_config.inl"
#include "shared/source/os_interface/hw_info_config_dg2_and_later.inl"
#include "shared/source/os_interface/hw_info_config_xehp_and_later.inl"
namespace NEO {
constexpr static auto gfxProduct = IGFX_DG2;
#include "shared/source/xe_hpg_core/os_agnostic_hw_info_config_dg2.inl"
#include "shared/source/xe_hpg_core/os_agnostic_hw_info_config_xe_hpg_core.inl"
template <>
int HwInfoConfigHw<gfxProduct>::configureHardwareCustom(HardwareInfo *hwInfo, OSInterface *osIface) {
if (allowRenderCompression(*hwInfo)) {
enableRenderCompression(hwInfo);
}
enableBlitterOperationsSupport(hwInfo);
return 0;
}
template <>
void HwInfoConfigHw<gfxProduct>::convertTimestampsFromOaToCsDomain(uint64_t &timestampData) {
timestampData >>= 1;
}
template class HwInfoConfigHw<gfxProduct>;
} // namespace NEO