Add L3_CONTROL cmd format for Gen12LP
Change-Id: Ibae6c3f10a54accb333aa1b21163024aac8cf93c Signed-off-by: Raiyan Latif <raiyan.latif@intel.com>
This commit is contained in:
Raiyan Latif
sys_ocldev
parent
90e858e5bd
commit
921e30802a
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@ -223,6 +223,8 @@ const Family::GPGPU_CSR_BASE_ADDRESS Family::cmdInitGpgpuCsrBaseAddress = Family
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const Family::STATE_SIP Family::cmdInitStateSip = Family::STATE_SIP::sInit();
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const Family::BINDING_TABLE_STATE Family::cmdInitBindingTableState = Family::BINDING_TABLE_STATE::sInit();
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const Family::MI_USER_INTERRUPT Family::cmdInitUserInterrupt = Family::MI_USER_INTERRUPT::sInit();
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const Family::L3_CONTROL Family::cmdInitL3ControlWithoutPostSync = Family::L3_CONTROL::sInit();
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const Family::L3_CONTROL Family::cmdInitL3ControlWithPostSync = Family::L3_CONTROL::sInit();
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const Family::XY_COPY_BLT Family::cmdInitXyCopyBlt = Family::XY_COPY_BLT::sInit();
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const Family::MI_FLUSH_DW Family::cmdInitMiFlushDw = Family::MI_FLUSH_DW::sInit();
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const Family::XY_FAST_COLOR_BLT Family::cmdInitXyColorBlt = Family::XY_FAST_COLOR_BLT::sInit();
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@ -84,6 +84,8 @@ struct TGLLPFamily : public GEN12LP {
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static const STATE_SIP cmdInitStateSip;
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static const BINDING_TABLE_STATE cmdInitBindingTableState;
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static const MI_USER_INTERRUPT cmdInitUserInterrupt;
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static const L3_CONTROL cmdInitL3ControlWithoutPostSync;
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static const L3_CONTROL cmdInitL3ControlWithPostSync;
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static const XY_COPY_BLT cmdInitXyCopyBlt;
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static const MI_FLUSH_DW cmdInitMiFlushDw;
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static const XY_FAST_COLOR_BLT cmdInitXyColorBlt;
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@ -5223,6 +5223,357 @@ typedef struct tagGPGPU_CSR_BASE_ADDRESS {
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} GPGPU_CSR_BASE_ADDRESS;
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STATIC_ASSERT(12 == sizeof(GPGPU_CSR_BASE_ADDRESS));
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typedef struct tagL3_FLUSH_ADDRESS_RANGE {
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union tagTheStructure {
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struct tagCommon {
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uint64_t Reserved_0 : BITFIELD_RANGE(0, 2);
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uint64_t AddressMask : BITFIELD_RANGE(3, 8);
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uint64_t Reserved_9 : BITFIELD_RANGE(9, 11);
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uint64_t AddressLow : BITFIELD_RANGE(12, 31);
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uint64_t AddressHigh : BITFIELD_RANGE(32, 47);
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uint64_t Reserved_48 : BITFIELD_RANGE(48, 59);
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uint64_t L3FlushEvictionPolicy : BITFIELD_RANGE(60, 61);
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uint64_t Reserved_62 : BITFIELD_RANGE(62, 63);
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} Common;
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struct tagCommonA0Stepping {
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uint64_t AddressHigh : BITFIELD_RANGE(0, 15);
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uint64_t Reserved_0 : BITFIELD_RANGE(16, 27);
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uint64_t L3FlushEvictionPolicy : BITFIELD_RANGE(28, 29);
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uint64_t Reserved_9 : BITFIELD_RANGE(30, 34);
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uint64_t AddressMask : BITFIELD_RANGE(35, 40);
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uint64_t Reserved_48 : BITFIELD_RANGE(41, 43);
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uint64_t AddressLow : BITFIELD_RANGE(44, 63);
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} CommonA0Stepping;
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uint32_t RawData[2];
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} TheStructure;
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typedef enum tagL3_FLUSH_EVICTION_POLICY {
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L3_FLUSH_EVICTION_POLICY_FLUSH_L3_WITH_EVICTION = 0x0,
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} L3_FLUSH_EVICTION_POLICY;
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inline void init() {
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memset(&TheStructure, 0, sizeof(TheStructure));
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}
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static tagL3_FLUSH_ADDRESS_RANGE sInit() {
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L3_FLUSH_ADDRESS_RANGE state;
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state.init();
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return state;
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}
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inline uint32_t &getRawData(const uint32_t index) {
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UNRECOVERABLE_IF(index >= 2);
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return TheStructure.RawData[index];
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}
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typedef enum tagADDRESSLOW {
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ADDRESSLOW_BIT_SHIFT = 0xC,
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ADDRESSLOW_ALIGN_SIZE = 0x1000,
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} ADDRESSLOW;
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inline void setAddressLow(const uint64_t value, bool isA0Stepping) {
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if (isA0Stepping) {
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TheStructure.CommonA0Stepping.AddressLow = value >> ADDRESSLOW_BIT_SHIFT;
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} else {
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TheStructure.Common.AddressLow = value >> ADDRESSLOW_BIT_SHIFT;
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}
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}
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inline uint64_t getAddressLow(bool isA0Stepping) const {
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if (isA0Stepping) {
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return (TheStructure.CommonA0Stepping.AddressLow << ADDRESSLOW_BIT_SHIFT) & uint64_t(0xffffffff);
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} else {
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return (TheStructure.Common.AddressLow << ADDRESSLOW_BIT_SHIFT);
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}
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}
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inline void setAddressHigh(const uint64_t value, bool isA0Stepping) {
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if (isA0Stepping) {
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TheStructure.CommonA0Stepping.AddressHigh = value;
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} else {
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TheStructure.Common.AddressHigh = value;
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}
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}
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inline uint64_t getAddressHigh(bool isA0Stepping) const {
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if (isA0Stepping) {
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return (TheStructure.CommonA0Stepping.AddressHigh);
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} else {
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return (TheStructure.Common.AddressHigh);
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}
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}
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inline void setAddress(const uint64_t value, bool isA0Stepping) {
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setAddressLow(static_cast<uint32_t>(value), isA0Stepping);
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setAddressHigh(static_cast<uint32_t>(value >> 32), isA0Stepping);
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}
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inline uint64_t getAddress(bool isA0Stepping) const {
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return static_cast<uint64_t>(getAddressLow(isA0Stepping)) | (static_cast<uint64_t>(getAddressHigh(isA0Stepping)) << 32);
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}
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inline void setL3FlushEvictionPolicy(const L3_FLUSH_EVICTION_POLICY value, bool isA0Stepping) {
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if (isA0Stepping) {
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TheStructure.CommonA0Stepping.L3FlushEvictionPolicy = value;
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} else {
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TheStructure.Common.L3FlushEvictionPolicy = value;
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}
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}
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inline L3_FLUSH_EVICTION_POLICY getL3FlushEvictionPolicy(bool isA0Stepping) const {
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if (isA0Stepping) {
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return static_cast<L3_FLUSH_EVICTION_POLICY>(TheStructure.CommonA0Stepping.L3FlushEvictionPolicy);
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} else {
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return static_cast<L3_FLUSH_EVICTION_POLICY>(TheStructure.Common.L3FlushEvictionPolicy);
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}
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}
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inline void setAddressMask(const uint64_t value, bool isA0Stepping) {
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if (isA0Stepping) {
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TheStructure.CommonA0Stepping.AddressMask = value;
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} else {
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UNRECOVERABLE_IF(value > 0x1f8);
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TheStructure.Common.AddressMask = value;
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}
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}
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inline uint32_t getAddressMask(bool isA0Stepping) const {
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if (isA0Stepping) {
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return TheStructure.CommonA0Stepping.AddressMask;
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} else {
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return TheStructure.Common.AddressMask;
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}
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}
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} L3_FLUSH_ADDRESS_RANGE;
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STATIC_ASSERT(8 == sizeof(L3_FLUSH_ADDRESS_RANGE));
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struct L3_CONTROL_BASE {
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union tagTheStructure {
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struct tagCommon {
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uint32_t Length : BITFIELD_RANGE(0, 7);
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uint32_t DepthCacheFlush : BITFIELD_RANGE(8, 8);
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uint32_t RenderTargetCacheFlushEnable : BITFIELD_RANGE(9, 9);
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uint32_t HdcPipelineFlush : BITFIELD_RANGE(10, 10);
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uint32_t Reserved_11 : BITFIELD_RANGE(11, 13);
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uint32_t PostSyncOperation : BITFIELD_RANGE(14, 14);
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uint32_t PostSyncOperationL3CacheabilityControl : BITFIELD_RANGE(15, 15); // removed on DG1
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uint32_t Reserved_16 : BITFIELD_RANGE(16, 19);
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uint32_t CommandStreamerStallEnable : BITFIELD_RANGE(20, 20);
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uint32_t DestinationAddressType : BITFIELD_RANGE(21, 21);
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uint32_t Reserved_22 : BITFIELD_RANGE(22, 22);
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uint32_t _3DCommandSubOpcode : BITFIELD_RANGE(23, 23);
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uint32_t _3DCommandOpcode : BITFIELD_RANGE(24, 26);
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uint32_t CommandSubtype : BITFIELD_RANGE(27, 28);
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uint32_t Type : BITFIELD_RANGE(29, 31);
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} Common;
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uint32_t RawData[1];
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} TheStructure;
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typedef enum tagLENGTH {
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LENGTH_POST_SYNC_OPERATION_DISABLED = 1,
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LENGTH_POST_SYNC_OPERATION_ENABLED = 5,
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} LENGTH;
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typedef enum tagPOST_SYNC_OPERATION {
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POST_SYNC_OPERATION_NO_WRITE = 0x0,
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POST_SYNC_OPERATION_WRITE_IMMEDIATE_DATA = 0x1,
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} POST_SYNC_OPERATION;
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typedef enum tagPOST_SYNC_OPERATION_L3_CACHEABILITY_CONTROL {
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POST_SYNC_OPERATION_L3_CACHEABILITY_CONTROL_DEFAULT_MOCS = 0x0,
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POST_SYNC_OPERATION_L3_CACHEABILITY_CONTROL_CACHEABLE_MOCS = 0x1,
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} POST_SYNC_OPERATION_L3_CACHEABILITY_CONTROL;
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typedef enum tagDESTINATION_ADDRESS_TYPE {
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DESTINATION_ADDRESS_TYPE_PPGTT = 0x0,
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DESTINATION_ADDRESS_TYPE_GGTT = 0x1,
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} DESTINATION_ADDRESS_TYPE;
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typedef enum tag_3D_COMMAND_SUB_OPCODE {
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_3D_COMMAND_SUB_OPCODE_L3_CONTROL = 0x1,
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} _3D_COMMAND_SUB_OPCODE;
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typedef enum tag_3D_COMMAND_OPCODE {
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_3D_COMMAND_OPCODE_L3_CONTROL = 0x5,
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} _3D_COMMAND_OPCODE;
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typedef enum tagCOMMAND_SUBTYPE {
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COMMAND_SUBTYPE_GFXPIPE_3D = 0x3,
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} COMMAND_SUBTYPE;
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typedef enum tagTYPE {
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TYPE_GFXPIPE = 0x3,
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} TYPE;
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inline void init(void) {
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memset(&TheStructure, 0, sizeof(TheStructure));
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TheStructure.Common.PostSyncOperation = POST_SYNC_OPERATION_NO_WRITE;
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TheStructure.Common.PostSyncOperationL3CacheabilityControl = POST_SYNC_OPERATION_L3_CACHEABILITY_CONTROL_DEFAULT_MOCS;
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TheStructure.Common.DestinationAddressType = DESTINATION_ADDRESS_TYPE_PPGTT;
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TheStructure.Common._3DCommandSubOpcode = _3D_COMMAND_SUB_OPCODE_L3_CONTROL;
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TheStructure.Common._3DCommandOpcode = _3D_COMMAND_OPCODE_L3_CONTROL;
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TheStructure.Common.CommandSubtype = COMMAND_SUBTYPE_GFXPIPE_3D;
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TheStructure.Common.Type = TYPE_GFXPIPE;
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}
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static L3_CONTROL_BASE sInit(void) {
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L3_CONTROL_BASE state;
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state.init();
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return state;
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}
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inline uint32_t &getRawData(const uint32_t index) {
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UNRECOVERABLE_IF(index >= 7);
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return TheStructure.RawData[index];
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}
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inline void setLength(const LENGTH value) {
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TheStructure.Common.Length = value;
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}
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inline LENGTH getLength(void) const {
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return (LENGTH)TheStructure.Common.Length;
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}
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inline void setDepthCacheFlush(const bool value) {
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TheStructure.Common.DepthCacheFlush = value;
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}
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inline bool getDepthCacheFlush(void) const {
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return TheStructure.Common.DepthCacheFlush;
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}
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inline void setRenderTargetCacheFlushEnable(const bool value) {
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TheStructure.Common.RenderTargetCacheFlushEnable = value;
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}
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inline bool getRenderTargetCacheFlushEnable(void) const {
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return TheStructure.Common.RenderTargetCacheFlushEnable;
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}
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inline void setHdcPipelineFlush(const bool value) {
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TheStructure.Common.HdcPipelineFlush = value;
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}
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inline bool getHdcPipelineFlush(void) const {
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return TheStructure.Common.HdcPipelineFlush;
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}
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inline void setPostSyncOperation(const POST_SYNC_OPERATION value) {
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TheStructure.Common.PostSyncOperation = value;
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}
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inline POST_SYNC_OPERATION getPostSyncOperation(void) const {
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return static_cast<POST_SYNC_OPERATION>(TheStructure.Common.PostSyncOperation);
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}
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inline void setPostSyncOperationL3CacheabilityControl(const POST_SYNC_OPERATION_L3_CACHEABILITY_CONTROL value) {
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TheStructure.Common.PostSyncOperationL3CacheabilityControl = value;
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}
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inline POST_SYNC_OPERATION_L3_CACHEABILITY_CONTROL getPostSyncOperationL3CacheabilityControl(void) const {
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return static_cast<POST_SYNC_OPERATION_L3_CACHEABILITY_CONTROL>(TheStructure.Common.PostSyncOperationL3CacheabilityControl);
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}
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inline void setCommandStreamerStallEnable(const bool value) {
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TheStructure.Common.CommandStreamerStallEnable = value;
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}
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inline bool getCommandStreamerStallEnable(void) const {
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return TheStructure.Common.CommandStreamerStallEnable;
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}
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inline void setDestinationAddressType(const DESTINATION_ADDRESS_TYPE value) {
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TheStructure.Common.DestinationAddressType = value;
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}
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inline DESTINATION_ADDRESS_TYPE getDestinationAddressType(void) const {
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return static_cast<DESTINATION_ADDRESS_TYPE>(TheStructure.Common.DestinationAddressType);
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}
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inline void setType(const TYPE value) {
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TheStructure.Common.Type = value;
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}
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inline TYPE getType(void) const {
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return static_cast<TYPE>(TheStructure.Common.Type);
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}
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};
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struct L3_CONTROL_POST_SYNC_DATA {
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union tagTheStructure {
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struct tagCommon {
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uint64_t Reserved_96 : BITFIELD_RANGE(0, 2);
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uint64_t Address : BITFIELD_RANGE(3, 47);
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uint64_t Reserved_144 : BITFIELD_RANGE(48, 63);
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uint64_t ImmediateData;
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} Common;
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uint32_t RawData[4];
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} TheStructure;
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inline void init(void) {
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memset(&TheStructure, 0, sizeof(TheStructure));
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}
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typedef enum tagADDRESS {
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ADDRESS_BIT_SHIFT = 0x3,
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ADDRESS_ALIGN_SIZE = 0x8,
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} ADDRESS;
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inline void setAddress(const uint64_t value) {
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UNRECOVERABLE_IF(value > 0xfffffffffff8L);
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TheStructure.Common.Address = value >> ADDRESS_BIT_SHIFT;
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}
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inline uint64_t getAddress(void) const {
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return TheStructure.Common.Address << ADDRESS_BIT_SHIFT;
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}
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inline void setImmediateData(const uint64_t value) {
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TheStructure.Common.ImmediateData = value;
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}
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inline uint64_t getImmediateData(void) const {
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return TheStructure.Common.ImmediateData;
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}
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};
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struct L3_CONTROL {
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union tagTheStructure {
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struct tagCommon {
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L3_CONTROL_BASE Base;
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L3_CONTROL_POST_SYNC_DATA PostSyncData;
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L3_FLUSH_ADDRESS_RANGE L3FlushAddressRange;
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} Common;
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uint32_t RawData[7];
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} TheStructure;
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inline void init(void) {
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memset(&TheStructure, 0, sizeof(TheStructure));
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getBase().init();
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getPostSyncData().init();
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getBase().setLength(L3_CONTROL_BASE::LENGTH_POST_SYNC_OPERATION_ENABLED);
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TheStructure.Common.L3FlushAddressRange.init();
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}
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inline void setL3FlushAddressRange(const L3_FLUSH_ADDRESS_RANGE &value) {
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TheStructure.Common.L3FlushAddressRange = value;
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}
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inline L3_FLUSH_ADDRESS_RANGE &getL3FlushAddressRange(void) {
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return TheStructure.Common.L3FlushAddressRange;
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}
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inline const L3_FLUSH_ADDRESS_RANGE &getL3FlushAddressRange(void) const {
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return TheStructure.Common.L3FlushAddressRange;
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}
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static L3_CONTROL sInit(void) {
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L3_CONTROL state;
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state.init();
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return state;
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}
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inline uint32_t &getRawData(const uint32_t index) {
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UNRECOVERABLE_IF(index >= 7);
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return TheStructure.RawData[index];
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}
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L3_CONTROL_BASE &getBase() {
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return TheStructure.Common.Base;
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}
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const L3_CONTROL_BASE &getBase() const {
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return TheStructure.Common.Base;
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}
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L3_CONTROL_POST_SYNC_DATA &getPostSyncData() {
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return TheStructure.Common.PostSyncData;
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}
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const L3_CONTROL_POST_SYNC_DATA &getPostSyncData() const {
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return TheStructure.Common.PostSyncData;
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}
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inline void setPostSyncAddress(const uint64_t value) {
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getPostSyncData().setAddress(value);
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}
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inline uint64_t getPostSyncAddress(void) const {
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return getPostSyncData().getAddress();
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}
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inline void setPostSyncImmediateData(const uint64_t value) {
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getPostSyncData().setImmediateData(value);
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}
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inline uint64_t getPostSyncImmediateData(void) const {
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return getPostSyncData().getImmediateData();
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}
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};
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STATIC_ASSERT(28 == sizeof(L3_CONTROL));
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STATIC_ASSERT(std::is_pod<L3_CONTROL>::value);
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typedef struct tagXY_BLOCK_COPY_BLT {
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union tagTheStructure {
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struct tagCommon {
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