I915_EXEC_DATA_PORT_COHERENT support
- new mechanism to switch coherency at exec level Change-Id: I3e9cca2141822828be7d44e858e8fe2c258efbfa
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26b0b9a873
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933312e098
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@ -132,7 +132,7 @@ bool BufferObject::setTiling(uint32_t mode, uint32_t stride) {
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void BufferObject::fillExecObject(drm_i915_gem_exec_object2 &execObject) {
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execObject.handle = this->handle;
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execObject.relocation_count = 0; //No relocations, we are SoftPinning
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execObject.relocation_count = 0; //No relocations, we are SoftPinning
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execObject.relocs_ptr = 0ul;
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execObject.alignment = 0;
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execObject.offset = this->isSoftpin ? this->offset64 : 0;
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@ -167,7 +167,9 @@ int BufferObject::exec(uint32_t used, size_t startOffset, unsigned int flags, bo
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execbuf.flags = flags;
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if (drm->peekCoherencyDisablePatchActive() && !requiresCoherency) {
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execbuf.flags = execbuf.flags | I915_PRIVATE_EXEC_FORCE_NON_COHERENT;
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execbuf.flags |= (uint64_t)I915_PRIVATE_EXEC_FORCE_NON_COHERENT;
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} else if (drm->peekDataPortCoherencyPatchActive() && requiresCoherency) {
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execbuf.flags |= (uint64_t)I915_EXEC_DATA_PORT_COHERENT;
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}
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if (lowPriority) {
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execbuf.rsvd1 = this->drm->lowPriorityContextId & I915_EXEC_CONTEXT_ID_MASK;
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@ -124,6 +124,12 @@ void Drm::obtainCoherencyDisablePatchActive() {
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coherencyDisablePatchActive = (ret == 0) && (value != 0);
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}
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void Drm::obtainDataPortCoherencyPatchActive() {
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int value = 0;
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auto ret = getParamIoctl(I915_PARAM_HAS_EXEC_DATA_PORT_COHERENCY, &value);
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dataPortCoherencyPatchActive = (ret == 0) && (value != 0);
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}
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std::string Drm::getSysFsPciPath(int deviceID) {
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std::string nullPath;
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std::string sysFsPciDirectory = Os::sysFsPciPath;
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@ -39,6 +39,9 @@ namespace OCLRT {
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#define I915_CONTEXT_PRIVATE_PARAM_BOOST 0x80000000
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#define I915_EXEC_DATA_PORT_COHERENT (1 << 20)
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#define I915_PARAM_HAS_EXEC_DATA_PORT_COHERENCY 52
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class DeviceFactory;
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struct HardwareInfo;
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@ -74,8 +77,10 @@ class Drm {
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bool is48BitAddressRangeSupported();
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MOCKABLE_VIRTUAL bool hasPreemption();
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bool setLowPriority();
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bool peekCoherencyDisablePatchActive() { return coherencyDisablePatchActive; }
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bool peekCoherencyDisablePatchActive() const { return coherencyDisablePatchActive; }
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bool peekDataPortCoherencyPatchActive() const { return dataPortCoherencyPatchActive; }
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virtual void obtainCoherencyDisablePatchActive();
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MOCKABLE_VIRTUAL void obtainDataPortCoherencyPatchActive();
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int getFileDescriptor() const { return fd; }
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bool contextCreate();
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void contextDestroy();
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@ -90,6 +95,7 @@ class Drm {
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int revisionId;
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GTTYPE eGtType;
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bool coherencyDisablePatchActive = false;
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bool dataPortCoherencyPatchActive = false;
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Drm(int fd) : lowPriorityContextId(0), fd(fd), deviceId(0), revisionId(0), eGtType(GTTYPE_UNDEFINED) {}
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virtual ~Drm();
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@ -131,6 +131,7 @@ int HwInfoConfig::configureHwInfo(const HardwareInfo *inHwInfo, HardwareInfo *ou
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pSysInfo->SubSliceCount = static_cast<uint32_t>(subSliceCount);
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drm->obtainCoherencyDisablePatchActive();
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drm->obtainDataPortCoherencyPatchActive();
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pSkuTable->ftrSVM = drm->is48BitAddressRangeSupported();
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int maxGpuFreq = 0;
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@ -81,6 +81,7 @@ class DrmMockCustom : public Drm {
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IoctlResExt(int32_t no, int32_t res) : no(no), res(res) {}
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};
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void overideCoherencyPatchActive(bool newCoherencyPatchActiveValue) { coherencyDisablePatchActive = newCoherencyPatchActiveValue; }
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void overideDataPortCoherencyPatchActive(bool newValue) { dataPortCoherencyPatchActive = newValue; }
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class Ioctls {
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public:
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@ -110,6 +110,36 @@ TEST_F(DrmBufferObjectTest, givenDrmWithCoherencyPatchActiveWhenExecIsCalledWith
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EXPECT_EQ(expectedFlag, currentFlag);
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}
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TEST_F(DrmBufferObjectTest, givenDrmWithDataPortCoherencyPatchActiveWhenExecWithCoherencyRequestCalledThenSetExecFlag) {
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mock->ioctl_expected.total = 1;
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mock->ioctl_res = 0;
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mock->overideDataPortCoherencyPatchActive(true);
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auto ret = bo->exec(0, 0, 0, true);
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EXPECT_EQ(mock->ioctl_res, ret);
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EXPECT_NE(0u, mock->execBuffer.flags & I915_EXEC_DATA_PORT_COHERENT);
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}
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TEST_F(DrmBufferObjectTest, givenDrmWithoutDataPortCoherencyPatchActiveWhenExecWithCoherencyRequestCalledThenDontSetExecFlag) {
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mock->ioctl_expected.total = 1;
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mock->ioctl_res = 0;
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mock->overideDataPortCoherencyPatchActive(false);
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auto ret = bo->exec(0, 0, 0, true);
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EXPECT_EQ(mock->ioctl_res, ret);
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EXPECT_EQ(0u, mock->execBuffer.flags & I915_EXEC_DATA_PORT_COHERENT);
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}
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TEST_F(DrmBufferObjectTest, givenDrmWithDataPortCoherencyPatchActiveWhenExecWithoutCoherencyRequestCalledThenDontSetExecFlag) {
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mock->ioctl_expected.total = 1;
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mock->ioctl_res = 0;
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mock->overideDataPortCoherencyPatchActive(true);
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auto ret = bo->exec(0, 0, 0, false);
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EXPECT_EQ(mock->ioctl_res, ret);
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EXPECT_EQ(0u, mock->execBuffer.flags & I915_EXEC_DATA_PORT_COHERENT);
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}
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TEST_F(DrmBufferObjectTest, exec_ioctlFailed) {
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mock->ioctl_expected.total = 1;
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mock->ioctl_res = -1;
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@ -26,6 +26,7 @@
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#include "unit_tests/os_interface/linux/drm_mock.h"
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#include "unit_tests/fixtures/memory_management_fixture.h"
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#include "gtest/gtest.h"
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#include "gmock/gmock.h"
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#include "runtime/os_interface/os_interface.h"
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#include <fstream>
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@ -180,6 +181,50 @@ TEST(DrmTest, GivenMockDrmWhenAskedFor48BitAddressCorrectValueReturned) {
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delete pDrm;
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}
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ACTION_P2(saveGetParamData, saveParamPtr, forceReturnValuePtr) {
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auto getParamArg = static_cast<drm_i915_getparam_t *>(arg1);
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*saveParamPtr = getParamArg->param;
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*getParamArg->value = forceReturnValuePtr;
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}
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struct DrmDataPortCoherencyTests : public ::testing::Test {
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struct MyMockDrm : public Drm2 {
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MyMockDrm() : Drm2(){};
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MOCK_METHOD2(ioctl, int(unsigned long request, void *arg));
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} drm;
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void setupExpectCall(int expectedRetVal, int expectedGetParamValue) {
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using namespace ::testing;
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auto saveAndReturnAction = DoAll(saveGetParamData(&receivedGetParamType, expectedGetParamValue),
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Return(expectedRetVal));
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EXPECT_CALL(drm, ioctl(DRM_IOCTL_I915_GETPARAM, _)).Times(1).WillOnce(saveAndReturnAction);
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}
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int receivedGetParamType = 0;
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};
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TEST_F(DrmDataPortCoherencyTests, givenDisabledPatchWhenAskedToObtainDataPortCoherencyPatchThenReturnFlase) {
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setupExpectCall(1, 0); // return error == 1, dont care about assigned feature value
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drm.obtainDataPortCoherencyPatchActive();
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EXPECT_EQ(receivedGetParamType, I915_PARAM_HAS_EXEC_DATA_PORT_COHERENCY);
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EXPECT_FALSE(drm.peekDataPortCoherencyPatchActive());
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}
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TEST_F(DrmDataPortCoherencyTests, givenEnabledPatchAndDisabledFeatureWhenAskedToObtainDataPortCoherencyPatchThenReturnFlase) {
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setupExpectCall(0, 0); // return success(0), set disabled feature (0)
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drm.obtainDataPortCoherencyPatchActive();
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EXPECT_EQ(receivedGetParamType, I915_PARAM_HAS_EXEC_DATA_PORT_COHERENCY);
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EXPECT_FALSE(drm.peekDataPortCoherencyPatchActive());
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}
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TEST_F(DrmDataPortCoherencyTests, givenEnabledPatchAndEnabledFeatureWhenAskedToObtainDataPortCoherencyPatchThenReturnTrue) {
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setupExpectCall(0, 1); // return success(0), set enabled feature (1)
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drm.obtainDataPortCoherencyPatchActive();
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EXPECT_EQ(receivedGetParamType, I915_PARAM_HAS_EXEC_DATA_PORT_COHERENCY);
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EXPECT_TRUE(drm.peekDataPortCoherencyPatchActive());
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}
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#if defined(I915_PARAM_HAS_PREEMPTION)
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TEST(DrmTest, GivenMockDrmWhenAskedForPreemptionCorrectValueReturned) {
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Drm2 *pDrm = new Drm2;
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@ -358,4 +358,14 @@ TEST_F(HwInfoConfigTestLinuxDummy, givenPointerToHwInfoWhenConfigureHwInfoCalled
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int ret = hwConfig.configureHwInfo(pInHwInfo, &outHwInfo, osInterface);
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EXPECT_EQ(0, ret);
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EXPECT_EQ(outHwInfo.pSysInfo->CsrSizeInMb * MemoryConstants::megaByte, outHwInfo.capabilityTable.requiredPreemptionSurfaceSize);
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}
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}
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TEST_F(HwInfoConfigTestLinuxDummy, whenAskedToConfigureHwInfoThenObtainDataPortCoherencyPatchStatus) {
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struct MyDrm : public Drm2 {
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void obtainDataPortCoherencyPatchActive() override { obtainDataPortCoherencyPatchActiveCalled = true; }
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bool obtainDataPortCoherencyPatchActiveCalled = false;
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} myDrm;
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osInterface->get()->setDrm(&myDrm);
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hwConfig.configureHwInfo(pInHwInfo, &outHwInfo, osInterface);
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EXPECT_TRUE(myDrm.obtainDataPortCoherencyPatchActiveCalled);
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}
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