diff --git a/level_zero/core/source/gfx_core_helpers/CMakeLists.txt b/level_zero/core/source/gfx_core_helpers/CMakeLists.txt
index 05b08aba8c..73748408b6 100644
--- a/level_zero/core/source/gfx_core_helpers/CMakeLists.txt
+++ b/level_zero/core/source/gfx_core_helpers/CMakeLists.txt
@@ -1,5 +1,5 @@
 #
-# Copyright (C) 2023 Intel Corporation
+# Copyright (C) 2023-2024 Intel Corporation
 #
 # SPDX-License-Identifier: MIT
 #
@@ -40,6 +40,13 @@ if(SUPPORT_GEN12LP OR SUPPORT_XE_HP_CORE OR SUPPORT_XE_HPG_CORE)
   )
 endif()
 
+if(SUPPORT_XE_HPC_CORE OR SUPPORT_XE_HPG_CORE)
+  target_sources(${L0_STATIC_LIB_NAME}
+                 PRIVATE
+                 ${CMAKE_CURRENT_SOURCE_DIR}/l0_gfx_core_helper_xe_hpg_and_xe_hpc.inl
+  )
+endif()
+
 if(SUPPORT_PVC_AND_LATER)
   target_sources(${L0_STATIC_LIB_NAME}
                  PRIVATE
@@ -53,3 +60,10 @@ if(SUPPORT_GEN9 OR SUPPORT_GEN11 OR SUPPORT_GEN12LP OR SUPPORT_XE_HPG_CORE OR SU
                  ${CMAKE_CURRENT_SOURCE_DIR}/l0_gfx_core_helper_skl_to_pvc.inl
   )
 endif()
+
+if(SUPPORT_XE_HP_CORE OR SUPPORT_XE_HPG_CORE OR SUPPORT_XE2_HPG_CORE)
+  target_sources(${L0_STATIC_LIB_NAME}
+                 PRIVATE
+                 ${CMAKE_CURRENT_SOURCE_DIR}/l0_gfx_core_helper_xe_hpg_to_xe2_hpg.inl
+  )
+endif()
diff --git a/level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_base.inl b/level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_base.inl
index 48bbbd3950..9e948f9144 100644
--- a/level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_base.inl
+++ b/level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_base.inl
@@ -40,11 +40,6 @@ bool L0GfxCoreHelperHw<Family>::multiTileCapablePlatform() const {
     return false;
 }
 
-template <typename Family>
-zet_debug_regset_type_intel_gpu_t L0GfxCoreHelperHw<Family>::getRegsetTypeForLargeGrfDetection() const {
-    return ZET_DEBUG_REGSET_TYPE_INVALID_INTEL_GPU;
-}
-
 template <typename Family>
 uint32_t L0GfxCoreHelperHw<Family>::getCmdListWaitOnMemoryDataSize() const {
     if constexpr (Family::isQwordInOrderCounter) {
diff --git a/level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_skl_to_tgllp.inl b/level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_skl_to_tgllp.inl
index 3df2dd0709..8a4c643fbd 100644
--- a/level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_skl_to_tgllp.inl
+++ b/level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_skl_to_tgllp.inl
@@ -74,4 +74,9 @@ ze_mutable_command_exp_flags_t L0GfxCoreHelperHw<Family>::getPlatformCmdListUpda
     return 0;
 }
 
+template <typename Family>
+zet_debug_regset_type_intel_gpu_t L0GfxCoreHelperHw<Family>::getRegsetTypeForLargeGrfDetection() const {
+    return ZET_DEBUG_REGSET_TYPE_INVALID_INTEL_GPU;
+}
+
 } // namespace L0
diff --git a/level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_xe_hpg_and_xe_hpc.inl b/level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_xe_hpg_and_xe_hpc.inl
new file mode 100644
index 0000000000..74e87edfb2
--- /dev/null
+++ b/level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_xe_hpg_and_xe_hpc.inl
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2024 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper.h"
+
+namespace L0 {
+
+template <typename Family>
+zet_debug_regset_type_intel_gpu_t L0GfxCoreHelperHw<Family>::getRegsetTypeForLargeGrfDetection() const {
+    return ZET_DEBUG_REGSET_TYPE_CR_INTEL_GPU;
+}
+
+} // namespace L0
diff --git a/level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_xe_hpg_to_xe2_hpg.inl b/level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_xe_hpg_to_xe2_hpg.inl
new file mode 100644
index 0000000000..d5ead0c3ff
--- /dev/null
+++ b/level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_xe_hpg_to_xe2_hpg.inl
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2024 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper.h"
+
+namespace L0 {
+
+template <typename Family>
+ze_rtas_format_exp_t L0GfxCoreHelperHw<Family>::getSupportedRTASFormat() const {
+    return static_cast<ze_rtas_format_exp_t>(RTASDeviceFormatInternal::version1);
+}
+
+} // namespace L0
diff --git a/level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_xehp_and_later.inl b/level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_xehp_and_later.inl
index 97c5536982..2bf968fd6b 100644
--- a/level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_xehp_and_later.inl
+++ b/level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_xehp_and_later.inl
@@ -67,11 +67,6 @@ NEO::HeapAddressModel L0GfxCoreHelperHw<Family>::getPlatformHeapAddressModel(con
     return NEO::HeapAddressModel::privateHeaps;
 }
 
-template <typename Family>
-ze_rtas_format_exp_t L0GfxCoreHelperHw<Family>::getSupportedRTASFormat() const {
-    return static_cast<ze_rtas_format_exp_t>(RTASDeviceFormatInternal::version1);
-}
-
 template <typename Family>
 bool L0GfxCoreHelperHw<Family>::platformSupportsPrimaryBatchBufferCmdList() const {
     return true;
diff --git a/level_zero/core/source/xe_hpc_core/l0_gfx_core_helper_xe_hpc_core.cpp b/level_zero/core/source/xe_hpc_core/l0_gfx_core_helper_xe_hpc_core.cpp
index 8b2b9c6b9a..6cd4aafa5a 100644
--- a/level_zero/core/source/xe_hpc_core/l0_gfx_core_helper_xe_hpc_core.cpp
+++ b/level_zero/core/source/xe_hpc_core/l0_gfx_core_helper_xe_hpc_core.cpp
@@ -10,6 +10,8 @@
 #include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_base.inl"
 #include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_pvc_and_later.inl"
 #include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_skl_to_pvc.inl"
+#include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_xe_hpg_and_xe_hpc.inl"
+#include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_xe_hpg_to_xe2_hpg.inl"
 #include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_xehp_and_later.inl"
 #include "level_zero/core/source/helpers/l0_populate_factory.h"
 
@@ -35,11 +37,6 @@ bool L0GfxCoreHelperHw<Family>::platformSupportsStateBaseAddressTracking(const N
     return true;
 }
 
-template <>
-zet_debug_regset_type_intel_gpu_t L0GfxCoreHelperHw<Family>::getRegsetTypeForLargeGrfDetection() const {
-    return ZET_DEBUG_REGSET_TYPE_CR_INTEL_GPU;
-}
-
 template class L0GfxCoreHelperHw<Family>;
 
 } // namespace L0
diff --git a/level_zero/core/source/xe_hpg_core/l0_gfx_core_helper_xe_hpg_core.cpp b/level_zero/core/source/xe_hpg_core/l0_gfx_core_helper_xe_hpg_core.cpp
index f5df9ecc54..7d6233b915 100644
--- a/level_zero/core/source/xe_hpg_core/l0_gfx_core_helper_xe_hpg_core.cpp
+++ b/level_zero/core/source/xe_hpg_core/l0_gfx_core_helper_xe_hpg_core.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2021-2023 Intel Corporation
+ * Copyright (C) 2021-2024 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
@@ -10,6 +10,8 @@
 #include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_base.inl"
 #include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_skl_to_pvc.inl"
 #include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_tgllp_to_dg2.inl"
+#include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_xe_hpg_and_xe_hpc.inl"
+#include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_xe_hpg_to_xe2_hpg.inl"
 #include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_xehp_and_later.inl"
 #include "level_zero/core/source/helpers/l0_populate_factory.h"
 
@@ -18,11 +20,6 @@ namespace L0 {
 using Family = NEO::XeHpgCoreFamily;
 static auto gfxCore = IGFX_XE_HPG_CORE;
 
-template <>
-zet_debug_regset_type_intel_gpu_t L0GfxCoreHelperHw<Family>::getRegsetTypeForLargeGrfDetection() const {
-    return ZET_DEBUG_REGSET_TYPE_CR_INTEL_GPU;
-}
-
 #include "level_zero/core/source/helpers/l0_gfx_core_helper_factory_init.inl"
 
 template class L0GfxCoreHelperHw<Family>;