diff --git a/Jenkinsfile b/Jenkinsfile index 3d051d3c8d..d38b36a5e0 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -7,4 +7,4 @@ * */ -dependenciesRevision='8b3508010c90fc3b9db303cf46ca9f9353a5c4ba-1995' +dependenciesRevision='f4c2b1eaed8dded91f30c42dd1f3d89b3b439c8d-2000' diff --git a/manifests/manifest.yml b/manifests/manifest.yml index e256bb352d..5160e94402 100644 --- a/manifests/manifest.yml +++ b/manifests/manifest.yml @@ -3,7 +3,7 @@ components: branch: master dest_dir: aub_stream repository: https://github.com/intel/aubstream - revision: 01846a70a2654582f7102e4ae4ed84a16e799eea + revision: ab1488b1d95eae4cf5a18b28d82dce561a6e5913 type: git gmmlib: dest_dir: gmmlib @@ -38,7 +38,7 @@ components: dest_dir: kernels_bin type: git branch: kernels_bin - revision: 1995-448 + revision: 2000-456 kmdaf: branch: kmdaf dest_dir: kmdaf @@ -78,5 +78,5 @@ components: dest_dir: wsl revision: 56430997dac34ca0e9e18c177636234cac26ad54 type: git -converter: M-1995 +converter: M-2000 version: '1' diff --git a/third_party/aub_stream/aubstream/headers/allocation_params.h b/third_party/aub_stream/aubstream/headers/allocation_params.h new file mode 100644 index 0000000000..46bd7094a9 --- /dev/null +++ b/third_party/aub_stream/aubstream/headers/allocation_params.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2022 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#include +#include +#include + +namespace aub_stream { + +struct AllocationParams { + AllocationParams() = delete; + AllocationParams(uint64_t gfxAddress, const void *memory, size_t size, uint32_t memoryBanks, int hint, size_t pageSize) + : gfxAddress(gfxAddress), memory(memory), size(size), memoryBanks(memoryBanks), hint(hint), pageSize(pageSize) { + additionalParams = {}; + } + + uint64_t gfxAddress = 0; + const void *memory = nullptr; + size_t size = 0; + uint32_t memoryBanks = 0; + int hint = 0; + size_t pageSize = 0; + + struct AdditionalParams { + bool compressionEnabled : 1; + bool uncached : 1; + bool padding : 6; + }; + + AdditionalParams additionalParams; +}; + +static_assert(std::is_standard_layout::value, "AllocationParams is not standard layout type"); + +} // namespace aub_stream diff --git a/third_party/aub_stream/aubstream/headers/aub_manager.h b/third_party/aub_stream/aubstream/headers/aub_manager.h new file mode 100644 index 0000000000..bd7184de6f --- /dev/null +++ b/third_party/aub_stream/aubstream/headers/aub_manager.h @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2022 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#include +#include +#include +#include "page_info.h" +#include "shared_mem_info.h" +#include "physical_allocation_info.h" + +namespace aub_stream { + +enum class ProductFamily : uint32_t; + +struct AllocationParams; +struct HardwareContext; + +struct AubManagerOptions { + uint32_t version{}; + uint32_t productFamily{}; + uint32_t devicesCount{}; + uint64_t memoryBankSize{}; + uint32_t stepping{}; + bool localMemorySupported{}; + uint32_t mode{}; + uint64_t gpuAddressSpace{}; + SharedMemoryInfo sharedMemoryInfo{}; + bool throwOnError{}; +}; + +class AubManager { + public: + virtual ~AubManager() = default; + + virtual HardwareContext *createHardwareContext(uint32_t device, uint32_t engine, uint32_t flags) = 0; + + virtual void open(const std::string &aubFileName) = 0; + virtual void close() = 0; + virtual bool isOpen() = 0; + virtual const std::string getFileName() = 0; + virtual void pause(bool onoff) = 0; + + virtual void addComment(const char *message) = 0; + virtual void writeMemory(uint64_t gfxAddress, const void *memory, size_t size, uint32_t memoryBanks, int hint, size_t pageSize) = 0; + virtual void writePageTableEntries(uint64_t gfxAddress, size_t size, uint32_t memoryBanks, int hint, + std::vector &lastLevelPages, size_t pageSize) = 0; + + virtual void writePhysicalMemoryPages(const void *memory, std::vector &pages, size_t size, int hint) = 0; + virtual void freeMemory(uint64_t gfxAddress, size_t size) = 0; + + static AubManager *create(uint32_t productFamily, uint32_t devicesCount, uint64_t memoryBankSize, uint32_t stepping, + bool localMemorySupported, uint32_t streamMode, uint64_t gpuAddressSpace); + + static AubManager *create(ProductFamily productFamily, uint32_t devicesCount, uint64_t memoryBankSize, uint32_t stepping, + bool localMemorySupported, uint32_t streamMode, uint64_t gpuAddressSpace); + + virtual void writeMemory2(AllocationParams allocationParams) = 0; + + static AubManager *create(const struct AubManagerOptions &options); + + virtual bool reservePhysicalMemory(AllocationParams allocationParams, PhysicalAllocationInfo &physicalAllocInfo) = 0; + virtual bool mapGpuVa(uint64_t gfxAddress, size_t size, PhysicalAllocationInfo physicalAllocInfo) = 0; +}; + +} // namespace aub_stream diff --git a/third_party/aub_stream/aubstream/headers/aubstream.h b/third_party/aub_stream/aubstream/headers/aubstream.h new file mode 100644 index 0000000000..cd595e9c4b --- /dev/null +++ b/third_party/aub_stream/aubstream/headers/aubstream.h @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2022 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#include +#include +#include +#include +#include + +namespace aub_stream { + +struct SurfaceInfo { + uint64_t address; + uint32_t width; + uint32_t height; + uint32_t pitch; + uint32_t format; + uint32_t surftype; + uint32_t tilingType; + bool compressed; + uint32_t dumpType; + bool useClearValue; + uint32_t clearColorType; + uint32_t auxEncodingFormat; + uint32_t auxSurfaceWidth; + uint32_t auxSurfaceHeight; + uint32_t auxSurfacePitch; + uint32_t auxSurfaceQPitch; + uint32_t auxSurfaceTilingType; + uint64_t clearColorAddress; + uint64_t auxSurfaceAddress; +}; + +namespace surftype { +constexpr uint32_t image1D = 0; +constexpr uint32_t image2D = 1; +constexpr uint32_t image3D = 2; +constexpr uint32_t buffer = 4; +} // namespace surftype + +namespace tilingType { +constexpr uint32_t linear = 0; +constexpr uint32_t xmajor = 2; +constexpr uint32_t ymajor = 3; +} // namespace tilingType + +namespace dumpType { +constexpr uint32_t bmp = 0; +constexpr uint32_t bin = 1; +constexpr uint32_t tre = 3; +} // namespace dumpType + +namespace mode { +constexpr uint32_t aubFile = 0; +constexpr uint32_t tbx = 1; +constexpr uint32_t aubFileAndTbx = 2; +constexpr uint32_t tbxShm = 3; +} // namespace mode + +namespace clearColorType { +constexpr uint32_t immediate = 0; +constexpr uint32_t address = 1; +} // namespace clearColorType + +using MMIOPair = std::pair; +using MMIOList = std::vector; + +extern "C" void injectMMIOList(MMIOList mmioList); +extern "C" void setTbxServerPort(uint16_t port); +extern "C" void setTbxServerIp(std::string server); +extern "C" void setTbxFrontdoorMode(bool frontdoor); + +static_assert(std::is_pod::value, "SurfaceInfo is not POD type"); + +} // namespace aub_stream diff --git a/third_party/aub_stream/aubstream/headers/engine_node.h b/third_party/aub_stream/aubstream/headers/engine_node.h new file mode 100644 index 0000000000..6320410fbe --- /dev/null +++ b/third_party/aub_stream/aubstream/headers/engine_node.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2022 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#include + +namespace aub_stream { + +enum EngineType : uint32_t { + ENGINE_RCS = 0, + ENGINE_BCS, + ENGINE_VCS, + ENGINE_VECS, + ENGINE_CCS, + ENGINE_CCS1, + ENGINE_CCS2, + ENGINE_CCS3, + ENGINE_CCCS, + ENGINE_BCS1, + ENGINE_BCS2, + ENGINE_BCS3, + ENGINE_BCS4, + ENGINE_BCS5, + ENGINE_BCS6, + ENGINE_BCS7, + ENGINE_BCS8, + NUM_ENGINES +}; + +} // namespace aub_stream diff --git a/third_party/aub_stream/aubstream/headers/hardware_context.h b/third_party/aub_stream/aubstream/headers/hardware_context.h new file mode 100644 index 0000000000..c1adaca9d4 --- /dev/null +++ b/third_party/aub_stream/aubstream/headers/hardware_context.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2022 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#include +#include + +namespace aub_stream { + +struct AllocationParams; +struct SurfaceInfo; + +struct HardwareContext { + virtual void initialize() = 0; + virtual void pollForCompletion() = 0; + virtual void writeAndSubmitBatchBuffer(uint64_t gfxAddress, const void *batchBuffer, size_t size, uint32_t memoryBanks, size_t pageSize) = 0; + virtual void submitBatchBuffer(uint64_t gfxAddress, bool overrideRingHead) = 0; + virtual void writeMemory(uint64_t gfxAddress, const void *memory, size_t size, uint32_t memoryBanks, int hint, size_t pageSize) = 0; + virtual void freeMemory(uint64_t gfxAddress, size_t size) = 0; + virtual void expectMemory(uint64_t gfxAddress, const void *memory, size_t size, uint32_t compareOperation) = 0; + virtual void readMemory(uint64_t gfxAddress, void *memory, size_t size, uint32_t memoryBanks, size_t pageSize) = 0; + virtual void dumpBufferBIN(uint64_t gfxAddress, size_t size) = 0; + virtual void dumpSurface(const SurfaceInfo &surfaceInfo) = 0; + virtual ~HardwareContext() = default; + virtual void writeMemory2(AllocationParams allocationParams) = 0; + virtual void writeMMIO(uint32_t offset, uint32_t value) = 0; + virtual void pollForFenceCompletion() = 0; +}; + +} // namespace aub_stream diff --git a/third_party/aub_stream/aubstream/headers/page_info.h b/third_party/aub_stream/aubstream/headers/page_info.h new file mode 100644 index 0000000000..31d613814b --- /dev/null +++ b/third_party/aub_stream/aubstream/headers/page_info.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2022 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#include +#include + +namespace aub_stream { + +struct PageInfo { + uint64_t physicalAddress; + size_t size; + bool isLocalMemory; + uint32_t memoryBank; +}; + +static_assert(std::is_pod::value, "PageInfo is not POD type"); + +} // namespace aub_stream \ No newline at end of file diff --git a/third_party/aub_stream/aubstream/headers/physical_allocation_info.h b/third_party/aub_stream/aubstream/headers/physical_allocation_info.h new file mode 100644 index 0000000000..0c5a08819c --- /dev/null +++ b/third_party/aub_stream/aubstream/headers/physical_allocation_info.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2022 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#include +#include + +namespace aub_stream { + +struct PhysicalAllocationInfo { + uint64_t physicalAddress; + size_t size; + uint32_t memoryBank; + size_t pageSize; +}; + +static_assert(std::is_pod::value, "PhysicalAllocationInfo is not POD type"); + +} // namespace aub_stream \ No newline at end of file diff --git a/third_party/aub_stream/aubstream/headers/product_family.h b/third_party/aub_stream/aubstream/headers/product_family.h new file mode 100644 index 0000000000..1ae1ad9035 --- /dev/null +++ b/third_party/aub_stream/aubstream/headers/product_family.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2022 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#include + +namespace aub_stream { + +enum class ProductFamily : uint32_t { + Bdw, + Skl, + Kbl, + Cfl, + Bxt, + Glk, + Icllp, + Tgllp, + Adls, + Adlp, + Adln, + Dg1, + XeHpSdv, + Dg2, + Pvc, + MaxProduct, +}; +} // namespace aub_stream diff --git a/third_party/aub_stream/aubstream/headers/shared_mem_info.h b/third_party/aub_stream/aubstream/headers/shared_mem_info.h new file mode 100644 index 0000000000..d6e414b057 --- /dev/null +++ b/third_party/aub_stream/aubstream/headers/shared_mem_info.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2022 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#include + +namespace aub_stream { + +struct SharedMemoryInfo { + uint8_t *sysMemBase{}; + uint64_t sysMemSize{}; + + uint8_t *localMemBase{}; + uint64_t localMemSize{}; +}; + +} // namespace aub_stream