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Correct formatting

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Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
This commit is contained in:
Filip Hazubski
2021-03-15 11:39:58 +00:00
committed by Compute-Runtime-Automation
parent 264f20ea00
commit 9a8125cdb0
27 changed files with 76 additions and 68 deletions
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8
opencl/test/unit_test/command_queue/enqueue_copy_buffer_rect_tests.cpp
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2020 Intel Corporation
* Copyright (C) 2017-2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@ -125,7 +125,8 @@ HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyBufferRectTest, WhenCopyingBufferRect2DTh
// Compute the SIMD lane mask
size_t simd =
cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD32 ? 32 : cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD16 ? 16 : 8;
cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD32 ? 32 : cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD16 ? 16
: 8;
uint64_t simdMask = maxNBitValue(simd);
// Mask off lanes based on the execution masks
@ -306,7 +307,8 @@ HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyBufferRectTest, WhenCopyingBufferRect3DTh
// Compute the SIMD lane mask
size_t simd =
cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD32 ? 32 : cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD16 ? 16 : 8;
cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD32 ? 32 : cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD16 ? 16
: 8;
uint64_t simdMask = maxNBitValue(simd);
// Mask off lanes based on the execution masks

5
opencl/test/unit_test/command_queue/enqueue_copy_buffer_tests.cpp
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2020 Intel Corporation
* Copyright (C) 2017-2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@ -152,7 +152,8 @@ HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyBufferTest, WhenCopyingBufferThenGpgpuWal
// Compute the SIMD lane mask
size_t simd =
cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD32 ? 32 : cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD16 ? 16 : 8;
cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD32 ? 32 : cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD16 ? 16
: 8;
uint64_t simdMask = maxNBitValue(simd);
// Mask off lanes based on the execution masks

3
opencl/test/unit_test/command_queue/enqueue_copy_image_tests.cpp
View File

@ -40,7 +40,8 @@ HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyImageTest, WhenCopyingImageThenGpgpuWalke
// Compute the SIMD lane mask
size_t simd =
cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD32 ? 32 : cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD16 ? 16 : 8;
cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD32 ? 32 : cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD16 ? 16
: 8;
uint64_t simdMask = maxNBitValue(simd);
// Mask off lanes based on the execution masks

3
opencl/test/unit_test/command_queue/enqueue_copy_image_to_buffer_tests.cpp
View File

@ -42,7 +42,8 @@ HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyImageToBufferTest, WhenCopyingImageToBuff
// Compute the SIMD lane mask
size_t simd =
cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD32 ? 32 : cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD16 ? 16 : 8;
cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD32 ? 32 : cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD16 ? 16
: 8;
uint64_t simdMask = maxNBitValue(simd);
// Mask off lanes based on the execution masks

5
opencl/test/unit_test/command_queue/enqueue_fill_image_tests.cpp
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2020 Intel Corporation
* Copyright (C) 2017-2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@ -60,7 +60,8 @@ HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueFillImageTest, WhenFillingImageThenGpgpuWalke
// Compute the SIMD lane mask
size_t simd =
cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD32 ? 32 : cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD16 ? 16 : 8;
cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD32 ? 32 : cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD16 ? 16
: 8;
uint64_t simdMask = maxNBitValue(simd);
// Mask off lanes based on the execution masks

5
opencl/test/unit_test/command_queue/enqueue_read_buffer_rect_tests.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2020 Intel Corporation
* Copyright (C) 2017-2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@ -138,7 +138,8 @@ HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueReadBufferRectTest, Given2dRegionWhenReadingB
// Compute the SIMD lane mask
size_t simd =
cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD32 ? 32 : cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD16 ? 16 : 8;
cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD32 ? 32 : cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD16 ? 16
: 8;
uint64_t simdMask = maxNBitValue(simd);
// Mask off lanes based on the execution masks

5
opencl/test/unit_test/command_queue/enqueue_write_buffer_rect_tests.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2020 Intel Corporation
* Copyright (C) 2017-2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@ -113,7 +113,8 @@ HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueWriteBufferRectTest, Given2dRegionWhenWriting
// Compute the SIMD lane mask
size_t simd =
cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD32 ? 32 : cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD16 ? 16 : 8;
cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD32 ? 32 : cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD16 ? 16
: 8;
uint64_t simdMask = maxNBitValue(simd);
// Mask off lanes based on the execution masks

4
opencl/test/unit_test/mocks/mock_cif.cpp
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2020 Intel Corporation
* Copyright (C) 2018-2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@ -20,7 +20,7 @@ namespace CIF {
namespace Builtins {
template <typename... ArgsT>
Buffer<0>::Buffer(ArgsT &&... args) {
Buffer<0>::Buffer(ArgsT &&...args) {
}
Buffer<0>::~Buffer() {

12
opencl/test/unit_test/mocks/mock_event.h
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2020 Intel Corporation
* Copyright (C) 2017-2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@ -12,14 +12,14 @@
namespace NEO {
#define FORWARD_CONSTRUCTOR(THIS_CLASS, BASE_CLASS) \
template <typename... ArgsT> \
THIS_CLASS(ArgsT &&... args) : BASE_CLASS(std::forward<ArgsT>(args)...) { \
#define FORWARD_CONSTRUCTOR(THIS_CLASS, BASE_CLASS) \
template <typename... ArgsT> \
THIS_CLASS(ArgsT &&...args) : BASE_CLASS(std::forward<ArgsT>(args)...) { \
}
#define FORWARD_FUNC(FUNC_NAME, BASE_CLASS) \
template <typename... ArgsT> \
void FUNC_NAME(ArgsT &&... args) { \
void FUNC_NAME(ArgsT &&...args) { \
BASE_CLASS::FUNC_NAME(std::forward<ArgsT>(args)...); \
}
@ -52,7 +52,7 @@ struct MockEventBuilder : EventBuilder {
}
template <typename EventType, typename... ArgsT>
static EventType *createAndFinalize(ArgsT &&... args) {
static EventType *createAndFinalize(ArgsT &&...args) {
MockEventBuilder mb;
mb.create<EventType>(std::forward<ArgsT>(args)...);
return static_cast<EventType *>(mb.finalizeAndRelease());