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Remove HW types from synchronization interface

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Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
This commit is contained in:
Dunajski, Bartosz
2022-07-21 14:28:10 +00:00
committed by Compute-Runtime-Automation
parent 975e2af781
commit a3903c385e
87 changed files with 459 additions and 502 deletions
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2
opencl/test/unit_test/gen12lp/coherency_tests_gen12lp.inl
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@ -244,7 +244,7 @@ GEN12LPTEST_F(Gen12LpCoherencyRequirements, givenCoherencyRequirementWithoutShar
auto hwInfo = device->getHardwareInfo();
flushTask(false);
if (MemorySynchronizationCommands<FamilyType>::isPipeControlPriorToPipelineSelectWArequired(hwInfo)) {
if (MemorySynchronizationCommands<FamilyType>::isBarrierlPriorToPipelineSelectWaRequired(hwInfo)) {
findCmd(true, false, true); // first time
} else {
findCmd(true, false, false); // first time

4
opencl/test/unit_test/gen12lp/command_stream_receiver_hw_tests_gen12lp.inl
View File

@ -84,7 +84,7 @@ GEN12LPTEST_F(UltCommandStreamReceiverTestGen12Lp, givenDebugEnablingCacheFlushW
LinearStream stream(buff, sizeof(PIPE_CONTROL) * 3);
PipeControlArgs args;
MemorySynchronizationCommands<FamilyType>::addPipeControl(stream, args);
MemorySynchronizationCommands<FamilyType>::addSingleBarrier(stream, args);
parseCommands<FamilyType>(stream, 0);
@ -111,7 +111,7 @@ GEN12LPTEST_F(UltCommandStreamReceiverTestGen12Lp, givenDebugDisablingCacheFlush
PipeControlArgs args;
args.dcFlushEnable = true;
args.hdcPipelineFlush = true;
MemorySynchronizationCommands<FamilyType>::addPipeControl(stream, args);
MemorySynchronizationCommands<FamilyType>::addSingleBarrier(stream, args);
parseCommands<FamilyType>(stream, 0);