Add xe_hpg common tests

Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>

shared/test/common/helpers/CMakeLists.txt

@@ -44,6 +44,12 @@ if(TESTS_XEHP_AND_LATER)
   )
 endif()
 
+if(TESTS_DG2_AND_LATER)
+  list(APPEND NEO_CORE_HELPERS_TESTS
+       ${CMAKE_CURRENT_SOURCE_DIR}/hw_helper_tests_dg2_and_later.cpp
+  )
+endif()
+
 add_subdirectories()
 
 target_sources(${TARGET_NAME} PRIVATE

shared/test/common/helpers/hw_helper_tests_dg2_and_later.cpp

@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "shared/source/helpers/hw_helper.h"
+#include "shared/test/common/fixtures/device_fixture.h"
+
+#include "test.h"
+
+using namespace NEO;
+
+using HwHelperDg2AndLaterTest = Test<DeviceFixture>;
+
+HWTEST2_F(HwHelperDg2AndLaterTest, GivenUseL1CacheAsTrueWhenCallSetL1CachePolicyThenL1CachePolicyL1CacheControlIsSetProperly, IsAtLeastXeHpgCore) {
+    using RENDER_SURFACE_STATE = typename FamilyType::RENDER_SURFACE_STATE;
+    using SURFACE_TYPE = typename RENDER_SURFACE_STATE::SURFACE_TYPE;
+
+    auto &helper = reinterpret_cast<HwHelperHw<FamilyType> &>(HwHelperHw<FamilyType>::get());
+
+    RENDER_SURFACE_STATE surfaceState = FamilyType::cmdInitRenderSurfaceState;
+    bool useL1Cache = true;
+    helper.setL1CachePolicy(useL1Cache, &surfaceState, defaultHwInfo.get());
+    EXPECT_EQ(RENDER_SURFACE_STATE::L1_CACHE_POLICY_WB, surfaceState.getL1CachePolicyL1CacheControl());
+}
+HWTEST2_F(HwHelperDg2AndLaterTest, GivenUseL1CacheAsFalseWhenCallSetL1CachePolicyThenL1CachePolicyL1CacheControlIsNotSet, IsAtLeastXeHpgCore) {
+    using RENDER_SURFACE_STATE = typename FamilyType::RENDER_SURFACE_STATE;
+    using SURFACE_TYPE = typename RENDER_SURFACE_STATE::SURFACE_TYPE;
+
+    auto &helper = reinterpret_cast<HwHelperHw<FamilyType> &>(HwHelperHw<FamilyType>::get());
+    RENDER_SURFACE_STATE surfaceState = FamilyType::cmdInitRenderSurfaceState;
+    bool useL1Cache = false;
+    helper.setL1CachePolicy(useL1Cache, &surfaceState, defaultHwInfo.get());
+    EXPECT_NE(RENDER_SURFACE_STATE::L1_CACHE_POLICY_WB, surfaceState.getL1CachePolicyL1CacheControl());
+}

shared/test/common/helpers/includes/test_traits_common.h

@@ -11,3 +11,4 @@
 #include "shared/test/common/gen8/test_traits_gen8.h"
 #include "shared/test/common/gen9/test_traits_gen9.h"
 #include "shared/test/common/xe_hp_core/test_traits_xe_hp_core.h"
+#include "shared/test/common/xe_hpg_core/test_traits_xe_hpg_core.h"

shared/test/common/libult/xe_hpg_core.cpp

@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "shared/source/helpers/populate_factory.h"
+#include "shared/test/common/libult/ult_command_stream_receiver.h"
+
+namespace NEO {
+
+typedef XE_HPG_COREFamily Family;
+
+static auto gfxCore = IGFX_XE_HPG_CORE;
+
+extern CommandStreamReceiverCreateFunc commandStreamReceiverFactory[2 * IGFX_MAX_CORE];
+
+template <>
+void populateFactoryTable<UltCommandStreamReceiver<Family>>() {
+    commandStreamReceiverFactory[IGFX_MAX_CORE + gfxCore] = UltCommandStreamReceiver<Family>::create;
+}
+
+struct enableXeHpgCore {
+    enableXeHpgCore() {
+        populateFactoryTable<UltCommandStreamReceiver<Family>>();
+    }
+};
+
+static enableXeHpgCore enable;
+
+template class UltCommandStreamReceiver<XE_HPG_COREFamily>;
+} // namespace NEO

shared/test/common/test_configuration/aub_tests/xe_hpg_core/CMakeLists.txt

@@ -0,0 +1,15 @@
+#
+# Copyright (C) 2021 Intel Corporation
+#
+# SPDX-License-Identifier: MIT
+#
+
+if(TESTS_XE_HPG_CORE)
+  set(NEO_SHARED_aub_tests_configurations
+      ${NEO_SHARED_aub_tests_configurations}
+      ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
+      ${CMAKE_CURRENT_SOURCE_DIR}/aub_tests_configuration_xe_hpg_core.cpp
+  )
+
+  set(NEO_SHARED_aub_tests_configurations ${NEO_SHARED_aub_tests_configurations} PARENT_SCOPE)
+endif()

shared/test/common/test_configuration/aub_tests/xe_hpg_core/aub_tests_configuration_xe_hpg_core.cpp

@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "shared/test/common/test_configuration/aub_tests/aub_tests_configuration.h"
+
+#include "hw_cmds.h"
+
+using namespace NEO;
+
+template <>
+AubTestsConfig GetAubTestsConfig<XE_HPG_COREFamily>() {
+    AubTestsConfig aubTestsConfig;
+    aubTestsConfig.testCanonicalAddress = true;
+    return aubTestsConfig;
+}

shared/test/common/xe_hpg_core/CMakeLists.txt

@@ -0,0 +1,30 @@
+#
+# Copyright (C) 2021 Intel Corporation
+#
+# SPDX-License-Identifier: MIT
+#
+
+if(TESTS_XE_HPG_CORE)
+
+  set(NEO_CORE_TESTS_XE_HPG_CORE
+      ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
+      ${CMAKE_CURRENT_SOURCE_DIR}/simd_helper_tests_xe_hpg_core.cpp
+      ${CMAKE_CURRENT_SOURCE_DIR}/test_traits_xe_hpg_core.h
+  )
+  set_property(GLOBAL PROPERTY NEO_CORE_TESTS_XE_HPG_CORE ${NEO_CORE_TESTS_XE_HPG_CORE})
+  add_subdirectories()
+
+  set(IGDRCL_SRCS_tests_xe_hpg_core_excludes
+      ${CMAKE_CURRENT_SOURCE_DIR}/excludes_xe_hpg_core.cpp
+  )
+  set_property(GLOBAL APPEND PROPERTY IGDRCL_SRCS_tests_excludes ${IGDRCL_SRCS_tests_xe_hpg_core_excludes})
+
+  target_sources(${TARGET_NAME} PRIVATE
+                 ${IGDRCL_SRCS_tests_xe_hpg_core_excludes}
+                 ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
+                 ${CMAKE_CURRENT_SOURCE_DIR}/image_surface_state_tests_xe_hpg_core.cpp
+                 ${CMAKE_CURRENT_SOURCE_DIR}/test_preemption_xe_hpg_core.cpp
+                 ${COMPUTE_RUNTIME_ULT_XE_HPG_CORE}
+  )
+
+endif()

shared/test/common/xe_hpg_core/cmd_parse_xe_hpg_core.cpp

@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "shared/source/xe_hpg_core/hw_cmds.h"
+using GenStruct = NEO::XE_HPG_CORE;
+using GenGfxFamily = NEO::XE_HPG_COREFamily;
+#include "shared/test/common/cmd_parse/cmd_parse_xehp_and_later.inl"

shared/test/common/xe_hpg_core/dg2/CMakeLists.txt

@@ -0,0 +1,23 @@
+#
+# Copyright (C) 2021 Intel Corporation
+#
+# SPDX-License-Identifier: MIT
+#
+
+if(TESTS_DG2)
+  set(IGDRCL_SRCS_tests_xe_hpg_core_dg2_excludes
+      ${CMAKE_CURRENT_SOURCE_DIR}/excludes_dg2.cpp
+  )
+  set_property(GLOBAL APPEND PROPERTY IGDRCL_SRCS_tests_excludes ${IGDRCL_SRCS_tests_xe_hpg_core_dg2_excludes})
+
+  set(NEO_CORE_TESTS_XE_HPG_CORE_DG2
+      ${IGDRCL_SRCS_tests_xe_hpg_core_dg2_excludes}
+      ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
+      ${CMAKE_CURRENT_SOURCE_DIR}/test_encode_dispatch_kernel_dg2.cpp
+      ${CMAKE_CURRENT_SOURCE_DIR}/test_hw_info_config_dg2.cpp
+      ${CMAKE_CURRENT_SOURCE_DIR}/test_hw_helper_dg2.cpp
+      ${CMAKE_CURRENT_SOURCE_DIR}/test_encode_dg2.cpp
+  )
+
+  target_sources(${TARGET_NAME} PRIVATE ${NEO_CORE_TESTS_XE_HPG_CORE_DG2})
+endif()

shared/test/common/xe_hpg_core/dg2/excludes_dg2.cpp

@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "test.h"
+
+HWTEST_EXCLUDE_PRODUCT(CommandEncodeStatesTest, givenSlmTotalSizeEqualZeroWhenDispatchingKernelThenSharedMemorySizeIsSetCorrectly, IGFX_DG2);

shared/test/common/xe_hpg_core/dg2/test_encode_dg2.cpp

@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "shared/source/command_container/command_encoder.h"
+#include "shared/source/command_stream/stream_properties.h"
+#include "shared/test/common/helpers/default_hw_info.h"
+
+#include "test.h"
+
+#include "hw_cmds.h"
+
+using namespace NEO;
+
+using CommandEncodeDG2Test = ::testing::Test;
+
+DG2TEST_F(CommandEncodeDG2Test, whenProgrammingStateComputeModeThenProperFieldsAreSet) {
+    using STATE_COMPUTE_MODE = typename FamilyType::STATE_COMPUTE_MODE;
+    using PIXEL_ASYNC_COMPUTE_THREAD_LIMIT = typename STATE_COMPUTE_MODE::PIXEL_ASYNC_COMPUTE_THREAD_LIMIT;
+    using Z_PASS_ASYNC_COMPUTE_THREAD_LIMIT = typename STATE_COMPUTE_MODE::Z_PASS_ASYNC_COMPUTE_THREAD_LIMIT;
+    uint8_t buffer[64]{};
+
+    StateComputeModeProperties properties;
+    auto pLinearStream = std::make_unique<LinearStream>(buffer, sizeof(buffer));
+    EncodeComputeMode<FamilyType>::adjustComputeMode(*pLinearStream, nullptr, properties, *defaultHwInfo);
+    auto pScm = reinterpret_cast<STATE_COMPUTE_MODE *>(pLinearStream->getCpuBase());
+    EXPECT_EQ(0u, pScm->getMaskBits());
+    EXPECT_EQ(STATE_COMPUTE_MODE::FORCE_NON_COHERENT_FORCE_DISABLED, pScm->getForceNonCoherent());
+    EXPECT_EQ(STATE_COMPUTE_MODE::PIXEL_ASYNC_COMPUTE_THREAD_LIMIT_DISABLED, pScm->getPixelAsyncComputeThreadLimit());
+    EXPECT_EQ(STATE_COMPUTE_MODE::Z_PASS_ASYNC_COMPUTE_THREAD_LIMIT_MAX_60, pScm->getZPassAsyncComputeThreadLimit());
+    EXPECT_FALSE(pScm->getLargeGrfMode());
+
+    properties.isCoherencyRequired.value = 0;
+    properties.zPassAsyncComputeThreadLimit.value = 1;
+    properties.pixelAsyncComputeThreadLimit.value = 1;
+    properties.largeGrfMode.value = 1;
+    pLinearStream = std::make_unique<LinearStream>(buffer, sizeof(buffer));
+    EncodeComputeMode<FamilyType>::adjustComputeMode(*pLinearStream, nullptr, properties, *defaultHwInfo);
+    pScm = reinterpret_cast<STATE_COMPUTE_MODE *>(pLinearStream->getCpuBase());
+    EXPECT_EQ(0u, pScm->getMaskBits());
+    EXPECT_EQ(STATE_COMPUTE_MODE::FORCE_NON_COHERENT_FORCE_DISABLED, pScm->getForceNonCoherent());
+    EXPECT_EQ(STATE_COMPUTE_MODE::PIXEL_ASYNC_COMPUTE_THREAD_LIMIT_DISABLED, pScm->getPixelAsyncComputeThreadLimit());
+    EXPECT_EQ(STATE_COMPUTE_MODE::Z_PASS_ASYNC_COMPUTE_THREAD_LIMIT_MAX_60, pScm->getZPassAsyncComputeThreadLimit());
+    EXPECT_FALSE(pScm->getLargeGrfMode());
+
+    properties.isCoherencyRequired.isDirty = true;
+    properties.zPassAsyncComputeThreadLimit.isDirty = true;
+    properties.pixelAsyncComputeThreadLimit.isDirty = true;
+    properties.largeGrfMode.isDirty = true;
+    pLinearStream = std::make_unique<LinearStream>(buffer, sizeof(buffer));
+    EncodeComputeMode<FamilyType>::adjustComputeMode(*pLinearStream, nullptr, properties, *defaultHwInfo);
+    pScm = reinterpret_cast<STATE_COMPUTE_MODE *>(pLinearStream->getCpuBase());
+    auto expectedMask = FamilyType::stateComputeModeForceNonCoherentMask |
+                        FamilyType::stateComputeModeZPassAsyncComputeThreadLimitMask |
+                        FamilyType::stateComputeModePixelAsyncComputeThreadLimitMask | FamilyType::stateComputeModeLargeGrfModeMask;
+    EXPECT_EQ(expectedMask, pScm->getMaskBits());
+    EXPECT_EQ(STATE_COMPUTE_MODE::FORCE_NON_COHERENT_FORCE_GPU_NON_COHERENT, pScm->getForceNonCoherent());
+    EXPECT_EQ(STATE_COMPUTE_MODE::PIXEL_ASYNC_COMPUTE_THREAD_LIMIT_MAX_2, pScm->getPixelAsyncComputeThreadLimit());
+    EXPECT_EQ(STATE_COMPUTE_MODE::Z_PASS_ASYNC_COMPUTE_THREAD_LIMIT_MAX_64, pScm->getZPassAsyncComputeThreadLimit());
+    EXPECT_TRUE(pScm->getLargeGrfMode());
+}

shared/test/common/xe_hpg_core/dg2/test_encode_dispatch_kernel_dg2.cpp

@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "shared/source/command_container/command_encoder.h"
+#include "shared/source/helpers/hw_helper.h"
+#include "shared/source/os_interface/hw_info_config.h"
+#include "shared/test/common/helpers/default_hw_info.h"
+#include "shared/test/common/helpers/variable_backup.h"
+
+#include "test.h"
+
+#include "hw_cmds.h"
+
+using namespace NEO;
+
+using CommandEncodeStatesDg2Test = ::testing::Test;
+
+DG2TEST_F(CommandEncodeStatesDg2Test, GivenSmallSlmTotalSizesWhenSetAdditionalInfoIsCalledThenCorrectValuesAreSet) {
+    using INTERFACE_DESCRIPTOR_DATA = typename FamilyType::INTERFACE_DESCRIPTOR_DATA;
+    using PREFERRED_SLM_SIZE_OVERRIDE = typename INTERFACE_DESCRIPTOR_DATA::PREFERRED_SLM_SIZE_OVERRIDE;
+    using PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS = typename INTERFACE_DESCRIPTOR_DATA::PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS;
+
+    VariableBackup<unsigned short> revisionId(&defaultHwInfo->platform.usRevId);
+    uint32_t threadsCount = 1;
+    uint32_t slmTotalSize = 0;
+
+    {
+        revisionId = HwInfoConfig::get(productFamily)->getHwRevIdFromStepping(REVISION_A0, *defaultHwInfo);
+        INTERFACE_DESCRIPTOR_DATA idd = FamilyType::cmdInitInterfaceDescriptorData;
+        EncodeDispatchKernel<FamilyType>::appendAdditionalIDDFields(&idd, *defaultHwInfo, threadsCount, slmTotalSize, SlmPolicy::SlmPolicyNone);
+        EXPECT_EQ(PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS::PREFERRED_SLM_SIZE_IS_128K, idd.getPreferredSlmAllocationSizePerDss());
+    }
+    {
+        revisionId = HwInfoConfig::get(productFamily)->getHwRevIdFromStepping(REVISION_B, *defaultHwInfo);
+        INTERFACE_DESCRIPTOR_DATA idd = FamilyType::cmdInitInterfaceDescriptorData;
+        EncodeDispatchKernel<FamilyType>::appendAdditionalIDDFields(&idd, *defaultHwInfo, threadsCount, slmTotalSize, SlmPolicy::SlmPolicyNone);
+        EXPECT_EQ(PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS::PREFERRED_SLM_SIZE_IS_0K, idd.getPreferredSlmAllocationSizePerDss());
+    }
+}
+
+DG2TEST_F(CommandEncodeStatesDg2Test, givenNoWorkaroundNeededWhenSelectingPreferredSlmSizePerDssThenUseDssCount) {
+    using INTERFACE_DESCRIPTOR_DATA = typename FamilyType::INTERFACE_DESCRIPTOR_DATA;
+    using PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS = typename INTERFACE_DESCRIPTOR_DATA::PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS;
+
+    HardwareInfo hwInfo = *defaultHwInfo;
+    hwInfo.platform.usRevId = HwInfoConfig::get(productFamily)->getHwRevIdFromStepping(REVISION_B, *defaultHwInfo);
+    hwInfo.gtSystemInfo.ThreadCount = 1024;
+    hwInfo.gtSystemInfo.DualSubSliceCount = 8;
+    hwInfo.gtSystemInfo.SubSliceCount = 2 * hwInfo.gtSystemInfo.DualSubSliceCount;
+
+    {
+        const uint32_t threadsPerThreadGroup = 7; // 18 groups will fit in one DSS
+        const uint32_t slmSizePerThreadGroup = 2 * MemoryConstants::kiloByte;
+        INTERFACE_DESCRIPTOR_DATA idd = FamilyType::cmdInitInterfaceDescriptorData;
+        EncodeDispatchKernel<FamilyType>::appendAdditionalIDDFields(&idd, hwInfo, threadsPerThreadGroup, slmSizePerThreadGroup, SlmPolicy::SlmPolicyLargeSlm);
+        EXPECT_EQ(PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS::PREFERRED_SLM_SIZE_IS_64K, idd.getPreferredSlmAllocationSizePerDss());
+    }
+    {
+        const uint32_t threadsPerThreadGroup = 8; // 16 groups will fit in one DSS
+        const uint32_t slmSizePerThreadGroup = 2 * MemoryConstants::kiloByte;
+        INTERFACE_DESCRIPTOR_DATA idd = FamilyType::cmdInitInterfaceDescriptorData;
+        EncodeDispatchKernel<FamilyType>::appendAdditionalIDDFields(&idd, hwInfo, threadsPerThreadGroup, slmSizePerThreadGroup, SlmPolicy::SlmPolicyLargeSlm);
+        EXPECT_EQ(PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS::PREFERRED_SLM_SIZE_IS_32K, idd.getPreferredSlmAllocationSizePerDss());
+    }
+    {
+        const uint32_t threadsPerThreadGroup = 9; // 14 groups will fit in one DSS
+        const uint32_t slmSizePerThreadGroup = 2 * MemoryConstants::kiloByte;
+        INTERFACE_DESCRIPTOR_DATA idd = FamilyType::cmdInitInterfaceDescriptorData;
+        EncodeDispatchKernel<FamilyType>::appendAdditionalIDDFields(&idd, hwInfo, threadsPerThreadGroup, slmSizePerThreadGroup, SlmPolicy::SlmPolicyLargeSlm);
+        EXPECT_EQ(PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS::PREFERRED_SLM_SIZE_IS_32K, idd.getPreferredSlmAllocationSizePerDss());
+    }
+    {
+        const uint32_t threadsPerThreadGroup = 50; // 2 groups will fit in one DSS
+        const uint32_t slmSizePerThreadGroup = 16 * MemoryConstants::kiloByte;
+        INTERFACE_DESCRIPTOR_DATA idd = FamilyType::cmdInitInterfaceDescriptorData;
+        EncodeDispatchKernel<FamilyType>::appendAdditionalIDDFields(&idd, hwInfo, threadsPerThreadGroup, slmSizePerThreadGroup, SlmPolicy::SlmPolicyLargeSlm);
+        EXPECT_EQ(PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS::PREFERRED_SLM_SIZE_IS_32K, idd.getPreferredSlmAllocationSizePerDss());
+    }
+}

shared/test/common/xe_hpg_core/dg2/test_hw_helper_dg2.cpp

@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "shared/source/helpers/hw_helper.h"
+#include "shared/source/os_interface/hw_info_config.h"
+#include "shared/test/common/helpers/default_hw_info.h"
+#include "shared/test/common/helpers/hw_helper_tests.h"
+
+#include "test.h"
+
+using namespace NEO;
+using HwHelperTestDg2 = ::testing::Test;
+
+DG2TEST_F(HwHelperTestDg2, GivenDifferentSteppingWhenComputeSlmSizeIsCalledThenCorrectValueIsReturned) {
+    using SHARED_LOCAL_MEMORY_SIZE = typename FamilyType::INTERFACE_DESCRIPTOR_DATA::SHARED_LOCAL_MEMORY_SIZE;
+
+    __REVID revisions[] = {REVISION_A0, REVISION_B};
+    auto &hwHelper = HwHelperHw<FamilyType>::get();
+    const auto &hwInfoConfig = *HwInfoConfig::get(productFamily);
+
+    auto hwInfo = *defaultHwInfo;
+    for (auto revision : revisions) {
+        hwInfo.platform.usRevId = hwInfoConfig.getHwRevIdFromStepping(revision, hwInfo);
+        for (auto &testInput : computeSlmValuesXeHPAndLaterTestsInput) {
+            EXPECT_EQ(testInput.expected, hwHelper.computeSlmValues(hwInfo, testInput.slmSize));
+        }
+    }
+}

shared/test/common/xe_hpg_core/dg2/test_hw_info_config_dg2.cpp

@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "shared/source/os_interface/hw_info_config.h"
+#include "shared/test/common/fixtures/device_fixture.h"
+
+#include "test.h"
+
+using namespace NEO;
+
+using TestDg2HwInfoConfig = Test<DeviceFixture>;
+
+HWTEST_EXCLUDE_PRODUCT(HwInfoConfigTestWindows, givenHardwareInfoWhenCallingIsAdditionalStateBaseAddressWARequiredThenFalseIsReturned, IGFX_DG2);
+HWTEST_EXCLUDE_PRODUCT(HwInfoConfigTestWindows, givenHardwareInfoWhenCallingIsMaxThreadsForWorkgroupWARequiredThenFalseIsReturned, IGFX_DG2);
+
+DG2TEST_F(TestDg2HwInfoConfig, givenDG2WithCSteppingThenAdditionalStateBaseAddressWAIsNotRequired) {
+    const auto &hwInfoConfig = *HwInfoConfig::get(productFamily);
+    auto hwInfo = pDevice->getRootDeviceEnvironment().getMutableHardwareInfo();
+    hwInfo->platform.usRevId = hwInfoConfig.getHwRevIdFromStepping(REVISION_C, *hwInfo);
+    auto isWARequired = hwInfoConfig.isAdditionalStateBaseAddressWARequired(pDevice->getHardwareInfo());
+    EXPECT_FALSE(isWARequired);
+}
+
+DG2TEST_F(TestDg2HwInfoConfig, givenDG2WithBSteppingThenAdditionalStateBaseAddressWAIsRequired) {
+    const auto &hwInfoConfig = *HwInfoConfig::get(productFamily);
+    auto hwInfo = pDevice->getRootDeviceEnvironment().getMutableHardwareInfo();
+    hwInfo->platform.usRevId = hwInfoConfig.getHwRevIdFromStepping(REVISION_B, *hwInfo);
+    auto isWARequired = hwInfoConfig.isAdditionalStateBaseAddressWARequired(pDevice->getHardwareInfo());
+    EXPECT_TRUE(isWARequired);
+}
+
+DG2TEST_F(TestDg2HwInfoConfig, givenDG2WithA0SteppingThenMaxThreadsForWorkgroupWAIsRequired) {
+    const auto &hwInfoConfig = *HwInfoConfig::get(productFamily);
+    auto hwInfo = pDevice->getRootDeviceEnvironment().getMutableHardwareInfo();
+    hwInfo->platform.usRevId = hwInfoConfig.getHwRevIdFromStepping(REVISION_A0, *hwInfo);
+    auto isWARequired = hwInfoConfig.isMaxThreadsForWorkgroupWARequired(pDevice->getHardwareInfo());
+    EXPECT_TRUE(isWARequired);
+}
+
+DG2TEST_F(TestDg2HwInfoConfig, givenDG2WithBSteppingThenMaxThreadsForWorkgroupWAIsNotRequired) {
+    const auto &hwInfoConfig = *HwInfoConfig::get(productFamily);
+    auto hwInfo = pDevice->getRootDeviceEnvironment().getMutableHardwareInfo();
+    hwInfo->platform.usRevId = hwInfoConfig.getHwRevIdFromStepping(REVISION_A1, *hwInfo);
+    auto isWARequired = hwInfoConfig.isMaxThreadsForWorkgroupWARequired(pDevice->getHardwareInfo());
+    EXPECT_FALSE(isWARequired);
+}
+
+DG2TEST_F(TestDg2HwInfoConfig, givenSteppingWhenAskingForLocalMemoryAccessModeThenDisallowOnA0) {
+    HardwareInfo hwInfo = *defaultHwInfo;
+    const auto &hwInfoConfig = *HwInfoConfig::get(defaultHwInfo->platform.eProductFamily);
+
+    hwInfo.platform.usRevId = hwInfoConfig.getHwRevIdFromStepping(REVISION_A0, hwInfo);
+    EXPECT_EQ(LocalMemoryAccessMode::CpuAccessDisallowed, hwInfoConfig.getLocalMemoryAccessMode(hwInfo));
+
+    hwInfo.platform.usRevId = hwInfoConfig.getHwRevIdFromStepping(REVISION_B, hwInfo);
+    EXPECT_EQ(LocalMemoryAccessMode::Default, hwInfoConfig.getLocalMemoryAccessMode(hwInfo));
+}

shared/test/common/xe_hpg_core/excludes_xe_hpg_core.cpp

@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "test.h"
+
+HWTEST_EXCLUDE_PRODUCT(CommandEncodeStatesTest, givenEventAddressWhenEncodeThenMocsFromGmmHelperIsSet, IGFX_XE_HPG_CORE);

shared/test/common/xe_hpg_core/image_surface_state_tests_xe_hpg_core.cpp

@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "shared/test/unit_test/image/image_surface_state_fixture.h"
+
+using namespace NEO;
+
+using ImageSurfaceStateTestsXeHpgCore = ImageSurfaceStateTests;
+
+XE_HPG_CORETEST_F(ImageSurfaceStateTestsXeHpgCore, givenGmmWithMediaCompressedWhenSetFlagsForMediaCompressionThenAuxiliarySurfaceNoneIsSetAndMemoryCompressionEnable) {
+    auto size = sizeof(typename FamilyType::RENDER_SURFACE_STATE);
+    auto surfaceState = std::make_unique<char[]>(size);
+    auto castSurfaceState = reinterpret_cast<typename FamilyType::RENDER_SURFACE_STATE *>(surfaceState.get());
+    castSurfaceState->setAuxiliarySurfaceMode(FamilyType::RENDER_SURFACE_STATE::AUXILIARY_SURFACE_MODE::AUXILIARY_SURFACE_MODE_AUX_CCS_E);
+
+    mockGmm->gmmResourceInfo->getResourceFlags()->Info.MediaCompressed = false;
+    EncodeSurfaceState<FamilyType>::setFlagsForMediaCompression(castSurfaceState, mockGmm.get());
+    EXPECT_EQ(castSurfaceState->getAuxiliarySurfaceMode(), FamilyType::RENDER_SURFACE_STATE::AUXILIARY_SURFACE_MODE::AUXILIARY_SURFACE_MODE_AUX_CCS_E);
+    EXPECT_EQ(castSurfaceState->getMemoryCompressionEnable(), false);
+    mockGmm->gmmResourceInfo->getResourceFlags()->Info.MediaCompressed = true;
+    EncodeSurfaceState<FamilyType>::setFlagsForMediaCompression(castSurfaceState, mockGmm.get());
+    EXPECT_EQ(castSurfaceState->getAuxiliarySurfaceMode(), FamilyType::RENDER_SURFACE_STATE::AUXILIARY_SURFACE_MODE::AUXILIARY_SURFACE_MODE_AUX_NONE);
+    EXPECT_EQ(castSurfaceState->getMemoryCompressionEnable(), true);
+}
+
+XE_HPG_CORETEST_F(ImageSurfaceStateTestsXeHpgCore, givenGmmWhenSetClearColorParamsThenClearValueAddressEnable) {
+    auto size = sizeof(typename FamilyType::RENDER_SURFACE_STATE);
+    auto surfaceState = std::make_unique<char[]>(size);
+    auto castSurfaceState = reinterpret_cast<typename FamilyType::RENDER_SURFACE_STATE *>(surfaceState.get());
+
+    mockGmm->gmmResourceInfo->getResourceFlags()->Gpu.IndirectClearColor = true;
+    EncodeSurfaceState<FamilyType>::setClearColorParams(castSurfaceState, mockGmm.get());
+    EXPECT_EQ(castSurfaceState->getClearValueAddressEnable(), true);
+}
+
+XE_HPG_CORETEST_F(ImageSurfaceStateTestsXeHpgCore, givenGmmWithMediaCompressedWhenSetMipTailStartLodThenMipTailStartLodIsSet) {
+    auto size = sizeof(typename FamilyType::RENDER_SURFACE_STATE);
+    auto surfaceState = std::make_unique<char[]>(size);
+    auto castSurfaceState = reinterpret_cast<typename FamilyType::RENDER_SURFACE_STATE *>(surfaceState.get());
+
+    setMipTailStartLod<FamilyType>(castSurfaceState, nullptr);
+
+    EXPECT_EQ(castSurfaceState->getMipTailStartLod(), 0u);
+
+    setMipTailStartLod<FamilyType>(castSurfaceState, mockGmm.get());
+
+    EXPECT_EQ(castSurfaceState->getMipTailStartLod(), mockGmm->gmmResourceInfo->getMipTailStartLodSurfaceState());
+}

shared/test/common/xe_hpg_core/simd_helper_tests_xe_hpg_core.cpp

@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "shared/test/common/helpers/simd_helper_tests.inl"
+
+using namespace NEO;
+
+using TestSimdConfigSet = ::testing::Test;
+
+XE_HPG_CORETEST_F(TestSimdConfigSet, GivenSimdSizeWhenGetSimdConfigCalledThenCorrectEnumReturnedXeHpgCore) {
+    GivenSimdSizeWhenGetSimdConfigCalledThenCorrectEnumReturned<typename FamilyType::COMPUTE_WALKER>::TestBodyImpl();
+}

shared/test/common/xe_hpg_core/test_preemption_xe_hpg_core.cpp

@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "shared/source/helpers/hw_helper.h"
+#include "shared/test/common/fixtures/preemption_fixture.h"
+
+using namespace NEO;
+
+template <>
+PreemptionTestHwDetails GetPreemptionTestHwDetails<XE_HPG_COREFamily>() {
+    PreemptionTestHwDetails ret;
+    ret.modeToRegValueMap[PreemptionMode::ThreadGroup] = DwordBuilder::build(1, true) | DwordBuilder::build(2, true, false);
+    ret.modeToRegValueMap[PreemptionMode::MidBatch] = DwordBuilder::build(2, true) | DwordBuilder::build(1, true, false);
+    ret.modeToRegValueMap[PreemptionMode::MidThread] = DwordBuilder::build(2, true, false) | DwordBuilder::build(1, true, false);
+    ret.defaultRegValue = ret.modeToRegValueMap[PreemptionMode::MidBatch];
+    ret.regAddress = 0x2580u;
+    return ret;
+}

shared/test/common/xe_hpg_core/test_traits_xe_hpg_core.h

@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#pragma once
+#include "shared/test/common/helpers/test_traits.h"
+
+template <>
+struct TestTraits<IGFX_XE_HPG_CORE> {
+    static constexpr bool surfaceStateCompressionParamsSupported = true;
+    static constexpr bool clearColorAddressMatcher = true;
+    static constexpr bool auxBuiltinsSupported = true;
+    static constexpr bool localMemCompressionAubsSupported = true;
+    static constexpr bool systemMemCompressionAubsSupported = false;
+    static constexpr bool l3ControlSupported = true;
+    static constexpr bool forceNonCoherentSupported = true;
+    static constexpr bool threadPreemptionDisableBitMatcher = true;
+    static constexpr bool programOnlyChangedFieldsInComputeStateMode = true;
+    static constexpr bool iohInSbaSupported = false;
+    static constexpr bool auxTranslationSupported = true;
+    static constexpr bool deviceEnqueueSupport = false;
+};

shared/test/common/xe_hpg_core/unit_test_helper_xe_hpg_core.cpp

@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "shared/source/xe_hpg_core/hw_info.h"
+#include "shared/test/common/helpers/unit_test_helper.h"
+#include "shared/test/common/helpers/unit_test_helper.inl"
+using Family = NEO::XE_HPG_COREFamily;
+#include "shared/test/common/helpers/unit_test_helper_xehp_and_later.inl"
+
+namespace NEO {
+template <>
+const AuxTranslationMode UnitTestHelper<Family>::requiredAuxTranslationMode = AuxTranslationMode::Blit;
+
+template <>
+const bool UnitTestHelper<Family>::additionalMiFlushDwRequired = true;
+
+template <>
+uint32_t UnitTestHelper<Family>::getDebugModeRegisterOffset() {
+    return 0x20d8;
+}
+
+template <>
+uint32_t UnitTestHelper<Family>::getDebugModeRegisterValue() {
+    return (1u << 5) | (1u << 21);
+}
+
+template <>
+uint32_t UnitTestHelper<Family>::getTdCtlRegisterOffset() {
+    return 0xe400;
+}
+
+template <>
+uint32_t UnitTestHelper<Family>::getTdCtlRegisterValue() {
+    return (1u << 7) | (1u << 4) | (1u << 2) | (1u << 0);
+}
+
+template struct UnitTestHelper<Family>;
+} // namespace NEO