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Use single class to program load register command

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Change-Id: I90fe084409588cb32f0ac43a3db5082047d7a68b
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
This commit is contained in:
Zbigniew Zdanowicz
2020-10-06 10:58:18 +02:00
committed by sys_ocldev
parent 138f04bdcd
commit ce1b669cda
12 changed files with 66 additions and 71 deletions
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10
opencl/source/command_queue/gpgpu_walker_base.inl
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@ -53,12 +53,10 @@ void GpgpuWalkerHelper<GfxFamily>::addAluReadModifyWriteRegister(
*pCmd = cmdReg;
// Load "Mask" into CS_GPR_R1
typedef typename GfxFamily::MI_LOAD_REGISTER_IMM MI_LOAD_REGISTER_IMM;
auto pCmd2 = pCommandStream->getSpaceForCmd<MI_LOAD_REGISTER_IMM>();
MI_LOAD_REGISTER_IMM cmdImm = GfxFamily::cmdInitLoadRegisterImm;
cmdImm.setRegisterOffset(CS_GPR_R1);
cmdImm.setDataDword(mask);
*pCmd2 = cmdImm;
LriHelper<GfxFamily>::program(pCommandStream,
CS_GPR_R1,
mask,
false);
// Add instruction MI_MATH with 4 MI_MATH_ALU_INST_INLINE operands
auto pCmd3 = reinterpret_cast<uint32_t *>(pCommandStream->getSpace(sizeof(MI_MATH) + NUM_ALU_INST_FOR_READ_MODIFY_WRITE * sizeof(MI_MATH_ALU_INST_INLINE)));

20
opencl/source/device_queue/device_queue_hw_base.inl
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@ -202,14 +202,18 @@ size_t DeviceQueueHw<GfxFamily>::getCSPrefetchSize() {
template <typename GfxFamily>
void DeviceQueueHw<GfxFamily>::addLriCmd(bool setArbCheck) {
using MI_LOAD_REGISTER_IMM = typename GfxFamily::MI_LOAD_REGISTER_IMM;
auto lri = slbCS.getSpaceForCmd<MI_LOAD_REGISTER_IMM>();
*lri = GfxFamily::cmdInitLoadRegisterImm;
lri->setRegisterOffset(0x2248); // CTXT_PREMP_DBG offset
if (setArbCheck)
lri->setDataDword(0x00000100); // set only bit 8 (Preempt On MI_ARB_CHK Only)
else
lri->setDataDword(0x0);
// CTXT_PREMP_DBG offset
constexpr uint32_t registerAddress = 0x2248u;
uint32_t value = 0u;
if (setArbCheck) {
// set only bit 8 (Preempt On MI_ARB_CHK Only)
value = 0x00000100;
}
LriHelper<GfxFamily>::program(&slbCS,
registerAddress,
value,
false);
}
template <typename GfxFamily>

19
opencl/source/gen8/device_queue_gen8.cpp
View File

@ -42,13 +42,18 @@ void DeviceQueueHw<Family>::addMiAtomicCmdWa(uint64_t atomicOpPlaceholder) {
template <>
void DeviceQueueHw<Family>::addLriCmdWa(bool setArbCheck) {
auto lri = slbCS.getSpaceForCmd<Family::MI_LOAD_REGISTER_IMM>();
*lri = Family::cmdInitLoadRegisterImm;
lri->setRegisterOffset(0x2248); // CTXT_PREMP_DBG offset
if (setArbCheck)
lri->setDataDword(0x00000100); // set only bit 8 (Preempt On MI_ARB_CHK Only)
else
lri->setDataDword(0x0);
// CTXT_PREMP_DBG offset
constexpr uint32_t registerAddress = 0x2248u;
uint32_t value = 0u;
if (setArbCheck) {
// set only bit 8 (Preempt On MI_ARB_CHK Only)
value = 0x00000100;
}
LriHelper<Family>::program(&slbCS,
registerAddress,
value,
false);
}
template <>