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build: update upstream kernel headers to v6.12 

Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
This commit is contained in:
Mateusz Jablonski 2024-11-18 10:07:24 +00:00 committed by Compute-Runtime-Automation
parent fe23e7fa40
commit ced84fbb2e
4 changed files with 37 additions and 2 deletions
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2
third_party/uapi/upstream/.version vendored
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@ -1,2 +1,2 @@
git_revision: v6.11
git_revision: v6.12
git_url: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/

25
third_party/uapi/upstream/drm/drm_fourcc.h vendored
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@ -702,6 +702,31 @@ extern "C" {
*/
#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)
/*
* Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression
* on integrated graphics
*
* The main surface is Tile 4 and at plane index 0. For semi-planar formats
* like NV12, the Y and UV planes are Tile 4 and are located at plane indices
* 0 and 1, respectively. The CCS for all planes are stored outside of the
* GEM object in a reserved memory area dedicated for the storage of the
* CCS data for all compressible GEM objects.
*/
#define I915_FORMAT_MOD_4_TILED_LNL_CCS fourcc_mod_code(INTEL, 16)
/*
* Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression
* on discrete graphics
*
* The main surface is Tile 4 and at plane index 0. For semi-planar formats
* like NV12, the Y and UV planes are Tile 4 and are located at plane indices
* 0 and 1, respectively. The CCS for all planes are stored outside of the
* GEM object in a reserved memory area dedicated for the storage of the
* CCS data for all compressible GEM objects. The GEM object must be stored in
* contiguous memory with a size aligned to 64KB
*/
#define I915_FORMAT_MOD_4_TILED_BMG_CCS fourcc_mod_code(INTEL, 17)
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*

2
third_party/uapi/upstream/drm/drm_mode.h vendored
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@ -859,6 +859,8 @@ struct drm_color_lut {
/**
* struct drm_plane_size_hint - Plane size hints
* @width: The width of the plane in pixel
* @height: The height of the plane in pixel
*
* The plane SIZE_HINTS property blob contains an
* array of struct drm_plane_size_hint.

10
third_party/uapi/upstream/xe/xe_drm.h vendored
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@ -517,7 +517,14 @@ struct drm_xe_query_gt_list {
* available per Dual Sub Slices (DSS). For example a query response
* containing the following in mask:
* ``EU_PER_DSS ff ff 00 00 00 00 00 00``
* means each DSS has 16 EU.
* means each DSS has 16 SIMD8 EUs. This type may be omitted if device
* doesn't have SIMD8 EUs.
* - %DRM_XE_TOPO_SIMD16_EU_PER_DSS - To query the mask of SIMD16 Execution
* Units (EU) available per Dual Sub Slices (DSS). For example a query
* response containing the following in mask:
* ``SIMD16_EU_PER_DSS ff ff 00 00 00 00 00 00``
* means each DSS has 16 SIMD16 EUs. This type may be omitted if device
* doesn't have SIMD16 EUs.
*/
struct drm_xe_query_topology_mask {
/** @gt_id: GT ID the mask is associated with */
@ -527,6 +534,7 @@ struct drm_xe_query_topology_mask {
#define DRM_XE_TOPO_DSS_COMPUTE 2
#define DRM_XE_TOPO_L3_BANK 3
#define DRM_XE_TOPO_EU_PER_DSS 4
#define DRM_XE_TOPO_SIMD16_EU_PER_DSS 5
/** @type: type of mask */
__u16 type;