mirror of
https://github.com/intel/compute-runtime.git
synced 2025-09-15 13:01:45 +08:00
Reorganization directory structure [3/n]
Change-Id: If3dfa3f6007f8810a6a1ae1a4f0c7da38544648d
This commit is contained in:
21
shared/source/sku_info/CMakeLists.txt
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21
shared/source/sku_info/CMakeLists.txt
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#
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# Copyright (C) 2019-2020 Intel Corporation
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#
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# SPDX-License-Identifier: MIT
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#
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set(NEO_CORE_SKU_INFO_BASE
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${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
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${CMAKE_CURRENT_SOURCE_DIR}/sku_info_base.h
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${CMAKE_CURRENT_SOURCE_DIR}/operations/sku_info_transfer.h
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${CMAKE_CURRENT_SOURCE_DIR}/definitions${BRANCH_DIR_SUFFIX}/sku_info.h
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${CMAKE_CURRENT_SOURCE_DIR}/operations${BRANCH_DIR_SUFFIX}/sku_info_transfer.cpp
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)
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set(NEO_CORE_SKU_INFO_WINDOWS
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${CMAKE_CURRENT_SOURCE_DIR}/operations/windows/sku_info_receiver.h
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${CMAKE_CURRENT_SOURCE_DIR}/operations/windows${BRANCH_DIR_SUFFIX}/sku_info_receiver.cpp
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)
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set_property(GLOBAL PROPERTY NEO_CORE_SKU_INFO_BASE ${NEO_CORE_SKU_INFO_BASE})
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set_property(GLOBAL PROPERTY NEO_CORE_SKU_INFO_WINDOWS ${NEO_CORE_SKU_INFO_WINDOWS})
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15
shared/source/sku_info/definitions/sku_info.h
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15
shared/source/sku_info/definitions/sku_info.h
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/*
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* Copyright (C) 2018-2020 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#pragma once
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#include "sku_info/sku_info_base.h"
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namespace NEO {
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struct FeatureTable : FeatureTableBase {};
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struct WorkaroundTable : WorkaroundTableBase {};
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} // namespace NEO
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18
shared/source/sku_info/operations/sku_info_transfer.cpp
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18
shared/source/sku_info/operations/sku_info_transfer.cpp
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/*
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* Copyright (C) 2018-2020 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#include "sku_info/operations/sku_info_transfer.h"
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namespace NEO {
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void SkuInfoTransfer::transferWaTableForGmm(_WA_TABLE *dstWaTable, const NEO::WorkaroundTable *srcWaTable) {
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transferWaTableForGmmBase(dstWaTable, srcWaTable);
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}
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void SkuInfoTransfer::transferFtrTableForGmm(_SKU_FEATURE_TABLE *dstFtrTable, const NEO::FeatureTable *srcFtrTable) {
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transferFtrTableForGmmBase(dstFtrTable, srcFtrTable);
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}
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} // namespace NEO
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65
shared/source/sku_info/operations/sku_info_transfer.h
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65
shared/source/sku_info/operations/sku_info_transfer.h
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/*
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* Copyright (C) 2018-2020 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#pragma once
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#include "gmm_helper/gmm_lib.h"
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#include "sku_info/operations/sku_info_transfer.h"
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#include "sku_info.h"
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namespace NEO {
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class SkuInfoTransfer {
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public:
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static void transferFtrTableForGmm(_SKU_FEATURE_TABLE *dstFtrTable, const FeatureTable *srcFtrTable);
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static void transferWaTableForGmm(_WA_TABLE *dstWaTable, const WorkaroundTable *srcWaTable);
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protected:
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static void transferFtrTableForGmmBase(_SKU_FEATURE_TABLE *dstFtrTable, const NEO::FeatureTable *srcFtrTable) {
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#define TRANSFER_FTR_TO_GMM(VAL_NAME) dstFtrTable->Ftr##VAL_NAME = srcFtrTable->ftr##VAL_NAME
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TRANSFER_FTR_TO_GMM(StandardMipTailFormat);
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TRANSFER_FTR_TO_GMM(ULT);
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TRANSFER_FTR_TO_GMM(EDram);
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TRANSFER_FTR_TO_GMM(FrameBufferLLC);
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TRANSFER_FTR_TO_GMM(Crystalwell);
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TRANSFER_FTR_TO_GMM(DisplayEngineS3d);
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TRANSFER_FTR_TO_GMM(TileY);
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TRANSFER_FTR_TO_GMM(DisplayYTiling);
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TRANSFER_FTR_TO_GMM(Fbc);
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TRANSFER_FTR_TO_GMM(VERing);
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TRANSFER_FTR_TO_GMM(Vcs2);
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TRANSFER_FTR_TO_GMM(LCIA);
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TRANSFER_FTR_TO_GMM(IA32eGfxPTEs);
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TRANSFER_FTR_TO_GMM(Wddm2GpuMmu);
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TRANSFER_FTR_TO_GMM(Wddm2_1_64kbPages);
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TRANSFER_FTR_TO_GMM(TranslationTable);
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TRANSFER_FTR_TO_GMM(UserModeTranslationTable);
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TRANSFER_FTR_TO_GMM(Wddm2Svm);
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TRANSFER_FTR_TO_GMM(LLCBypass);
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TRANSFER_FTR_TO_GMM(E2ECompression);
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TRANSFER_FTR_TO_GMM(LinearCCS);
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TRANSFER_FTR_TO_GMM(CCSRing);
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TRANSFER_FTR_TO_GMM(CCSNode);
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TRANSFER_FTR_TO_GMM(MemTypeMocsDeferPAT);
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#undef TRANSFER_FTR_TO_GMM
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}
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static void transferWaTableForGmmBase(_WA_TABLE *dstWaTable, const NEO::WorkaroundTable *srcWaTable) {
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#define TRANSFER_WA_TO_GMM(VAL_NAME) dstWaTable->Wa##VAL_NAME = srcWaTable->wa##VAL_NAME
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TRANSFER_WA_TO_GMM(FbcLinearSurfaceStride);
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TRANSFER_WA_TO_GMM(DisableEdramForDisplayRT);
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TRANSFER_WA_TO_GMM(EncryptedEdramOnlyPartials);
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TRANSFER_WA_TO_GMM(LosslessCompressionSurfaceStride);
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TRANSFER_WA_TO_GMM(RestrictPitch128KB);
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TRANSFER_WA_TO_GMM(AuxTable16KGranular);
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TRANSFER_WA_TO_GMM(Limit128BMediaCompr);
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TRANSFER_WA_TO_GMM(UntypedBufferCompression);
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#undef TRANSFER_WA_TO_GMM
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}
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};
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} // namespace NEO
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@ -0,0 +1,18 @@
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/*
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* Copyright (C) 2018-2020 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#include "sku_info/operations/windows/sku_info_receiver.h"
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namespace NEO {
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void SkuInfoReceiver::receiveFtrTableFromAdapterInfo(FeatureTable *ftrTable, _ADAPTER_INFO *adapterInfo) {
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receiveFtrTableFromAdapterInfoBase(ftrTable, adapterInfo);
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}
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void SkuInfoReceiver::receiveWaTableFromAdapterInfo(WorkaroundTable *workaroundTable, _ADAPTER_INFO *adapterInfo) {
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receiveWaTableFromAdapterInfoBase(workaroundTable, adapterInfo);
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}
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} // namespace NEO
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137
shared/source/sku_info/operations/windows/sku_info_receiver.h
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137
shared/source/sku_info/operations/windows/sku_info_receiver.h
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/*
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* Copyright (C) 2018-2020 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#pragma once
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#include "os_interface/windows/windows_wrapper.h"
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#include "sku_info.h"
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#include "umKmInc/sharedata.h"
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namespace NEO {
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class SkuInfoReceiver {
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public:
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static void receiveFtrTableFromAdapterInfo(FeatureTable *ftrTable, _ADAPTER_INFO *adapterInfo);
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static void receiveWaTableFromAdapterInfo(WorkaroundTable *workaroundTable, _ADAPTER_INFO *adapterInfo);
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protected:
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static void receiveFtrTableFromAdapterInfoBase(FeatureTable *ftrTable, _ADAPTER_INFO *adapterInfo) {
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#define RECEIVE_FTR(VAL_NAME) ftrTable->ftr##VAL_NAME = adapterInfo->SkuTable.Ftr##VAL_NAME
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RECEIVE_FTR(Desktop);
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RECEIVE_FTR(ChannelSwizzlingXOREnabled);
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RECEIVE_FTR(GtBigDie);
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RECEIVE_FTR(GtMediumDie);
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RECEIVE_FTR(GtSmallDie);
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RECEIVE_FTR(GT1);
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RECEIVE_FTR(GT1_5);
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RECEIVE_FTR(GT2);
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RECEIVE_FTR(GT2_5);
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RECEIVE_FTR(GT3);
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RECEIVE_FTR(GT4);
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RECEIVE_FTR(IVBM0M1Platform);
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RECEIVE_FTR(SGTPVSKUStrapPresent);
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RECEIVE_FTR(GTA);
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RECEIVE_FTR(GTC);
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RECEIVE_FTR(GTX);
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RECEIVE_FTR(5Slice);
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RECEIVE_FTR(GpGpuMidBatchPreempt);
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RECEIVE_FTR(GpGpuThreadGroupLevelPreempt);
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RECEIVE_FTR(GpGpuMidThreadLevelPreempt);
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RECEIVE_FTR(IoMmuPageFaulting);
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RECEIVE_FTR(Wddm2Svm);
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RECEIVE_FTR(PooledEuEnabled);
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RECEIVE_FTR(ResourceStreamer);
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RECEIVE_FTR(PPGTT);
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RECEIVE_FTR(SVM);
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RECEIVE_FTR(EDram);
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RECEIVE_FTR(L3IACoherency);
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RECEIVE_FTR(IA32eGfxPTEs);
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RECEIVE_FTR(3dMidBatchPreempt);
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RECEIVE_FTR(3dObjectLevelPreempt);
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RECEIVE_FTR(PerCtxtPreemptionGranularityControl);
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RECEIVE_FTR(TileY);
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RECEIVE_FTR(DisplayYTiling);
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RECEIVE_FTR(TranslationTable);
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RECEIVE_FTR(UserModeTranslationTable);
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RECEIVE_FTR(EnableGuC);
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RECEIVE_FTR(Fbc);
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RECEIVE_FTR(Fbc2AddressTranslation);
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RECEIVE_FTR(FbcBlitterTracking);
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RECEIVE_FTR(FbcCpuTracking);
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RECEIVE_FTR(Vcs2);
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RECEIVE_FTR(VEBOX);
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RECEIVE_FTR(SingleVeboxSlice);
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RECEIVE_FTR(ULT);
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RECEIVE_FTR(LCIA);
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RECEIVE_FTR(GttCacheInvalidation);
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RECEIVE_FTR(TileMappedResource);
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RECEIVE_FTR(AstcHdr2D);
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RECEIVE_FTR(AstcLdr2D);
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RECEIVE_FTR(StandardMipTailFormat);
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RECEIVE_FTR(FrameBufferLLC);
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RECEIVE_FTR(Crystalwell);
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RECEIVE_FTR(LLCBypass);
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RECEIVE_FTR(DisplayEngineS3d);
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RECEIVE_FTR(VERing);
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RECEIVE_FTR(Wddm2GpuMmu);
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RECEIVE_FTR(Wddm2_1_64kbPages);
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RECEIVE_FTR(KmdDaf);
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RECEIVE_FTR(SimulationMode);
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RECEIVE_FTR(E2ECompression);
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RECEIVE_FTR(LinearCCS);
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RECEIVE_FTR(CCSRing);
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RECEIVE_FTR(CCSNode);
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RECEIVE_FTR(MemTypeMocsDeferPAT);
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#undef RECEIVE_FTR
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}
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static void receiveWaTableFromAdapterInfoBase(WorkaroundTable *workaroundTable, _ADAPTER_INFO *adapterInfo) {
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#define RECEIVE_WA(VAL_NAME) workaroundTable->wa##VAL_NAME = adapterInfo->WaTable.Wa##VAL_NAME
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RECEIVE_WA(DoNotUseMIReportPerfCount);
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RECEIVE_WA(EnablePreemptionGranularityControlByUMD);
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RECEIVE_WA(SendMIFLUSHBeforeVFE);
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RECEIVE_WA(ReportPerfCountUseGlobalContextID);
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RECEIVE_WA(DisableLSQCROPERFforOCL);
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RECEIVE_WA(Msaa8xTileYDepthPitchAlignment);
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RECEIVE_WA(LosslessCompressionSurfaceStride);
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RECEIVE_WA(FbcLinearSurfaceStride);
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RECEIVE_WA(4kAlignUVOffsetNV12LinearSurface);
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RECEIVE_WA(EncryptedEdramOnlyPartials);
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RECEIVE_WA(DisableEdramForDisplayRT);
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RECEIVE_WA(ForcePcBbFullCfgRestore);
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RECEIVE_WA(CompressedResourceRequiresConstVA21);
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RECEIVE_WA(DisablePerCtxtPreemptionGranularityControl);
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RECEIVE_WA(LLCCachingUnsupported);
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RECEIVE_WA(UseVAlign16OnTileXYBpp816);
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RECEIVE_WA(ModifyVFEStateAfterGPGPUPreemption);
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RECEIVE_WA(CSRUncachable);
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RECEIVE_WA(SamplerCacheFlushBetweenRedescribedSurfaceReads);
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RECEIVE_WA(RestrictPitch128KB);
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RECEIVE_WA(AuxTable16KGranular);
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RECEIVE_WA(Limit128BMediaCompr);
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RECEIVE_WA(UntypedBufferCompression);
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RECEIVE_WA(DisableFusedThreadScheduling);
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#undef RECEIVE_WA
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}
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};
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} // namespace NEO
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122
shared/source/sku_info/sku_info_base.h
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122
shared/source/sku_info/sku_info_base.h
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/*
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* Copyright (C) 2018-2020 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#pragma once
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namespace NEO {
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struct FeatureTableBase {
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bool ftrDesktop = false;
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bool ftrChannelSwizzlingXOREnabled = false;
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bool ftrGtBigDie = false;
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bool ftrGtMediumDie = false;
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bool ftrGtSmallDie = false;
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bool ftrGT1 = false;
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bool ftrGT1_5 = false;
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bool ftrGT2 = false;
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bool ftrGT2_5 = false;
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bool ftrGT3 = false;
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bool ftrGT4 = false;
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bool ftrIVBM0M1Platform = false;
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bool ftrSGTPVSKUStrapPresent = false;
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bool ftrGTA = false;
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bool ftrGTC = false;
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bool ftrGTX = false;
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bool ftr5Slice = false;
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bool ftrGpGpuMidBatchPreempt = false;
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bool ftrGpGpuThreadGroupLevelPreempt = false;
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bool ftrGpGpuMidThreadLevelPreempt = false;
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bool ftrIoMmuPageFaulting = false;
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bool ftrWddm2Svm = false;
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bool ftrPooledEuEnabled = false;
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bool ftrResourceStreamer = false;
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bool ftrPPGTT = false;
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bool ftrSVM = false;
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bool ftrEDram = false;
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bool ftrL3IACoherency = false;
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bool ftrIA32eGfxPTEs = false;
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bool ftr3dMidBatchPreempt = false;
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bool ftr3dObjectLevelPreempt = false;
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bool ftrPerCtxtPreemptionGranularityControl = false;
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bool ftrTileY = false;
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bool ftrDisplayYTiling = false;
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bool ftrTranslationTable = false;
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bool ftrUserModeTranslationTable = false;
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bool ftrEnableGuC = false;
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bool ftrFbc = false;
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bool ftrFbc2AddressTranslation = false;
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bool ftrFbcBlitterTracking = false;
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bool ftrFbcCpuTracking = false;
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bool ftrVcs2 = false;
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bool ftrVEBOX = false;
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bool ftrSingleVeboxSlice = false;
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bool ftrULT = false;
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bool ftrLCIA = false;
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bool ftrGttCacheInvalidation = false;
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bool ftrTileMappedResource = false;
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bool ftrAstcHdr2D = false;
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bool ftrAstcLdr2D = false;
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bool ftrStandardMipTailFormat = false;
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bool ftrFrameBufferLLC = false;
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bool ftrCrystalwell = false;
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bool ftrLLCBypass = false;
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bool ftrDisplayEngineS3d = false;
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bool ftrVERing = false;
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bool ftrWddm2GpuMmu = false;
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bool ftrWddm2_1_64kbPages = false;
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bool ftrWddmHwQueues = false;
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bool ftrMemTypeMocsDeferPAT = false;
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bool ftrKmdDaf = false;
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bool ftrSimulationMode = false;
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bool ftrE2ECompression = false;
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bool ftrLinearCCS = false;
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bool ftrCCSRing = false;
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bool ftrCCSNode = false;
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};
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struct WorkaroundTableBase {
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bool waDoNotUseMIReportPerfCount = false;
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bool waEnablePreemptionGranularityControlByUMD = false;
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bool waSendMIFLUSHBeforeVFE = false;
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bool waReportPerfCountUseGlobalContextID = false;
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bool waDisableLSQCROPERFforOCL = false;
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bool waMsaa8xTileYDepthPitchAlignment = false;
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bool waLosslessCompressionSurfaceStride = false;
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bool waFbcLinearSurfaceStride = false;
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bool wa4kAlignUVOffsetNV12LinearSurface = false;
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bool waEncryptedEdramOnlyPartials = false;
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bool waDisableEdramForDisplayRT = false;
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bool waForcePcBbFullCfgRestore = false;
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bool waCompressedResourceRequiresConstVA21 = false;
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bool waDisablePerCtxtPreemptionGranularityControl = false;
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bool waLLCCachingUnsupported = false;
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bool waUseVAlign16OnTileXYBpp816 = false;
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bool waModifyVFEStateAfterGPGPUPreemption = false;
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bool waCSRUncachable = false;
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bool waSamplerCacheFlushBetweenRedescribedSurfaceReads = false;
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bool waRestrictPitch128KB = false;
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bool waLimit128BMediaCompr = false;
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bool waUntypedBufferCompression = false;
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bool waAuxTable16KGranular = false;
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bool waDisableFusedThreadScheduling = false;
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};
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} // namespace NEO
|
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