From ff7882bcbefe41becae61e492245698c267389eb Mon Sep 17 00:00:00 2001 From: Krzysztof Gibala Date: Fri, 4 Feb 2022 15:43:17 +0000 Subject: [PATCH] Add PC before NP state commands Add pipe control before state base address, state compute mode and state sip commands on DG2 and PVC when CCS flow is used. Signed-off-by: Krzysztof Gibala --- ...ceiver_flush_task_tests_xehp_and_later.cpp | 47 +++++++++- ...stream_receiver_hw_tests_dg2_and_later.cpp | 37 +++++++- .../os_interface/hw_info_config_tests.cpp | 4 +- .../xehp/test_hw_info_config_xehp.inl | 17 +++- .../xe_hpc_core/excludes_xe_hpc_core.cpp | 2 +- .../pvc/test_hw_info_config_pvc.cpp | 12 ++- .../xe_hpg_core/dg2/excludes_dg2.cpp | 1 + ...mmand_stream_receiver_hw_dg2_and_later.inl | 12 ++- ...and_stream_receiver_hw_tgllp_and_later.inl | 7 +- ...mand_stream_receiver_hw_xehp_and_later.inl | 19 ++-- .../preemption_xehp_and_later.inl | 7 +- shared/source/os_interface/hw_info_config.h | 4 +- shared/source/os_interface/hw_info_config.inl | 4 +- .../os_agnostic_hw_info_config_xe_hp_core.inl | 11 +-- .../os_agnostic_hw_info_config_pvc.inl | 11 +-- .../os_agnostic_hw_info_config_dg2.inl | 11 +-- .../test/common/mocks/mock_hw_info_config.cpp | 4 +- .../test_macros/header/common_matchers.h | 1 + .../common/xe_hpg_core/dg2/excludes_dg2.cpp | 2 +- .../xe_hpg_core/excludes_xe_hpg_core.cpp | 6 +- .../compute_mode_tests_xehp_and_later.cpp | 68 ++++++++++++++ .../compute_mode_tests_xe_hp_core.cpp | 16 ++-- .../compute_mode_tests_xe_hpc_core.cpp | 61 +++++++++++-- .../compute_mode_tests_xe_hpg_core.cpp | 89 ++++++++++++++++++- .../dg2/compute_mode_tests_dg2.cpp | 68 ++++++++++++-- .../dg2/hw_info_config_tests_dg2.cpp | 49 ++++++++-- 26 files changed, 492 insertions(+), 78 deletions(-) diff --git a/opencl/test/unit_test/command_stream/command_stream_receiver_flush_task_tests_xehp_and_later.cpp b/opencl/test/unit_test/command_stream/command_stream_receiver_flush_task_tests_xehp_and_later.cpp index 3b6fa42ede..c2aa2375db 100644 --- a/opencl/test/unit_test/command_stream/command_stream_receiver_flush_task_tests_xehp_and_later.cpp +++ b/opencl/test/unit_test/command_stream/command_stream_receiver_flush_task_tests_xehp_and_later.cpp @@ -137,10 +137,13 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, CommandStreamReceiverFlushTaskXeHPAndLaterTests, gi auto &commandStreamReceiver = pDevice->getUltCommandStreamReceiver(); configureCSRtoNonDirtyState(false); - ioh.replaceBuffer(ptrOffset(ioh.getCpuBase(), +1u), ioh.getMaxAvailableSpace() + MemoryConstants::pageSize * 3); flushTask(commandStreamReceiver); parseCommands(commandStreamReceiver.getCS(0)); + auto requiredCmdSize = PreemptionHelper::getRequiredStateSipCmdSize(*pDevice, false); + auto cmdSize = sizeof(STATE_SIP) + sizeof(PIPE_CONTROL); + EXPECT_EQ(cmdSize, requiredCmdSize); + auto pipeControlIterator = find(cmdList.begin(), cmdList.end()); auto pipeControlCmd = genCmdCast(*pipeControlIterator); @@ -160,6 +163,48 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, CommandStreamReceiverFlushTaskXeHPAndLaterTests, gi EXPECT_EQ(sipAllocation->getGpuAddressToPatch(), sipCmd->getSystemInstructionPointer()); } +HWTEST2_F(CommandStreamReceiverFlushTaskXeHPAndLaterTests, givenProgramPipeControlPriorToNonPipelinedStateCommandAndStateSipWhenItIsRequiredThenThereIsPipeControlPriorToIt, IsXeHpgCore) { + using STATE_BASE_ADDRESS = typename FamilyType::STATE_BASE_ADDRESS; + using STATE_SIP = typename FamilyType::STATE_SIP; + using PIPE_CONTROL = typename FamilyType::PIPE_CONTROL; + + pDevice->executionEnvironment->rootDeviceEnvironments[0]->debugger.reset(new MockDebugger); + + auto sipType = SipKernel::getSipKernelType(*pDevice); + SipKernel::initSipKernel(sipType, *pDevice); + + auto &commandStreamReceiver = pDevice->getUltCommandStreamReceiver(); + + configureCSRtoNonDirtyState(false); + flushTask(commandStreamReceiver); + parseCommands(commandStreamReceiver.getCS(0)); + + auto requiredCmdSize = PreemptionHelper::getRequiredStateSipCmdSize(*pDevice, false); + auto cmdSize = sizeof(STATE_SIP) + sizeof(PIPE_CONTROL); + EXPECT_EQ(cmdSize, requiredCmdSize); + + // first PC prior SBA + auto pipeControlIterator = find(cmdList.begin(), cmdList.end()); + pipeControlIterator = find(++pipeControlIterator, cmdList.end()); + auto pipeControlCmd = genCmdCast(*pipeControlIterator); + + EXPECT_TRUE(UnitTestHelper::getPipeControlHdcPipelineFlush(*pipeControlCmd)); + EXPECT_TRUE(pipeControlCmd->getUnTypedDataPortCacheFlush()); + + EXPECT_FALSE(pipeControlCmd->getAmfsFlushEnable()); + EXPECT_FALSE(pipeControlCmd->getInstructionCacheInvalidateEnable()); + EXPECT_FALSE(pipeControlCmd->getTextureCacheInvalidationEnable()); + EXPECT_FALSE(pipeControlCmd->getConstantCacheInvalidationEnable()); + EXPECT_FALSE(pipeControlCmd->getStateCacheInvalidationEnable()); + + auto sipIterator = find(cmdList.begin(), cmdList.end()); + auto sipCmd = genCmdCast(*sipIterator); + + auto sipAllocation = SipKernel::getSipKernel(*pDevice).getSipAllocation(); + + EXPECT_EQ(sipAllocation->getGpuAddressToPatch(), sipCmd->getSystemInstructionPointer()); +} + HWTEST2_F(CommandStreamReceiverFlushTaskXeHPAndLaterTests, givenProgramPipeControlPriorToNonPipelinedStateCommandDebugKeyAndStateSipWhenA0SteppingIsActivatedThenOnlyGlobalSipIsProgrammed, IsXEHP) { DebugManagerStateRestore dbgRestorer; DebugManager.flags.ProgramPipeControlPriorToNonPipelinedStateCommand.set(true); diff --git a/opencl/test/unit_test/command_stream/command_stream_receiver_hw_tests_dg2_and_later.cpp b/opencl/test/unit_test/command_stream/command_stream_receiver_hw_tests_dg2_and_later.cpp index 09bb9e2397..6cd3635a0e 100644 --- a/opencl/test/unit_test/command_stream/command_stream_receiver_hw_tests_dg2_and_later.cpp +++ b/opencl/test/unit_test/command_stream/command_stream_receiver_hw_tests_dg2_and_later.cpp @@ -8,7 +8,9 @@ #include "shared/source/helpers/ray_tracing_helper.h" #include "shared/test/common/cmd_parse/hw_parse.h" #include "shared/test/common/helpers/debug_manager_state_restore.h" +#include "shared/test/common/helpers/engine_descriptor_helper.h" #include "shared/test/common/mocks/mock_csr.h" +#include "shared/test/common/mocks/mock_os_context.h" #include "shared/test/common/test_macros/test.h" #include "opencl/test/unit_test/fixtures/cl_device_fixture.h" @@ -60,9 +62,9 @@ HWTEST2_F(CommandStreamReceiverHwTestDg2AndLater, givenGen12AndLaterWhenRayTraci EXPECT_TRUE(commandStreamReceiver.isPerDssBackedBufferSent); } -typedef UltCommandStreamReceiverTest CommandStreamReceiverFlushTasDg2AndLaterTests; +typedef UltCommandStreamReceiverTest CommandStreamReceiverFlushTaskDg2AndLaterTests; -HWTEST2_F(CommandStreamReceiverFlushTasDg2AndLaterTests, givenProgramPipeControlPriorToNonPipelinedStateCommandWhenPerDssBackedBufferThenThereIsPipeControlPriorToIt, MatcherIsRTCapable) { +HWTEST2_F(CommandStreamReceiverFlushTaskDg2AndLaterTests, givenProgramPipeControlPriorToNonPipelinedStateCommandWhenPerDssBackedBufferThenThereIsPipeControlPriorToIt, MatcherIsRTCapable) { DebugManagerStateRestore restore; DebugManager.flags.ProgramPipeControlPriorToNonPipelinedStateCommand.set(true); @@ -139,6 +141,37 @@ HWTEST2_F(CommandStreamReceiverFlushTasDg2AndLaterTests, givenProgramPipeControl EXPECT_EQ(cmdSizeForAllCommandsWithoutPCand3dState + expectedCmdSize, cmdSizeForAllCommands); } +HWTEST2_F(CommandStreamReceiverFlushTaskDg2AndLaterTests, givenSBACommandToProgramOnSingleCCSSetupThenThereIsPipeControlPriorToIt, isXeHpcOrXeHpgCore) { + using STATE_BASE_ADDRESS = typename FamilyType::STATE_BASE_ADDRESS; + using PIPE_CONTROL = typename FamilyType::PIPE_CONTROL; + + hardwareInfo.gtSystemInfo.CCSInfo.NumberOfCCSEnabled = 1; + + auto mockDevice = std::unique_ptr(MockDevice::createWithNewExecutionEnvironment(&hardwareInfo, 0u)); + auto &commandStreamReceiver = mockDevice->getUltCommandStreamReceiver(); + + MockOsContext ccsOsContext(0, EngineDescriptorHelper::getDefaultDescriptor({aub_stream::ENGINE_CCS, EngineUsage::Regular})); + commandStreamReceiver.setupContext(ccsOsContext); + + configureCSRtoNonDirtyState(false); + flushTask(commandStreamReceiver); + parseCommands(commandStreamReceiver.getCS(0)); + + auto stateBaseAddressItor = find(cmdList.begin(), cmdList.end()); + auto pipeControlItor = find(cmdList.begin(), stateBaseAddressItor); + EXPECT_NE(stateBaseAddressItor, pipeControlItor); + + auto pipeControlCmd = reinterpret_cast(*pipeControlItor); + EXPECT_TRUE(UnitTestHelper::getPipeControlHdcPipelineFlush(*pipeControlCmd)); + EXPECT_TRUE(pipeControlCmd->getUnTypedDataPortCacheFlush()); + + EXPECT_FALSE(pipeControlCmd->getAmfsFlushEnable()); + EXPECT_FALSE(pipeControlCmd->getInstructionCacheInvalidateEnable()); + EXPECT_FALSE(pipeControlCmd->getTextureCacheInvalidationEnable()); + EXPECT_FALSE(pipeControlCmd->getConstantCacheInvalidationEnable()); + EXPECT_FALSE(pipeControlCmd->getStateCacheInvalidationEnable()); +} + HWTEST2_F(CommandStreamReceiverHwTestDg2AndLater, givenGen12AndLaterWhenRayTracingEnabledButAlreadySentThenCommandIsNotAddedToBatchBuffer, MatcherIsRTCapable) { using _3DSTATE_BTD = typename FamilyType::_3DSTATE_BTD; MockCsrHw commandStreamReceiver(*pDevice->executionEnvironment, pDevice->getRootDeviceIndex(), pDevice->getDeviceBitfield()); diff --git a/opencl/test/unit_test/os_interface/hw_info_config_tests.cpp b/opencl/test/unit_test/os_interface/hw_info_config_tests.cpp index bf1a5bd46f..b00a94507f 100644 --- a/opencl/test/unit_test/os_interface/hw_info_config_tests.cpp +++ b/opencl/test/unit_test/os_interface/hw_info_config_tests.cpp @@ -316,8 +316,10 @@ HWTEST_F(HwInfoConfigTest, givenHwInfoConfigWhenAskedIfPrefetchDisablingIsRequir HWTEST_F(HwInfoConfigTest, givenHwInfoConfigWhenAskedIfPipeControlPriorToNonPipelinedStateCommandsWARequiredThenFalseIsReturned) { const auto &hwInfoConfig = *HwInfoConfig::get(pInHwInfo.platform.eProductFamily); auto isRcs = false; + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(pInHwInfo, isRcs); - EXPECT_FALSE(hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(pInHwInfo, isRcs)); + EXPECT_FALSE(isWARequiredOnMultiCCS); + EXPECT_FALSE(isWARequiredOnSingleCCS); } HWTEST2_F(HwInfoConfigTest, givenHwInfoConfigWhenAskedIfHeapInLocalMemThenFalseIsReturned, IsAtMostGen12lp) { diff --git a/opencl/test/unit_test/xe_hp_core/xehp/test_hw_info_config_xehp.inl b/opencl/test/unit_test/xe_hp_core/xehp/test_hw_info_config_xehp.inl index bb313a0388..16146ad2dd 100644 --- a/opencl/test/unit_test/xe_hp_core/xehp/test_hw_info_config_xehp.inl +++ b/opencl/test/unit_test/xe_hp_core/xehp/test_hw_info_config_xehp.inl @@ -1,5 +1,5 @@ /* - * Copyright (C) 2021 Intel Corporation + * Copyright (C) 2021-2022 Intel Corporation * * SPDX-License-Identifier: MIT * @@ -121,7 +121,10 @@ XEHPTEST_F(XeHPHwInfoConfig, givenHwInfoConfigWithMultipleCSSWhenIsPipeControlPr hwInfo.gtSystemInfo.CCSInfo.NumberOfCCSEnabled = 2; auto isRcs = false; - EXPECT_TRUE(hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs)); + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs); + + EXPECT_TRUE(isWARequiredOnMultiCCS); + EXPECT_FALSE(isWARequiredOnSingleCCS); } XEHPTEST_F(XeHPHwInfoConfig, givenProgramPipeControlPriorToNonPipelinedStateCommandWhenIsPipeControlPriorToNonPipelinedStateCommandsWARequiredIsCalledThenTrueIsReturned) { @@ -132,7 +135,10 @@ XEHPTEST_F(XeHPHwInfoConfig, givenProgramPipeControlPriorToNonPipelinedStateComm auto hwInfo = *defaultHwInfo; auto isRcs = false; - EXPECT_TRUE(hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs)); + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs); + + EXPECT_TRUE(isWARequiredOnMultiCCS); + EXPECT_FALSE(isWARequiredOnSingleCCS); } XEHPTEST_F(XeHPHwInfoConfig, givenProgramPipeControlPriorToNonPipelinedStateCommandDisabledWhenIsPipeControlPriorToNonPipelinedStateCommandsWARequiredIsCalledThenFalseIsReturned) { @@ -143,5 +149,8 @@ XEHPTEST_F(XeHPHwInfoConfig, givenProgramPipeControlPriorToNonPipelinedStateComm auto hwInfo = *defaultHwInfo; auto isRcs = false; - EXPECT_FALSE(hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs)); + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs); + + EXPECT_FALSE(isWARequiredOnMultiCCS); + EXPECT_FALSE(isWARequiredOnSingleCCS); } diff --git a/opencl/test/unit_test/xe_hpc_core/excludes_xe_hpc_core.cpp b/opencl/test/unit_test/xe_hpc_core/excludes_xe_hpc_core.cpp index 216952c736..fd6724582a 100644 --- a/opencl/test/unit_test/xe_hpc_core/excludes_xe_hpc_core.cpp +++ b/opencl/test/unit_test/xe_hpc_core/excludes_xe_hpc_core.cpp @@ -28,7 +28,7 @@ HWTEST_EXCLUDE_PRODUCT(LocalWorkSizeTest, givenDispatchInfoWhenWorkSizeInfoIsCre HWTEST_EXCLUDE_PRODUCT(HwInfoConfigTest, whenCallingGetDeviceMemoryNameThenDdrIsReturned, IGFX_XE_HPC_CORE); HWTEST_EXCLUDE_PRODUCT(HwInfoConfigTest, givenHardwareInfoWhenCallingIsMaxThreadsForWorkgroupWARequiredThenFalseIsReturned, IGFX_XE_HPC_CORE); HWTEST_EXCLUDE_PRODUCT(HwInfoConfigTest, givenHwInfoConfigWhenAskedIfPipeControlPriorToNonPipelinedStateCommandsWARequiredThenFalseIsReturned, IGFX_XE_HPC_CORE); -HWTEST_EXCLUDE_PRODUCT(CommandStreamReceiverFlushTasDg2AndLaterTests, givenProgramPipeControlPriorToNonPipelinedStateCommandWhenPerDssBackedBufferThenThereIsPipeControlPriorToIt_MatcherIsRTCapable, IGFX_XE_HPC_CORE); +HWTEST_EXCLUDE_PRODUCT(CommandStreamReceiverFlushTaskDg2AndLaterTests, givenProgramPipeControlPriorToNonPipelinedStateCommandWhenPerDssBackedBufferThenThereIsPipeControlPriorToIt_MatcherIsRTCapable, IGFX_XE_HPC_CORE); HWTEST_EXCLUDE_PRODUCT(CommandStreamReceiverHwTestDg2AndLater, givenGen12AndLaterWhenRayTracingEnabledThenCommandIsAddedToBatchBuffer_MatcherIsRTCapable, IGFX_XE_HPC_CORE); HWTEST_EXCLUDE_PRODUCT(CommandStreamReceiverHwTestDg2AndLater, givenGen12AndLaterWhenRayTracingEnabledButAlreadySentThenCommandIsNotAddedToBatchBuffer_MatcherIsRTCapable, IGFX_XE_HPC_CORE); HWTEST_EXCLUDE_PRODUCT(HwInfoConfigTest, givenHwInfoConfigWhenAskedIfTile64With3DSurfaceOnBCSIsSupportedThenTrueIsReturned, IGFX_XE_HPC_CORE); diff --git a/opencl/test/unit_test/xe_hpc_core/pvc/test_hw_info_config_pvc.cpp b/opencl/test/unit_test/xe_hpc_core/pvc/test_hw_info_config_pvc.cpp index 7425de269e..6f5e0819e1 100644 --- a/opencl/test/unit_test/xe_hpc_core/pvc/test_hw_info_config_pvc.cpp +++ b/opencl/test/unit_test/xe_hpc_core/pvc/test_hw_info_config_pvc.cpp @@ -1,5 +1,5 @@ /* - * Copyright (C) 2021 Intel Corporation + * Copyright (C) 2021-2022 Intel Corporation * * SPDX-License-Identifier: MIT * @@ -52,7 +52,10 @@ PVCTEST_F(PvcHwInfoConfig, givenHwInfoConfigWhenAskedIfPipeControlPriorToNonPipe auto hwInfo = *defaultHwInfo; auto isRcs = false; - EXPECT_TRUE(hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs)); + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs); + + EXPECT_TRUE(isWARequiredOnMultiCCS); + EXPECT_TRUE(isWARequiredOnSingleCCS); } PVCTEST_F(PvcHwInfoConfig, givenPvcHwInfoConfigWhenCheckDirectSubmissionSupportedThenTrueIsReturned) { @@ -69,7 +72,10 @@ PVCTEST_F(PvcHwInfoConfig, givenHwInfoConfigAndProgramPipeControlPriorToNonPipel auto hwInfo = *defaultHwInfo; auto isRcs = false; - EXPECT_FALSE(hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs)); + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs); + + EXPECT_FALSE(isWARequiredOnMultiCCS); + EXPECT_TRUE(isWARequiredOnSingleCCS); } using CompilerHwInfoConfigHelperTestsPvc = ::testing::Test; diff --git a/opencl/test/unit_test/xe_hpg_core/dg2/excludes_dg2.cpp b/opencl/test/unit_test/xe_hpg_core/dg2/excludes_dg2.cpp index b631434021..47e3a09614 100644 --- a/opencl/test/unit_test/xe_hpg_core/dg2/excludes_dg2.cpp +++ b/opencl/test/unit_test/xe_hpg_core/dg2/excludes_dg2.cpp @@ -14,6 +14,7 @@ HWTEST_EXCLUDE_PRODUCT(HwInfoConfigTest, givenHardwareInfoWhenCallingIsMaxThread HWTEST_EXCLUDE_PRODUCT(HwInfoConfigTest, givenHwInfoConfigWhenAskedForDefaultEngineTypeAdjustmentThenFalseIsReturned, IGFX_DG2); HWTEST_EXCLUDE_PRODUCT(HwInfoConfigTest, givenHwInfoConfigWhenAskedIfAllocationSizeAdjustmentIsRequiredThenFalseIsReturned, IGFX_DG2); HWTEST_EXCLUDE_PRODUCT(HwInfoConfigTest, givenHwInfoConfigWhenAskedIfPrefetchDisablingIsRequiredThenFalseIsReturned, IGFX_DG2); +HWTEST_EXCLUDE_PRODUCT(HwInfoConfigTest, givenHwInfoConfigWhenAskedIfPipeControlPriorToNonPipelinedStateCommandsWARequiredThenFalseIsReturned, IGFX_DG2); HWTEST_EXCLUDE_PRODUCT(HwInfoConfigTest, givenHwInfoConfigWhenAskedIfTile64With3DSurfaceOnBCSIsSupportedThenTrueIsReturned, IGFX_DG2); HWTEST_EXCLUDE_PRODUCT(HwInfoConfigTestXeHpAndLater, givenXeHPAndLaterPlatformWhenAskedIfTile64With3DSurfaceOnBCSIsSupportedThenFalseIsReturned, IGFX_DG2); HWTEST_EXCLUDE_PRODUCT(WddmMemoryManagerSimpleTest, givenLinearStreamWhenItIsAllocatedThenItIsInLocalMemoryHasCpuPointerAndHasStandardHeap64kbAsGpuAddress, IGFX_DG2); diff --git a/shared/source/command_stream/command_stream_receiver_hw_dg2_and_later.inl b/shared/source/command_stream/command_stream_receiver_hw_dg2_and_later.inl index 8cb6123a33..de31168d2b 100644 --- a/shared/source/command_stream/command_stream_receiver_hw_dg2_and_later.inl +++ b/shared/source/command_stream/command_stream_receiver_hw_dg2_and_later.inl @@ -1,5 +1,5 @@ /* - * Copyright (C) 2021 Intel Corporation + * Copyright (C) 2021-2022 Intel Corporation * * SPDX-License-Identifier: MIT * @@ -41,7 +41,10 @@ size_t CommandStreamReceiverHw::getCmdSizeForPerDssBackedBuffer(const Ha size_t size = sizeof(_3DSTATE_BTD); auto hwInfoConfig = HwInfoConfig::get(hwInfo.platform.eProductFamily); - if (hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs())) { + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs()); + std::ignore = isWARequiredOnSingleCCS; + + if (isWARequiredOnMultiCCS) { size += sizeof(typename Family::PIPE_CONTROL); } @@ -52,10 +55,13 @@ template inline void CommandStreamReceiverHw::addPipeControlBefore3dState(LinearStream &commandStream, DispatchFlags &dispatchFlags) { auto &hwInfo = peekHwInfo(); auto hwInfoConfig = HwInfoConfig::get(hwInfo.platform.eProductFamily); + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs()); + std::ignore = isWARequiredOnSingleCCS; + PipeControlArgs args; args.dcFlushEnable = MemorySynchronizationCommands::getDcFlushEnable(true, hwInfo); - if (hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs()) && dispatchFlags.usePerDssBackedBuffer && !isPerDssBackedBufferSent) { + if (isWARequiredOnMultiCCS && dispatchFlags.usePerDssBackedBuffer && !isPerDssBackedBufferSent) { DEBUG_BREAK_IF(perDssBackedBuffer == nullptr); addPipeControlPriorToNonPipelinedStateCommand(commandStream, args); diff --git a/shared/source/command_stream/command_stream_receiver_hw_tgllp_and_later.inl b/shared/source/command_stream/command_stream_receiver_hw_tgllp_and_later.inl index 474affb5a9..ea2a3aed76 100644 --- a/shared/source/command_stream/command_stream_receiver_hw_tgllp_and_later.inl +++ b/shared/source/command_stream/command_stream_receiver_hw_tgllp_and_later.inl @@ -1,5 +1,5 @@ /* - * Copyright (C) 2019-2021 Intel Corporation + * Copyright (C) 2019-2022 Intel Corporation * * SPDX-License-Identifier: MIT * @@ -20,7 +20,10 @@ void CommandStreamReceiverHw::programComputeMode(LinearStream &stream programAdditionalPipelineSelect(stream, dispatchFlags.pipelineSelectArgs, true); auto hwInfoConfig = HwInfoConfig::get(hwInfo.platform.eProductFamily); - if (hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs())) { + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs()); + const auto isWARequired = isWARequiredOnSingleCCS || isWARequiredOnMultiCCS; + + if (isWARequired) { PipeControlArgs args; args.dcFlushEnable = MemorySynchronizationCommands::getDcFlushEnable(true, hwInfo); addPipeControlPriorToNonPipelinedStateCommand(stream, args); diff --git a/shared/source/command_stream/command_stream_receiver_hw_xehp_and_later.inl b/shared/source/command_stream/command_stream_receiver_hw_xehp_and_later.inl index d6790484ed..d66e0bd248 100644 --- a/shared/source/command_stream/command_stream_receiver_hw_xehp_and_later.inl +++ b/shared/source/command_stream/command_stream_receiver_hw_xehp_and_later.inl @@ -1,5 +1,5 @@ /* - * Copyright (C) 2021 Intel Corporation + * Copyright (C) 2021-2022 Intel Corporation * * SPDX-License-Identifier: MIT * @@ -59,7 +59,10 @@ size_t CommandStreamReceiverHw::getCmdSizeForComputeMode() { auto &hwInfo = peekHwInfo(); if (isComputeModeNeeded()) { auto hwInfoConfig = HwInfoConfig::get(hwInfo.platform.eProductFamily); - if (hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs())) { + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs()); + const auto isWARequired = isWARequiredOnSingleCCS || isWARequiredOnMultiCCS; + + if (isWARequired) { size += sizeof(typename GfxFamily::PIPE_CONTROL); } size += sizeof(typename GfxFamily::STATE_COMPUTE_MODE); @@ -164,8 +167,9 @@ template inline void CommandStreamReceiverHw::addPipeControlPriorToNonPipelinedStateCommand(LinearStream &commandStream, PipeControlArgs args) { auto &hwInfo = peekHwInfo(); auto hwInfoConfig = HwInfoConfig::get(hwInfo.platform.eProductFamily); + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs()); - if (hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs())) { + if (isWARequiredOnMultiCCS) { args.textureCacheInvalidationEnable = true; args.hdcPipelineFlush = true; args.amfsFlushEnable = true; @@ -175,6 +179,10 @@ inline void CommandStreamReceiverHw::addPipeControlPriorToNonPipeline args.dcFlushEnable = false; + setPipeControlPriorToNonPipelinedStateCommandExtraProperties(args); + } else if (isWARequiredOnSingleCCS) { + args.hdcPipelineFlush = true; + setPipeControlPriorToNonPipelinedStateCommandExtraProperties(args); } @@ -189,9 +197,10 @@ inline void CommandStreamReceiverHw::addPipeControlBeforeStateSip(Lin bool debuggingEnabled = device.getDebugger() != nullptr; PipeControlArgs args; args.dcFlushEnable = MemorySynchronizationCommands::getDcFlushEnable(true, hwInfo); + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs()); + const auto isWARequired = isWARequiredOnSingleCCS || isWARequiredOnMultiCCS; - if (hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs()) && debuggingEnabled && - !hwHelper.isSipWANeeded(hwInfo)) { + if (isWARequired && debuggingEnabled && !hwHelper.isSipWANeeded(hwInfo)) { addPipeControlPriorToNonPipelinedStateCommand(commandStream, args); } } diff --git a/shared/source/command_stream/preemption_xehp_and_later.inl b/shared/source/command_stream/preemption_xehp_and_later.inl index 74eb41faf3..db2f05038e 100644 --- a/shared/source/command_stream/preemption_xehp_and_later.inl +++ b/shared/source/command_stream/preemption_xehp_and_later.inl @@ -1,5 +1,5 @@ /* - * Copyright (C) 2018-2021 Intel Corporation + * Copyright (C) 2018-2022 Intel Corporation * * SPDX-License-Identifier: MIT * @@ -83,7 +83,10 @@ size_t PreemptionHelper::getRequiredStateSipCmdSize(Device &device, b size += 2 * sizeof(typename GfxFamily::MI_LOAD_REGISTER_IMM); } else { auto hwInfoConfig = HwInfoConfig::get(hwInfo.platform.eProductFamily); - if (hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs)) { + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs); + const auto isWARequired = isWARequiredOnSingleCCS || isWARequiredOnMultiCCS; + + if (isWARequired) { size += sizeof(typename GfxFamily::PIPE_CONTROL); } size += sizeof(typename GfxFamily::STATE_SIP); diff --git a/shared/source/os_interface/hw_info_config.h b/shared/source/os_interface/hw_info_config.h index 444cb4b0a1..3788d77761 100644 --- a/shared/source/os_interface/hw_info_config.h +++ b/shared/source/os_interface/hw_info_config.h @@ -67,7 +67,7 @@ class HwInfoConfig { virtual bool isPrefetchDisablingRequired(const HardwareInfo &hwInfo) const = 0; virtual bool isNewResidencyModelSupported() const = 0; virtual bool isDirectSubmissionSupported(const HardwareInfo &hwInfo) const = 0; - virtual bool isPipeControlPriorToNonPipelinedStateCommandsWARequired(const HardwareInfo &hwInfo, bool isRcs) const = 0; + virtual std::pair isPipeControlPriorToNonPipelinedStateCommandsWARequired(const HardwareInfo &hwInfo, bool isRcs) const = 0; virtual bool heapInLocalMem(const HardwareInfo &hwInfo) const = 0; virtual void setCapabilityCoherencyFlag(const HardwareInfo &hwInfo, bool &coherencyFlag) = 0; virtual bool isAdditionalMediaSamplerProgrammingRequired() const = 0; @@ -135,7 +135,7 @@ class HwInfoConfigHw : public HwInfoConfig { bool isPrefetchDisablingRequired(const HardwareInfo &hwInfo) const override; bool isNewResidencyModelSupported() const override; bool isDirectSubmissionSupported(const HardwareInfo &hwInfo) const override; - bool isPipeControlPriorToNonPipelinedStateCommandsWARequired(const HardwareInfo &hwInfo, bool isRcs) const override; + std::pair isPipeControlPriorToNonPipelinedStateCommandsWARequired(const HardwareInfo &hwInfo, bool isRcs) const override; bool heapInLocalMem(const HardwareInfo &hwInfo) const override; void setCapabilityCoherencyFlag(const HardwareInfo &hwInfo, bool &coherencyFlag) override; bool isAdditionalMediaSamplerProgrammingRequired() const override; diff --git a/shared/source/os_interface/hw_info_config.inl b/shared/source/os_interface/hw_info_config.inl index 26509d2afe..854482328a 100644 --- a/shared/source/os_interface/hw_info_config.inl +++ b/shared/source/os_interface/hw_info_config.inl @@ -214,8 +214,8 @@ bool HwInfoConfigHw::isPrefetchDisablingRequired(const HardwareInfo } template -bool HwInfoConfigHw::isPipeControlPriorToNonPipelinedStateCommandsWARequired(const HardwareInfo &hwInfo, bool isRcs) const { - return false; +std::pair HwInfoConfigHw::isPipeControlPriorToNonPipelinedStateCommandsWARequired(const HardwareInfo &hwInfo, bool isRcs) const { + return {false, false}; } template diff --git a/shared/source/xe_hp_core/os_agnostic_hw_info_config_xe_hp_core.inl b/shared/source/xe_hp_core/os_agnostic_hw_info_config_xe_hp_core.inl index 62a709e2f8..e875fa9831 100644 --- a/shared/source/xe_hp_core/os_agnostic_hw_info_config_xe_hp_core.inl +++ b/shared/source/xe_hp_core/os_agnostic_hw_info_config_xe_hp_core.inl @@ -1,5 +1,5 @@ /* - * Copyright (C) 2021 Intel Corporation + * Copyright (C) 2021-2022 Intel Corporation * * SPDX-License-Identifier: MIT * @@ -104,14 +104,15 @@ LocalMemoryAccessMode HwInfoConfigHw::getDefaultLocalMemoryAccessMod } template <> -bool HwInfoConfigHw::isPipeControlPriorToNonPipelinedStateCommandsWARequired(const HardwareInfo &hwInfo, bool isRcs) const { - bool required = hwInfo.gtSystemInfo.CCSInfo.NumberOfCCSEnabled > 1; +std::pair HwInfoConfigHw::isPipeControlPriorToNonPipelinedStateCommandsWARequired(const HardwareInfo &hwInfo, bool isRcs) const { + auto isWARequiredOnSingleCCS = false; + auto isWARequiredOnMultiCCS = hwInfo.gtSystemInfo.CCSInfo.NumberOfCCSEnabled > 1; if (DebugManager.flags.ProgramPipeControlPriorToNonPipelinedStateCommand.get() != -1) { - required = DebugManager.flags.ProgramPipeControlPriorToNonPipelinedStateCommand.get(); + isWARequiredOnMultiCCS = DebugManager.flags.ProgramPipeControlPriorToNonPipelinedStateCommand.get(); } - return required; + return {isWARequiredOnSingleCCS, isWARequiredOnMultiCCS}; } template <> diff --git a/shared/source/xe_hpc_core/os_agnostic_hw_info_config_pvc.inl b/shared/source/xe_hpc_core/os_agnostic_hw_info_config_pvc.inl index 6c3f198fe5..1a82fe38a2 100644 --- a/shared/source/xe_hpc_core/os_agnostic_hw_info_config_pvc.inl +++ b/shared/source/xe_hpc_core/os_agnostic_hw_info_config_pvc.inl @@ -1,5 +1,5 @@ /* - * Copyright (C) 2021 Intel Corporation + * Copyright (C) 2021-2022 Intel Corporation * * SPDX-License-Identifier: MIT * @@ -101,14 +101,15 @@ bool HwInfoConfigHw::isDisableOverdispatchAvailable(const HardwareIn } template <> -bool HwInfoConfigHw::isPipeControlPriorToNonPipelinedStateCommandsWARequired(const HardwareInfo &hwInfo, bool isRcs) const { - bool required = hwInfo.gtSystemInfo.CCSInfo.NumberOfCCSEnabled > 1; +std::pair HwInfoConfigHw::isPipeControlPriorToNonPipelinedStateCommandsWARequired(const HardwareInfo &hwInfo, bool isRcs) const { + auto isWARequiredOnSingleCCS = true; + auto isWARequiredOnMultiCCS = hwInfo.gtSystemInfo.CCSInfo.NumberOfCCSEnabled > 1; if (DebugManager.flags.ProgramPipeControlPriorToNonPipelinedStateCommand.get() != -1) { - required = DebugManager.flags.ProgramPipeControlPriorToNonPipelinedStateCommand.get(); + isWARequiredOnMultiCCS = DebugManager.flags.ProgramPipeControlPriorToNonPipelinedStateCommand.get(); } - return required; + return {isWARequiredOnSingleCCS, isWARequiredOnMultiCCS}; } template <> diff --git a/shared/source/xe_hpg_core/os_agnostic_hw_info_config_dg2.inl b/shared/source/xe_hpg_core/os_agnostic_hw_info_config_dg2.inl index 740622bc70..bf705ce7c1 100644 --- a/shared/source/xe_hpg_core/os_agnostic_hw_info_config_dg2.inl +++ b/shared/source/xe_hpg_core/os_agnostic_hw_info_config_dg2.inl @@ -123,14 +123,15 @@ bool HwInfoConfigHw::isPrefetchDisablingRequired(const HardwareInfo } template <> -bool HwInfoConfigHw::isPipeControlPriorToNonPipelinedStateCommandsWARequired(const HardwareInfo &hwInfo, bool isRcs) const { - bool required = hwInfo.gtSystemInfo.CCSInfo.NumberOfCCSEnabled > 1 && !isRcs; +std::pair HwInfoConfigHw::isPipeControlPriorToNonPipelinedStateCommandsWARequired(const HardwareInfo &hwInfo, bool isRcs) const { + auto isWARequiredOnSingleCCS = true; + auto isWARequiredOnMultiCCS = hwInfo.gtSystemInfo.CCSInfo.NumberOfCCSEnabled > 1 && !isRcs; if (DebugManager.flags.ProgramPipeControlPriorToNonPipelinedStateCommand.get() != -1) { - required = DebugManager.flags.ProgramPipeControlPriorToNonPipelinedStateCommand.get(); + isWARequiredOnMultiCCS = DebugManager.flags.ProgramPipeControlPriorToNonPipelinedStateCommand.get(); } - return required; + return {isWARequiredOnSingleCCS, isWARequiredOnMultiCCS}; } template <> @@ -165,4 +166,4 @@ uint32_t HwInfoConfigHw::computeMaxNeededSubSliceSpace(const Hardwar template <> void HwInfoConfigHw::convertTimestampsFromOaToCsDomain(uint64_t ×tampData) { timestampData >>= 1; -} \ No newline at end of file +} diff --git a/shared/test/common/mocks/mock_hw_info_config.cpp b/shared/test/common/mocks/mock_hw_info_config.cpp index 2c7c4601c2..3b29e89cf9 100644 --- a/shared/test/common/mocks/mock_hw_info_config.cpp +++ b/shared/test/common/mocks/mock_hw_info_config.cpp @@ -194,8 +194,8 @@ bool HwInfoConfigHw::isNewResidencyModelSupported() const { } template <> -bool HwInfoConfigHw::isPipeControlPriorToNonPipelinedStateCommandsWARequired(const HardwareInfo &hwInfo, bool isRcs) const { - return false; +std::pair HwInfoConfigHw::isPipeControlPriorToNonPipelinedStateCommandsWARequired(const HardwareInfo &hwInfo, bool isRcs) const { + return {false, false}; } template <> diff --git a/shared/test/common/test_macros/header/common_matchers.h b/shared/test/common/test_macros/header/common_matchers.h index 28a8f4eda4..0cf2c7efb2 100644 --- a/shared/test/common/test_macros/header/common_matchers.h +++ b/shared/test/common/test_macros/header/common_matchers.h @@ -34,6 +34,7 @@ using IsAtMostXeHpgCore = IsAtMostGfxCore; using IsAtLeastXeHpcCore = IsAtLeastGfxCore; using isXeHpOrXeHpcCore = IsAnyGfxCores; +using isXeHpcOrXeHpgCore = IsAnyGfxCores; using IsSKL = IsProduct; using IsKBL = IsProduct; diff --git a/shared/test/common/xe_hpg_core/dg2/excludes_dg2.cpp b/shared/test/common/xe_hpg_core/dg2/excludes_dg2.cpp index 1f58fd13b2..aa2ed2eeba 100644 --- a/shared/test/common/xe_hpg_core/dg2/excludes_dg2.cpp +++ b/shared/test/common/xe_hpg_core/dg2/excludes_dg2.cpp @@ -1,5 +1,5 @@ /* - * Copyright (C) 2021 Intel Corporation + * Copyright (C) 2021-2022 Intel Corporation * * SPDX-License-Identifier: MIT * diff --git a/shared/test/common/xe_hpg_core/excludes_xe_hpg_core.cpp b/shared/test/common/xe_hpg_core/excludes_xe_hpg_core.cpp index 78f690b35f..2a99367f1e 100644 --- a/shared/test/common/xe_hpg_core/excludes_xe_hpg_core.cpp +++ b/shared/test/common/xe_hpg_core/excludes_xe_hpg_core.cpp @@ -1,5 +1,5 @@ /* - * Copyright (C) 2021 Intel Corporation + * Copyright (C) 2021-2022 Intel Corporation * * SPDX-License-Identifier: MIT * @@ -8,3 +8,7 @@ #include "shared/test/common/test_macros/test.h" HWTEST_EXCLUDE_PRODUCT(CommandEncodeStatesTest, givenEventAddressWhenEncodeThenMocsFromGmmHelperIsSet, IGFX_XE_HPG_CORE); +HWTEST_EXCLUDE_PRODUCT(XeHPAndLaterPreemptionTests, GivenDebuggerUsedWhenProgrammingStateSipThenStateSipIsAdded, IGFX_XE_HPG_CORE); +HWTEST_EXCLUDE_PRODUCT(ComputeModeRequirements, givenComputeModeCmdSizeWhenLargeGrfModeChangeIsRequiredThenSCMCommandSizeIsCalculated, IGFX_XE_HPG_CORE); +HWTEST_EXCLUDE_PRODUCT(ComputeModeRequirements, givenCoherencyWithSharedHandlesWhenCommandSizeIsCalculatedThenCorrectCommandSizeIsReturned, IGFX_XE_HPG_CORE); +HWTEST_EXCLUDE_PRODUCT(ComputeModeRequirements, givenCoherencyWithoutSharedHandlesWhenCommandSizeIsCalculatedThenCorrectCommandSizeIsReturned, IGFX_XE_HPG_CORE); diff --git a/shared/test/unit_test/command_stream/compute_mode_tests_xehp_and_later.cpp b/shared/test/unit_test/command_stream/compute_mode_tests_xehp_and_later.cpp index f354835704..39f7e2dafe 100644 --- a/shared/test/unit_test/command_stream/compute_mode_tests_xehp_and_later.cpp +++ b/shared/test/unit_test/command_stream/compute_mode_tests_xehp_and_later.cpp @@ -79,8 +79,17 @@ struct ForceNonCoherentSupportedMatcher { HWTEST2_F(ComputeModeRequirements, givenCoherencyWithoutSharedHandlesWhenComputeModeIsProgrammedThenCorrectCommandsAreAdded, ForceNonCoherentSupportedMatcher) { SetUpImpl(); using STATE_COMPUTE_MODE = typename FamilyType::STATE_COMPUTE_MODE; + using PIPE_CONTROL = typename FamilyType::PIPE_CONTROL; + + const auto &hwInfoConfig = *HwInfoConfig::get(productFamily); + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(*defaultHwInfo, csr->isRcs()); + std::ignore = isWARequiredOnMultiCCS; auto cmdsSize = sizeof(STATE_COMPUTE_MODE); + if (isWARequiredOnSingleCCS) { + cmdsSize += +sizeof(PIPE_CONTROL); + } + char buff[1024] = {0}; LinearStream stream(buff, 1024); @@ -93,6 +102,9 @@ HWTEST2_F(ComputeModeRequirements, givenCoherencyWithoutSharedHandlesWhenCompute EXPECT_EQ(cmdsSize, stream.getUsed()); auto scmCmd = reinterpret_cast(stream.getCpuBase()); + if (isWARequiredOnSingleCCS) { + scmCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), sizeof(PIPE_CONTROL))); + } EXPECT_TRUE(isValueSet(scmCmd->getMaskBits(), expectedBitsMask)); expectedScmCmd.setMaskBits(scmCmd->getMaskBits()); EXPECT_TRUE(memcmp(&expectedScmCmd, scmCmd, sizeof(STATE_COMPUTE_MODE)) == 0); @@ -106,6 +118,9 @@ HWTEST2_F(ComputeModeRequirements, givenCoherencyWithoutSharedHandlesWhenCompute expectedScmCmd = FamilyType::cmdInitStateComputeMode; expectedScmCmd.setForceNonCoherent(STATE_COMPUTE_MODE::FORCE_NON_COHERENT_FORCE_DISABLED); scmCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), startOffset)); + if (isWARequiredOnSingleCCS) { + scmCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), startOffset + sizeof(PIPE_CONTROL))); + } EXPECT_TRUE(isValueSet(scmCmd->getMaskBits(), expectedBitsMask)); expectedScmCmd.setMaskBits(scmCmd->getMaskBits()); EXPECT_TRUE(memcmp(&expectedScmCmd, scmCmd, sizeof(STATE_COMPUTE_MODE)) == 0); @@ -116,7 +131,14 @@ HWTEST2_F(ComputeModeRequirements, givenCoherencyWithSharedHandlesWhenComputeMod using STATE_COMPUTE_MODE = typename FamilyType::STATE_COMPUTE_MODE; using PIPE_CONTROL = typename FamilyType::PIPE_CONTROL; + const auto &hwInfoConfig = *HwInfoConfig::get(productFamily); + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(*defaultHwInfo, csr->isRcs()); + std::ignore = isWARequiredOnMultiCCS; + auto cmdsSize = sizeof(STATE_COMPUTE_MODE) + sizeof(PIPE_CONTROL); + if (isWARequiredOnSingleCCS) { + cmdsSize += +sizeof(PIPE_CONTROL); + } char buff[1024] = {0}; LinearStream stream(buff, 1024); @@ -131,11 +153,17 @@ HWTEST2_F(ComputeModeRequirements, givenCoherencyWithSharedHandlesWhenComputeMod EXPECT_EQ(cmdsSize, stream.getUsed()); auto scmCmd = reinterpret_cast(stream.getCpuBase()); + if (isWARequiredOnSingleCCS) { + scmCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), sizeof(PIPE_CONTROL))); + } EXPECT_TRUE(isValueSet(scmCmd->getMaskBits(), expectedBitsMask)); expectedScmCmd.setMaskBits(scmCmd->getMaskBits()); EXPECT_TRUE(memcmp(&expectedScmCmd, scmCmd, sizeof(STATE_COMPUTE_MODE)) == 0); auto pcCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), sizeof(STATE_COMPUTE_MODE))); + if (isWARequiredOnSingleCCS) { + pcCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), sizeof(STATE_COMPUTE_MODE) + sizeof(PIPE_CONTROL))); + } EXPECT_TRUE(memcmp(&expectedPcCmd, pcCmd, sizeof(PIPE_CONTROL)) == 0); auto startOffset = stream.getUsed(); @@ -147,11 +175,17 @@ HWTEST2_F(ComputeModeRequirements, givenCoherencyWithSharedHandlesWhenComputeMod expectedScmCmd = FamilyType::cmdInitStateComputeMode; expectedScmCmd.setForceNonCoherent(STATE_COMPUTE_MODE::FORCE_NON_COHERENT_FORCE_DISABLED); scmCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), startOffset)); + if (isWARequiredOnSingleCCS) { + scmCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), startOffset + sizeof(PIPE_CONTROL))); + } EXPECT_TRUE(isValueSet(scmCmd->getMaskBits(), expectedBitsMask)); expectedScmCmd.setMaskBits(scmCmd->getMaskBits()); EXPECT_TRUE(memcmp(&expectedScmCmd, scmCmd, sizeof(STATE_COMPUTE_MODE)) == 0); pcCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), startOffset + sizeof(STATE_COMPUTE_MODE))); + if (isWARequiredOnSingleCCS) { + pcCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), startOffset + sizeof(STATE_COMPUTE_MODE) + sizeof(PIPE_CONTROL))); + } EXPECT_TRUE(memcmp(&expectedPcCmd, pcCmd, sizeof(PIPE_CONTROL)) == 0); } @@ -314,7 +348,14 @@ HWTEST2_F(ComputeModeRequirements, givenComputeModeProgrammingWhenLargeGrfModeCh using STATE_COMPUTE_MODE = typename FamilyType::STATE_COMPUTE_MODE; using PIPE_CONTROL = typename FamilyType::PIPE_CONTROL; + const auto &hwInfoConfig = *HwInfoConfig::get(productFamily); + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(*defaultHwInfo, csr->isRcs()); + std::ignore = isWARequiredOnMultiCCS; + auto cmdsSize = sizeof(STATE_COMPUTE_MODE); + if (isWARequiredOnSingleCCS) { + cmdsSize += +sizeof(PIPE_CONTROL); + } char buff[1024]; LinearStream stream(buff, 1024); @@ -329,6 +370,9 @@ HWTEST2_F(ComputeModeRequirements, givenComputeModeProgrammingWhenLargeGrfModeCh EXPECT_EQ(cmdsSize, stream.getUsed()); auto scmCmd = reinterpret_cast(stream.getCpuBase()); + if (isWARequiredOnSingleCCS) { + scmCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), sizeof(PIPE_CONTROL))); + } EXPECT_TRUE(isValueSet(scmCmd->getMaskBits(), expectedBitsMask)); expectedScmCmd.setMaskBits(scmCmd->getMaskBits()); EXPECT_TRUE(memcmp(&expectedScmCmd, scmCmd, sizeof(STATE_COMPUTE_MODE)) == 0); @@ -343,6 +387,9 @@ HWTEST2_F(ComputeModeRequirements, givenComputeModeProgrammingWhenLargeGrfModeCh expectedScmCmd.setLargeGrfMode(false); expectedScmCmd.setForceNonCoherent(STATE_COMPUTE_MODE::FORCE_NON_COHERENT_FORCE_GPU_NON_COHERENT); scmCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), startOffset)); + if (isWARequiredOnSingleCCS) { + scmCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), startOffset + sizeof(PIPE_CONTROL))); + } EXPECT_TRUE(isValueSet(scmCmd->getMaskBits(), expectedBitsMask)); expectedScmCmd.setMaskBits(scmCmd->getMaskBits()); EXPECT_TRUE(memcmp(&expectedScmCmd, scmCmd, sizeof(STATE_COMPUTE_MODE)) == 0); @@ -362,8 +409,16 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, ComputeModeRequirements, givenComputeModeProgrammin HWTEST2_F(ComputeModeRequirements, givenComputeModeProgrammingWhenRequiredGRFNumberIsLowerThan128ThenSmallGRFModeIsProgrammed, ForceNonCoherentSupportedMatcher) { SetUpImpl(); using STATE_COMPUTE_MODE = typename FamilyType::STATE_COMPUTE_MODE; + using PIPE_CONTROL = typename FamilyType::PIPE_CONTROL; + + const auto &hwInfoConfig = *HwInfoConfig::get(productFamily); + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(*defaultHwInfo, csr->isRcs()); + std::ignore = isWARequiredOnMultiCCS; auto cmdsSize = sizeof(STATE_COMPUTE_MODE); + if (isWARequiredOnSingleCCS) { + cmdsSize += +sizeof(PIPE_CONTROL); + } char buff[1024]; LinearStream stream(buff, 1024); @@ -377,6 +432,9 @@ HWTEST2_F(ComputeModeRequirements, givenComputeModeProgrammingWhenRequiredGRFNum EXPECT_EQ(cmdsSize, stream.getUsed()); auto scmCmd = reinterpret_cast(stream.getCpuBase()); + if (isWARequiredOnSingleCCS) { + scmCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), sizeof(PIPE_CONTROL))); + } EXPECT_TRUE(isValueSet(scmCmd->getMaskBits(), expectedBitsMask)); expectedScmCmd.setMaskBits(scmCmd->getMaskBits()); EXPECT_TRUE(memcmp(&expectedScmCmd, scmCmd, sizeof(STATE_COMPUTE_MODE)) == 0); @@ -387,7 +445,14 @@ HWTEST2_F(ComputeModeRequirements, givenComputeModeProgrammingWhenRequiredGRFNum using STATE_COMPUTE_MODE = typename FamilyType::STATE_COMPUTE_MODE; using PIPE_CONTROL = typename FamilyType::PIPE_CONTROL; + const auto &hwInfoConfig = *HwInfoConfig::get(productFamily); + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(*defaultHwInfo, csr->isRcs()); + std::ignore = isWARequiredOnMultiCCS; + auto cmdsSize = sizeof(STATE_COMPUTE_MODE); + if (isWARequiredOnSingleCCS) { + cmdsSize += +sizeof(PIPE_CONTROL); + } char buff[1024]; LinearStream stream(buff, 1024); @@ -401,6 +466,9 @@ HWTEST2_F(ComputeModeRequirements, givenComputeModeProgrammingWhenRequiredGRFNum EXPECT_EQ(cmdsSize, stream.getUsed()); auto scmCmd = reinterpret_cast(stream.getCpuBase()); + if (isWARequiredOnSingleCCS) { + scmCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), sizeof(PIPE_CONTROL))); + } EXPECT_TRUE(isValueSet(scmCmd->getMaskBits(), expectedBitsMask)); expectedScmCmd.setMaskBits(scmCmd->getMaskBits()); EXPECT_TRUE(memcmp(&expectedScmCmd, scmCmd, sizeof(STATE_COMPUTE_MODE)) == 0); diff --git a/shared/test/unit_test/xe_hp_core/compute_mode_tests_xe_hp_core.cpp b/shared/test/unit_test/xe_hp_core/compute_mode_tests_xe_hp_core.cpp index e7b14ef4e3..f8c3881941 100644 --- a/shared/test/unit_test/xe_hp_core/compute_mode_tests_xe_hp_core.cpp +++ b/shared/test/unit_test/xe_hp_core/compute_mode_tests_xe_hp_core.cpp @@ -48,10 +48,10 @@ HWTEST2_F(ComputeModeRequirements, GivenProgramPipeControlPriorToNonPipelinedSta EXPECT_TRUE(pipeControlCmd->getConstantCacheInvalidationEnable()); EXPECT_TRUE(pipeControlCmd->getStateCacheInvalidationEnable()); - auto stateComputeModelCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), sizeof(PIPE_CONTROL))); - EXPECT_TRUE(isValueSet(stateComputeModelCmd->getMaskBits(), expectedBitsMask)); - expectedScmCmd.setMaskBits(stateComputeModelCmd->getMaskBits()); - EXPECT_TRUE(memcmp(&expectedScmCmd, stateComputeModelCmd, sizeof(STATE_COMPUTE_MODE)) == 0); + auto stateComputeModeCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), sizeof(PIPE_CONTROL))); + EXPECT_TRUE(isValueSet(stateComputeModeCmd->getMaskBits(), expectedBitsMask)); + expectedScmCmd.setMaskBits(stateComputeModeCmd->getMaskBits()); + EXPECT_TRUE(memcmp(&expectedScmCmd, stateComputeModeCmd, sizeof(STATE_COMPUTE_MODE)) == 0); } HWTEST2_F(ComputeModeRequirements, GivenMultipleCCSEnabledSetupThenCorrectCommandsAreAdded, IsXEHP) { @@ -91,10 +91,10 @@ HWTEST2_F(ComputeModeRequirements, GivenMultipleCCSEnabledSetupThenCorrectComman EXPECT_TRUE(pipeControlCmd->getConstantCacheInvalidationEnable()); EXPECT_TRUE(pipeControlCmd->getStateCacheInvalidationEnable()); - auto stateComputeModelCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), sizeof(PIPE_CONTROL))); - EXPECT_TRUE(isValueSet(stateComputeModelCmd->getMaskBits(), expectedBitsMask)); - expectedScmCmd.setMaskBits(stateComputeModelCmd->getMaskBits()); - EXPECT_TRUE(memcmp(&expectedScmCmd, stateComputeModelCmd, sizeof(STATE_COMPUTE_MODE)) == 0); + auto stateComputeModeCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), sizeof(PIPE_CONTROL))); + EXPECT_TRUE(isValueSet(stateComputeModeCmd->getMaskBits(), expectedBitsMask)); + expectedScmCmd.setMaskBits(stateComputeModeCmd->getMaskBits()); + EXPECT_TRUE(memcmp(&expectedScmCmd, stateComputeModeCmd, sizeof(STATE_COMPUTE_MODE)) == 0); } HWTEST2_F(ComputeModeRequirements, GivenProgramPipeControlPriorToNonPipelinedStateCommandThenCommandSizeIsCalculatedAndCorrectCommandSizeIsReturned, IsXEHP) { diff --git a/shared/test/unit_test/xe_hpc_core/compute_mode_tests_xe_hpc_core.cpp b/shared/test/unit_test/xe_hpc_core/compute_mode_tests_xe_hpc_core.cpp index 60f471d0e5..82b9274676 100644 --- a/shared/test/unit_test/xe_hpc_core/compute_mode_tests_xe_hpc_core.cpp +++ b/shared/test/unit_test/xe_hpc_core/compute_mode_tests_xe_hpc_core.cpp @@ -387,9 +387,9 @@ PVCTEST_F(PvcComputeModeRequirements, givenComputeModeProgrammingThenCorrectComm EXPECT_TRUE(pipeControlCmd->getConstantCacheInvalidationEnable()); EXPECT_TRUE(pipeControlCmd->getStateCacheInvalidationEnable()); - auto stateComputeModelCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), sizeof(PIPE_CONTROL))); - expectedScmCmd.setMaskBits(stateComputeModelCmd->getMaskBits()); - EXPECT_TRUE(memcmp(&expectedScmCmd, stateComputeModelCmd, sizeof(STATE_COMPUTE_MODE)) == 0); + auto stateComputeModeCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), sizeof(PIPE_CONTROL))); + expectedScmCmd.setMaskBits(stateComputeModeCmd->getMaskBits()); + EXPECT_TRUE(memcmp(&expectedScmCmd, stateComputeModeCmd, sizeof(STATE_COMPUTE_MODE)) == 0); } PVCTEST_F(PvcComputeModeRequirements, givenProgramPipeControlPriorToNonPipelinedStateCommandThenCorrectCommandsAreAdded) { @@ -435,7 +435,56 @@ PVCTEST_F(PvcComputeModeRequirements, givenProgramPipeControlPriorToNonPipelined EXPECT_TRUE(pipeControlCmd->getConstantCacheInvalidationEnable()); EXPECT_TRUE(pipeControlCmd->getStateCacheInvalidationEnable()); - auto stateComputeModelCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), sizeof(PIPE_CONTROL))); - expectedScmCmd.setMaskBits(stateComputeModelCmd->getMaskBits()); - EXPECT_TRUE(memcmp(&expectedScmCmd, stateComputeModelCmd, sizeof(STATE_COMPUTE_MODE)) == 0); + auto stateComputeModeCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), sizeof(PIPE_CONTROL))); + expectedScmCmd.setMaskBits(stateComputeModeCmd->getMaskBits()); + EXPECT_TRUE(memcmp(&expectedScmCmd, stateComputeModeCmd, sizeof(STATE_COMPUTE_MODE)) == 0); +} + +PVCTEST_F(PvcComputeModeRequirements, GivenSingleCCSEnabledSetupThenCorrectCommandsAreAdded) { + HardwareInfo hwInfo = *defaultHwInfo; + hwInfo.gtSystemInfo.CCSInfo.NumberOfCCSEnabled = 1; + + SetUpImpl(&hwInfo); + + using STATE_COMPUTE_MODE = typename FamilyType::STATE_COMPUTE_MODE; + using PIPE_CONTROL = typename FamilyType::PIPE_CONTROL; + + auto cmdsSize = sizeof(STATE_COMPUTE_MODE) + sizeof(PIPE_CONTROL); + char buff[1024] = {0}; + LinearStream stream(buff, 1024); + + auto expectedScmCmd = FamilyType::cmdInitStateComputeMode; + expectedScmCmd.setForceNonCoherent(STATE_COMPUTE_MODE::FORCE_NON_COHERENT_FORCE_GPU_NON_COHERENT); + expectedScmCmd.setEuThreadSchedulingModeOverride(STATE_COMPUTE_MODE::EU_THREAD_SCHEDULING_MODE_OVERRIDE_OLDEST_FIRST); + expectedScmCmd.setMaskBits(FamilyType::stateComputeModeForceNonCoherentMask | FamilyType::stateComputeModeLargeGrfModeMask | + FamilyType::stateComputeModeEuThreadSchedulingModeOverrideMask); + + overrideComputeModeRequest(true, false, false, true, true); + + auto retSize = getCsrHw()->getCmdSizeForComputeMode(); + EXPECT_EQ(cmdsSize, retSize); + + getCsrHw()->programComputeMode(stream, flags, hwInfo); + EXPECT_EQ(cmdsSize, stream.getUsed()); + + auto startOffset = getCsrHw()->commandStream.getUsed(); + + HardwareParse hwParser; + hwParser.parseCommands(stream, startOffset); + + auto pipeControlIterator = find(hwParser.cmdList.begin(), hwParser.cmdList.end()); + auto pipeControlCmd = genCmdCast(*pipeControlIterator); + + EXPECT_TRUE(UnitTestHelper::getPipeControlHdcPipelineFlush(*pipeControlCmd)); + EXPECT_TRUE(pipeControlCmd->getUnTypedDataPortCacheFlush()); + + EXPECT_FALSE(pipeControlCmd->getAmfsFlushEnable()); + EXPECT_FALSE(pipeControlCmd->getInstructionCacheInvalidateEnable()); + EXPECT_FALSE(pipeControlCmd->getTextureCacheInvalidationEnable()); + EXPECT_FALSE(pipeControlCmd->getConstantCacheInvalidationEnable()); + EXPECT_FALSE(pipeControlCmd->getStateCacheInvalidationEnable()); + + auto stateComputeModeCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), sizeof(PIPE_CONTROL))); + expectedScmCmd.setMaskBits(stateComputeModeCmd->getMaskBits()); + EXPECT_TRUE(memcmp(&expectedScmCmd, stateComputeModeCmd, sizeof(STATE_COMPUTE_MODE)) == 0); } diff --git a/shared/test/unit_test/xe_hpg_core/compute_mode_tests_xe_hpg_core.cpp b/shared/test/unit_test/xe_hpg_core/compute_mode_tests_xe_hpg_core.cpp index 6924f82985..5846ae0930 100644 --- a/shared/test/unit_test/xe_hpg_core/compute_mode_tests_xe_hpg_core.cpp +++ b/shared/test/unit_test/xe_hpg_core/compute_mode_tests_xe_hpg_core.cpp @@ -17,10 +17,21 @@ using namespace NEO; using ComputeModeRequirementsXeHpgCore = ComputeModeRequirements; XE_HPG_CORETEST_F(ComputeModeRequirementsXeHpgCore, GivenVariousSettingsWhenComputeModeIsProgrammedThenThreadLimitsAreCorrectlySet) { - using STATE_COMPUTE_MODE = typename FamilyType::STATE_COMPUTE_MODE; - DebugManagerStateRestore restorer; SetUpImpl(); + + using STATE_COMPUTE_MODE = typename FamilyType::STATE_COMPUTE_MODE; + using PIPE_CONTROL = typename FamilyType::PIPE_CONTROL; + + const auto &hwInfoConfig = *HwInfoConfig::get(productFamily); + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(*defaultHwInfo, csr->isRcs()); + std::ignore = isWARequiredOnMultiCCS; + + auto cmdsSize = sizeof(STATE_COMPUTE_MODE); + if (isWARequiredOnSingleCCS) { + cmdsSize += +sizeof(PIPE_CONTROL); + } + overrideComputeModeRequest(false, false, false, true, 128u); auto defaultScmCmd = FamilyType::cmdInitStateComputeMode; @@ -54,9 +65,12 @@ XE_HPG_CORETEST_F(ComputeModeRequirementsXeHpgCore, GivenVariousSettingsWhenComp pCsr->streamProperties.stateComputeMode.setProperties(false, 0u, 0u); LinearStream stream(buff, 1024); pCsr->programComputeMode(stream, flags, *defaultHwInfo); - EXPECT_EQ(sizeof(STATE_COMPUTE_MODE), stream.getUsed()); + EXPECT_EQ(cmdsSize, stream.getUsed()); auto pScmCmd = reinterpret_cast(stream.getCpuBase()); + if (isWARequiredOnSingleCCS) { + pScmCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), sizeof(PIPE_CONTROL))); + } EXPECT_EQ(testValue.zPassThreadLimit, pScmCmd->getZPassAsyncComputeThreadLimit()); EXPECT_EQ(testValue.pixelThreadLimit, pScmCmd->getPixelAsyncComputeThreadLimit()); @@ -72,11 +86,78 @@ XE_HPG_CORETEST_F(ComputeModeRequirementsXeHpgCore, GivenVariousSettingsWhenComp pCsr->streamProperties.stateComputeMode.setProperties(false, 0u, 0u); LinearStream stream(buff, 1024); pCsr->programComputeMode(stream, flags, *defaultHwInfo); - EXPECT_EQ(sizeof(STATE_COMPUTE_MODE), stream.getUsed()); + EXPECT_EQ(cmdsSize, stream.getUsed()); auto pScmCmd = reinterpret_cast(stream.getCpuBase()); + if (isWARequiredOnSingleCCS) { + pScmCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), sizeof(PIPE_CONTROL))); + } EXPECT_EQ(STATE_COMPUTE_MODE::Z_PASS_ASYNC_COMPUTE_THREAD_LIMIT_MAX_60, pScmCmd->getZPassAsyncComputeThreadLimit()); EXPECT_EQ(STATE_COMPUTE_MODE::PIXEL_ASYNC_COMPUTE_THREAD_LIMIT_DISABLED, pScmCmd->getPixelAsyncComputeThreadLimit()); EXPECT_FALSE(isValueSet(pScmCmd->getMaskBits(), FamilyType::stateComputeModeZPassAsyncComputeThreadLimitMask)); EXPECT_FALSE(isValueSet(pScmCmd->getMaskBits(), FamilyType::stateComputeModePixelAsyncComputeThreadLimitMask)); } + +XE_HPG_CORETEST_F(ComputeModeRequirementsXeHpgCore, givenComputeModeCmdSizeWhenLargeGrfModeChangeIsRequiredThenSCMCommandSizeIsCalculated) { + SetUpImpl(); + using STATE_COMPUTE_MODE = typename FamilyType::STATE_COMPUTE_MODE; + using PIPE_CONTROL = typename FamilyType::PIPE_CONTROL; + + auto cmdSize = 0u; + + overrideComputeModeRequest(false, false, false, false, 128u); + auto retSize = getCsrHw()->getCmdSizeForComputeMode(); + EXPECT_EQ(cmdSize, retSize); + + cmdSize = sizeof(STATE_COMPUTE_MODE) + sizeof(PIPE_CONTROL); + + overrideComputeModeRequest(false, false, false, true, 256u); + retSize = getCsrHw()->getCmdSizeForComputeMode(); + EXPECT_EQ(cmdSize, retSize); + + overrideComputeModeRequest(true, false, false, true, 256u); + retSize = getCsrHw()->getCmdSizeForComputeMode(); + EXPECT_EQ(cmdSize, retSize); +} + +XE_HPG_CORETEST_F(ComputeModeRequirementsXeHpgCore, givenCoherencyWithSharedHandlesWhenCommandSizeIsCalculatedThenCorrectCommandSizeIsReturned) { + SetUpImpl(); + using STATE_COMPUTE_MODE = typename FamilyType::STATE_COMPUTE_MODE; + using PIPE_CONTROL = typename FamilyType::PIPE_CONTROL; + + auto cmdsSize = 0u; + + overrideComputeModeRequest(false, false, true); + auto retSize = getCsrHw()->getCmdSizeForComputeMode(); + EXPECT_EQ(cmdsSize, retSize); + + overrideComputeModeRequest(false, true, true); + retSize = getCsrHw()->getCmdSizeForComputeMode(); + EXPECT_EQ(cmdsSize, retSize); + + cmdsSize = sizeof(STATE_COMPUTE_MODE) + (2 * sizeof(PIPE_CONTROL)); + + overrideComputeModeRequest(true, true, true); + retSize = getCsrHw()->getCmdSizeForComputeMode(); + EXPECT_EQ(cmdsSize, retSize); + + overrideComputeModeRequest(true, false, true); + retSize = getCsrHw()->getCmdSizeForComputeMode(); + EXPECT_EQ(cmdsSize, retSize); +} + +XE_HPG_CORETEST_F(ComputeModeRequirementsXeHpgCore, givenCoherencyWithoutSharedHandlesWhenCommandSizeIsCalculatedThenCorrectCommandSizeIsReturned) { + using STATE_COMPUTE_MODE = typename FamilyType::STATE_COMPUTE_MODE; + using PIPE_CONTROL = typename FamilyType::PIPE_CONTROL; + SetUpImpl(); + + auto cmdsSize = sizeof(STATE_COMPUTE_MODE) + sizeof(PIPE_CONTROL); + + overrideComputeModeRequest(false, false, false, false); + auto retSize = getCsrHw()->getCmdSizeForComputeMode(); + EXPECT_EQ(0u, retSize); + + overrideComputeModeRequest(false, false, false, true); + retSize = getCsrHw()->getCmdSizeForComputeMode(); + EXPECT_EQ(cmdsSize, retSize); +} diff --git a/shared/test/unit_test/xe_hpg_core/dg2/compute_mode_tests_dg2.cpp b/shared/test/unit_test/xe_hpg_core/dg2/compute_mode_tests_dg2.cpp index 30d5d316b7..d8141825eb 100644 --- a/shared/test/unit_test/xe_hpg_core/dg2/compute_mode_tests_dg2.cpp +++ b/shared/test/unit_test/xe_hpg_core/dg2/compute_mode_tests_dg2.cpp @@ -57,10 +57,10 @@ HWTEST2_F(ComputeModeRequirements, GivenProgramPipeControlPriorToNonPipelinedSta EXPECT_TRUE(pipeControlCmd->getConstantCacheInvalidationEnable()); EXPECT_TRUE(pipeControlCmd->getStateCacheInvalidationEnable()); - auto stateComputeModelCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), sizeof(PIPE_CONTROL))); - EXPECT_TRUE(isValueSet(stateComputeModelCmd->getMaskBits(), expectedBitsMask)); - expectedScmCmd.setMaskBits(stateComputeModelCmd->getMaskBits()); - EXPECT_TRUE(memcmp(&expectedScmCmd, stateComputeModelCmd, sizeof(STATE_COMPUTE_MODE)) == 0); + auto stateComputeModeCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), sizeof(PIPE_CONTROL))); + EXPECT_TRUE(isValueSet(stateComputeModeCmd->getMaskBits(), expectedBitsMask)); + expectedScmCmd.setMaskBits(stateComputeModeCmd->getMaskBits()); + EXPECT_TRUE(memcmp(&expectedScmCmd, stateComputeModeCmd, sizeof(STATE_COMPUTE_MODE)) == 0); } HWTEST2_F(ComputeModeRequirements, GivenMultipleCCSEnabledSetupThenCorrectCommandsAreAdded, IsDG2) { @@ -104,10 +104,62 @@ HWTEST2_F(ComputeModeRequirements, GivenMultipleCCSEnabledSetupThenCorrectComman EXPECT_TRUE(pipeControlCmd->getConstantCacheInvalidationEnable()); EXPECT_TRUE(pipeControlCmd->getStateCacheInvalidationEnable()); - auto stateComputeModelCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), sizeof(PIPE_CONTROL))); - EXPECT_TRUE(isValueSet(stateComputeModelCmd->getMaskBits(), expectedBitsMask)); - expectedScmCmd.setMaskBits(stateComputeModelCmd->getMaskBits()); - EXPECT_TRUE(memcmp(&expectedScmCmd, stateComputeModelCmd, sizeof(STATE_COMPUTE_MODE)) == 0); + auto stateComputeModeCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), sizeof(PIPE_CONTROL))); + EXPECT_TRUE(isValueSet(stateComputeModeCmd->getMaskBits(), expectedBitsMask)); + expectedScmCmd.setMaskBits(stateComputeModeCmd->getMaskBits()); + EXPECT_TRUE(memcmp(&expectedScmCmd, stateComputeModeCmd, sizeof(STATE_COMPUTE_MODE)) == 0); +} + +HWTEST2_F(ComputeModeRequirements, GivenSingleCCSEnabledSetupThenCorrectCommandsAreAdded, IsDG2) { + HardwareInfo hwInfo = *defaultHwInfo; + hwInfo.gtSystemInfo.CCSInfo.NumberOfCCSEnabled = 1; + + SetUpImpl(&hwInfo); + MockOsContext ccsOsContext(0, EngineDescriptorHelper::getDefaultDescriptor({aub_stream::ENGINE_CCS, EngineUsage::Regular})); + + getCsrHw()->setupContext(ccsOsContext); + + using STATE_COMPUTE_MODE = typename FamilyType::STATE_COMPUTE_MODE; + using FORCE_NON_COHERENT = typename STATE_COMPUTE_MODE::FORCE_NON_COHERENT; + using PIPE_CONTROL = typename FamilyType::PIPE_CONTROL; + + auto cmdsSize = sizeof(STATE_COMPUTE_MODE) + sizeof(PIPE_CONTROL); + char buff[1024] = {0}; + LinearStream stream(buff, 1024); + + auto expectedScmCmd = FamilyType::cmdInitStateComputeMode; + expectedScmCmd.setForceNonCoherent(STATE_COMPUTE_MODE::FORCE_NON_COHERENT_FORCE_GPU_NON_COHERENT); + auto expectedBitsMask = FamilyType::stateComputeModeForceNonCoherentMask | FamilyType::stateComputeModeLargeGrfModeMask; + + overrideComputeModeRequest(true, false, false, false, true); + + auto retSize = getCsrHw()->getCmdSizeForComputeMode(); + EXPECT_EQ(cmdsSize, retSize); + + getCsrHw()->programComputeMode(stream, flags, hwInfo); + EXPECT_EQ(cmdsSize, stream.getUsed()); + + auto startOffset = getCsrHw()->commandStream.getUsed(); + + HardwareParse hwParser; + hwParser.parseCommands(stream, startOffset); + + auto pipeControlIterator = find(hwParser.cmdList.begin(), hwParser.cmdList.end()); + auto pipeControlCmd = genCmdCast(*pipeControlIterator); + + EXPECT_TRUE(UnitTestHelper::getPipeControlHdcPipelineFlush(*pipeControlCmd)); + EXPECT_TRUE(pipeControlCmd->getUnTypedDataPortCacheFlush()); + + EXPECT_FALSE(pipeControlCmd->getAmfsFlushEnable()); + EXPECT_FALSE(pipeControlCmd->getInstructionCacheInvalidateEnable()); + EXPECT_FALSE(pipeControlCmd->getTextureCacheInvalidationEnable()); + EXPECT_FALSE(pipeControlCmd->getConstantCacheInvalidationEnable()); + EXPECT_FALSE(pipeControlCmd->getStateCacheInvalidationEnable()); + + auto stateComputeModeCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), sizeof(PIPE_CONTROL))); + EXPECT_TRUE(isValueSet(stateComputeModeCmd->getMaskBits(), expectedBitsMask)); + expectedScmCmd.setMaskBits(stateComputeModeCmd->getMaskBits()); + EXPECT_TRUE(memcmp(&expectedScmCmd, stateComputeModeCmd, sizeof(STATE_COMPUTE_MODE)) == 0); } HWTEST2_F(ComputeModeRequirements, GivenProgramPipeControlPriorToNonPipelinedStateCommandThenCommandSizeIsCalculatedAndCorrectCommandSizeIsReturned, IsDG2) { diff --git a/shared/test/unit_test/xe_hpg_core/dg2/hw_info_config_tests_dg2.cpp b/shared/test/unit_test/xe_hpg_core/dg2/hw_info_config_tests_dg2.cpp index 4c5c7723f4..612f8da86c 100644 --- a/shared/test/unit_test/xe_hpg_core/dg2/hw_info_config_tests_dg2.cpp +++ b/shared/test/unit_test/xe_hpg_core/dg2/hw_info_config_tests_dg2.cpp @@ -103,7 +103,10 @@ DG2TEST_F(HwInfoConfigTestDg2, givenProgramPipeControlPriorToNonPipelinedStateCo auto hwInfo = *defaultHwInfo; auto isRcs = false; - EXPECT_TRUE(hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs)); + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs); + + EXPECT_TRUE(isWARequiredOnMultiCCS); + EXPECT_TRUE(isWARequiredOnSingleCCS); } DG2TEST_F(HwInfoConfigTestDg2, givenProgramPipeControlPriorToNonPipelinedStateCommandWhenIsPipeControlPriorToNonPipelinedStateCommandsWARequiredIsCalledOnRcsThenTrueIsReturned) { @@ -114,7 +117,10 @@ DG2TEST_F(HwInfoConfigTestDg2, givenProgramPipeControlPriorToNonPipelinedStateCo auto hwInfo = *defaultHwInfo; auto isRcs = true; - EXPECT_TRUE(hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs)); + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs); + + EXPECT_TRUE(isWARequiredOnMultiCCS); + EXPECT_TRUE(isWARequiredOnSingleCCS); } DG2TEST_F(HwInfoConfigTestDg2, givenProgramPipeControlPriorToNonPipelinedStateCommandDisabledWhenIsPipeControlPriorToNonPipelinedStateCommandsWARequiredIsCalledOnRcsThenFalseIsReturned) { @@ -125,7 +131,10 @@ DG2TEST_F(HwInfoConfigTestDg2, givenProgramPipeControlPriorToNonPipelinedStateCo auto hwInfo = *defaultHwInfo; auto isRcs = true; - EXPECT_FALSE(hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs)); + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs); + + EXPECT_FALSE(isWARequiredOnMultiCCS); + EXPECT_TRUE(isWARequiredOnSingleCCS); } DG2TEST_F(HwInfoConfigTestDg2, givenHwInfoConfigWithMultipleCSSWhenIsPipeControlPriorToNonPipelinedStateCommandsWARequiredIsCalledOnCcsThenTrueIsReturned) { @@ -134,7 +143,10 @@ DG2TEST_F(HwInfoConfigTestDg2, givenHwInfoConfigWithMultipleCSSWhenIsPipeControl hwInfo.gtSystemInfo.CCSInfo.NumberOfCCSEnabled = 2; auto isRcs = false; - EXPECT_TRUE(hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs)); + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs); + + EXPECT_TRUE(isWARequiredOnMultiCCS); + EXPECT_TRUE(isWARequiredOnSingleCCS); } DG2TEST_F(HwInfoConfigTestDg2, givenHwInfoConfigWithMultipleCSSWhenIsPipeControlPriorToNonPipelinedStateCommandsWARequiredIsCalledOnRcsThenFalseIsReturned) { @@ -143,7 +155,34 @@ DG2TEST_F(HwInfoConfigTestDg2, givenHwInfoConfigWithMultipleCSSWhenIsPipeControl hwInfo.gtSystemInfo.CCSInfo.NumberOfCCSEnabled = 2; auto isRcs = true; - EXPECT_FALSE(hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs)); + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs); + + EXPECT_FALSE(isWARequiredOnMultiCCS); + EXPECT_TRUE(isWARequiredOnSingleCCS); +} + +DG2TEST_F(HwInfoConfigTestDg2, givenHwInfoConfigWithSingleCSSWhenIsPipeControlPriorToNonPipelinedStateCommandsWARequiredIsCalledOnCcsThenTrueIsReturned) { + const auto &hwInfoConfig = *HwInfoConfig::get(productFamily); + auto hwInfo = *defaultHwInfo; + hwInfo.gtSystemInfo.CCSInfo.NumberOfCCSEnabled = 1; + auto isRcs = false; + + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs); + + EXPECT_FALSE(isWARequiredOnMultiCCS); + EXPECT_TRUE(isWARequiredOnSingleCCS); +} + +DG2TEST_F(HwInfoConfigTestDg2, givenHwInfoConfigWithSingleCSSWhenIsPipeControlPriorToNonPipelinedStateCommandsWARequiredIsCalledOnRcsThenTrueIsReturned) { + const auto &hwInfoConfig = *HwInfoConfig::get(productFamily); + auto hwInfo = *defaultHwInfo; + hwInfo.gtSystemInfo.CCSInfo.NumberOfCCSEnabled = 1; + auto isRcs = true; + + const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig.isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs); + + EXPECT_FALSE(isWARequiredOnMultiCCS); + EXPECT_TRUE(isWARequiredOnSingleCCS); } DG2TEST_F(HwInfoConfigTestDg2, givenDg2WhenIsBlitterForImagesSupportedIsCalledThenTrueIsReturned) {