8814b6ac4f
fix: do not prefer image compression on xe_lpg for linux and WSL
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Related-To: HSD-18034872015
Signed-off-by: Jaroslaw Warchulski <jaroslaw.warchulski@intel.com >
2025-02-28 14:20:57 +01:00
ad968550e8
fix: separate isUsmPoolAllocatorSupported for host and device
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Related-To: NEO-12287, HSD-18041505773
Signed-off-by: Fabian Zwoliński <fabian.zwolinski@intel.com >
2025-02-17 11:47:34 +01:00
c2387954e9
fix: disable 3d and media sharing support on PVC
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Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com >
2025-02-14 17:37:05 +01:00
05977f6158
feature: add getMaxLocalSubRegionSize() to product helper
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Related-To: NEO-13954
Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com >
2025-02-06 15:20:34 +01:00
635f69e54a
fix: Configure scratch pages for debugger
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DG2 requires scratch pages on for debugger. Other platforms do not.
Related-to: NEO-13883
Signed-off-by: Brandon Yates <brandon.yates@intel.com >
2025-01-31 06:49:49 +01:00
7918b44a94
fix: apply 2MB alignment to large local memory allocations
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In this patch, we align up the allocation size to 2MB for all
allocations >= 2MB located in local memory.
2MB alignment support is defined by function:
`is2MBLocalMemAlignmentEnabled`
Related-To: NEO-12287
Signed-off-by: Fabian Zwoliński <fabian.zwolinski@intel.com >
2025-01-30 22:09:39 +01:00
a8779c2387
fix: report ZE_MEMORY_ACCESS_CAP_FLAG_CONCURRENT correctly
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At the moment the capability is returned only based on the value
returned by the `productHelper`, which is too liberal. The capability
must also consider the support reported by `memoryManager`. Only then
the support reported is aligned with actual logic of handling
USM-allocations.
Related-To: NEO-10040
Signed-off-by: Maciej Bielski <maciej.bielski@intel.com >
2025-01-29 00:17:38 +01:00
e00da808cb
feature: add logic to control secondaryContextsSupport in ProductHelper
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- product helper sets flag in GfxCoreHelper - this allows to control
secondary contexts support per product - not whole core family
Related-To: NEO-13789
Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com >
2025-01-25 06:43:56 +01:00
c0838e1f76
fix: Apply dispatch all for small TG only on BMG
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Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com >
2025-01-22 13:04:44 +01:00
112abeeeef
fix: don't adjust programmed per thread scratch size
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when adjusting scratch space size then adjust only allocation size
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com >
2025-01-10 11:35:50 +01:00
a3b6c1fa6d
fix: correct thread/eu ratio for scratch to Xe2
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Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com >
2025-01-09 22:42:36 +01:00
5862cbcb9f
refactor: add max local region size query
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Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com >
2024-11-22 17:33:22 +01:00
8797c326b6
refactor: Move isDummyBlitWaRequired function to release helper
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Signed-off-by: Filip Hazubski <filip.hazubski@intel.com >
2024-11-15 13:22:00 +01:00
67581f57a4
refactor: unify local dispatch size query
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Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com >
2024-11-15 10:00:53 +01:00
cb3b2134ab
refactor: unify programming of preferred slm size 4/n
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- remove xe hpg encode preferred slm size
- add dg2/mtl/arl release helper preferred slm array
- drop dg2 preproduction stepping values for preferred slm size
- remove obsolete product helper method
Related-To: NEO-12639
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com >
2024-10-07 14:28:23 +02:00
d6016e1b91
refactor: unify programming of preferred slm size 3/n
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- add shared implementation to encode preferred slm size
- add pvc release helper preferred slm array
- drop pvc preproduction steppings values for preferred slm size
- remove obsolete product helper method
Related-To: NEO-12639
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com >
2024-10-07 12:10:27 +02:00
bbffbd16a0
refactor: remove not needed code
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Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com >
2024-10-04 11:59:45 +02:00
6abc5eb1a1
fix: using releaseHelper to determine MTP enablement
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Related-To: NEO-12466
Signed-off-by: Andrzej Koska <andrzej.koska@intel.com >
2024-10-01 15:06:07 +02:00
b8fd1bda36
feature: use sysInfo helper to detect memory type
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Related-To: NEO-12807
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com >
2024-09-30 18:19:42 +02:00
3bd2befe74
refactor: indirect detection helpers, VC
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Allow for different required version for VC compiled kernels.
Define constant for detection disabled.
Related-To: NEO-12491
Signed-off-by: Dominik Dabek <dominik.dabek@intel.com >
2024-09-13 19:42:57 +02:00
571d703135
refactor: indirect detection helpers
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Check indirect detection version from igc header for JIT.
Move required version to its own method.
This allows for different required versions per platform.
Related-To: NEO-12491
Signed-off-by: Dominik Dabek <dominik.dabek@intel.com >
2024-09-11 14:49:54 +02:00
a54a3bf624
performance: Optimize heap handling when mitigate dc flush
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Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com >
2024-09-06 04:33:41 +02:00
dc84b163b5
Revert "performance: Optimize heap handling when mitigate dc flush"
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This reverts commit 9249c5c65ccompute-runtime-validation@intel.com >
2024-09-03 08:33:20 +02:00
9249c5c65c
performance: Optimize heap handling when mitigate dc flush
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Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com >
2024-09-02 18:12:19 +02:00
d3f32358e9
Revert "performance: Optimize heap handling when mitigate dc flush"
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This reverts commit 452f4b1dd1compute-runtime-validation@intel.com >
2024-08-31 06:03:18 +02:00
452f4b1dd1
performance: Optimize heap handling when mitigate dc flush
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Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com >
2024-08-30 10:54:54 +02:00
63528e70a7
Revert "performance: Optimize heap handling when mitigate dc flush"
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This reverts commit 1a8149e91ccompute-runtime-validation@intel.com >
2024-08-30 05:59:25 +02:00
1a8149e91c
performance: Optimize heap handling when mitigate dc flush
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Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com >
2024-08-29 17:03:55 +02:00
496012d82f
performance: Use copy buffer rect middle builtin
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Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com >
2024-08-28 15:32:00 +02:00
5aa5d40937
performance: Mitigate dc flush on LNL Windows
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Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com >
2024-08-28 13:35:17 +02:00
0b848a5fdb
fix: Don't use copy buffer rect middle builtin
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Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com >
2024-08-27 12:01:58 +02:00
ad0d6f5435
Revert "refactor: Add dc flush mitigation infrastructure"
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This reverts commit e4412e385acompute-runtime-validation@intel.com >
2024-08-27 02:35:06 +02:00
e4412e385a
refactor: Add dc flush mitigation infrastructure
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Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com >
2024-08-26 10:38:56 +02:00
c1a5fb089b
performance: Add copy buffer rect middle builtin
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Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com >
2024-08-22 10:30:17 +02:00
a4060013de
refactor: move CLOS-related steps from core- to product-helper
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Future HW will not support cache reservation uniquely for the whole
platform. Implementation of some functions may vary between products.
Related-To: NEO-10158
Signed-off-by: Maciej Bielski <maciej.bielski@intel.com >
2024-08-12 09:27:04 +02:00
e27efd701f
Revert "fix: correct calculating max subslice space"
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This reverts commit 67f2500c03compute-runtime-validation@intel.com >
2024-08-02 12:28:13 +02:00
67f2500c03
fix: correct calculating max subslice space
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computeMaxNeededSubSliceSpace is no longer needed as getHighestEnabledSubSlice
already determines maximum index from all enabled subslices
Related-To: NEO-12073
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com >
2024-08-01 16:38:24 +02:00
2d1b263e9a
Revert "refactor: remove redundant function computeMaxNeededSubSliceSpace"
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This reverts commit c0b96dcd6ecompute-runtime-validation@intel.com >
2024-08-01 03:54:56 +02:00
c0b96dcd6e
refactor: remove redundant function computeMaxNeededSubSliceSpace
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use GfxCoreHelper::getHighestEnabledDualSubSlice instead
Related-To: NEO-12073
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com >
2024-07-31 14:50:13 +02:00
f5d00b2616
feature: 2d-block-load-transpose query
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Implemented device property query API for determining
support capabilities regarding 2d-block-load-tranpose
features for which not all Intel devices support.
Related-To: NEO-11592
Signed-off-by: Jack Myers <jack.myers@intel.com >
2024-07-30 18:21:07 +02:00
9b3ccf73b7
refactor: host usm recycle
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Signed-off-by: Dominik Dabek <dominik.dabek@intel.com >
2024-07-23 16:20:21 +02:00
39ec7facee
performance: use BCS for transfers if CCS is busy
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Related-To: NEO-11501
Also, if device is iGPU, don't use staging buffers
in that case.
Signed-off-by: Szymon Morek <szymon.morek@intel.com >
2024-07-22 15:36:26 +02:00
6a11e8a077
fix: revert changes around zero-copy
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Related-To: NEO-12018
Signed-off-by: Szymon Morek <szymon.morek@intel.com >
2024-07-19 12:29:18 +02:00
0cb2a22c55
Revert "fix: correct number of slice count in configureHwInfoDrm"
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This reverts commit b597f47a70compute-runtime-validation@intel.com >
2024-07-19 04:35:03 +02:00
33ab962121
fix: adjust compression hint usage for ocl buffers
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Related-To: NEO-11989
Also, use zero-copy on lnl
Signed-off-by: Szymon Morek <szymon.morek@intel.com >
2024-07-18 18:24:48 +02:00
b597f47a70
fix: correct number of slice count in configureHwInfoDrm
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adjust slice count to proper value based on previously calculated
max slices and max subslice counts
Related-To: NEO-12073
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com >
2024-07-18 16:54:51 +02:00
85e708819a
fix: Add per product cache line size property
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Signed-off-by: Maciej Plewka <maciej.plewka@intel.com >
2024-07-18 12:47:47 +02:00
1d7ce005d7
refactor: extract common logic from wddm and drm product helpers
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Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com >
2024-07-17 11:03:02 +02:00
e3053121cb
Revert "refactor: extract common logic from wddm and drm product helpers"
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This reverts commit 585caab757compute-runtime-validation@intel.com >
2024-07-17 04:53:28 +02:00
585caab757
refactor: extract common logic from wddm and drm product helpers
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Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com >
2024-07-16 11:17:18 +02:00
