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36 Commits

Author SHA1 Message Date
Zbigniew Zdanowicz e201725dd5 Add dedicated map allocation 
Related-To: NEO-2917

Change-Id: Ieeca40f5faf29433a5c464d2c3ca3b8910695a9b
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2019-04-09 16:16:31 +02:00
Mateusz Jablonski 91a64c8518 Fix locking resource logic for enqueue read/write buffer call 
Change-Id: I261ed4904d617a2f4600ea2a5ec7fd34f534c191
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2019-04-09 13:16:59 +02:00
Mateusz Jablonski f76c0e84fb Don't copy compressed buffer on CPU 
Change-Id: I9c36ee8f23284286bb846fd9a0fd196733d0f8f9
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2019-04-03 13:15:41 +02:00
Jobczyk, Lukasz a025dc6985 Reverse logic of creating Memory Manager - part 6 
-Remove a redundant condition from the MemoryManager constructor

Change-Id: I4b6c56f30a19e77a7a20f68c6d85516aaa52d102
Signed-off-by: Jobczyk, Lukasz <lukasz.jobczyk@intel.com>
 2019-04-01 10:27:29 +02:00
Maciej Plewka 9e52684f5b Change namespace from OCLRT to NEO 
Change-Id: If965c79d70392db26597aea4c2f3b7ae2820fe96
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2019-03-26 15:48:19 +01:00
Filip Hazubski 8b57d28116 clang-format: enable sorting includes 
Include files are now grouped and sorted in following order:
1. Header file of the class the current file implements
2. Project files
3. Third party files
4. Standard library

Change-Id: If31af05652184169f7fee1d7ad08f1b2ed602cf0
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2019-02-27 11:50:07 +01:00
Hoppe, Mateusz 509ed273c4 Refactor Ults finding hardware commands 
- use CPU address for found dynamicStateHeap address in
StateBaseAddress command

Change-Id: I2d857c5a069f5a8f46169d2047cdb27efd3502b8
 2019-02-04 17:26:37 +01:00
Mateusz Jablonski 128bf4552f Remove debug flag ForceResourceLockOnTransferCalls 
Unlock locked resoures in freeGraphicsMemory method

Change-Id: I2baae7b7f9d8260f19a4b083849c5bf0d1a764f3
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2019-01-25 14:03:29 +01:00
Hoppe, Mateusz cbc4d349a8 Do not align down pointer passed to hostPtr allocation 
- do not align up hostPtr allocation size
- align BaseAddress programmed in SurfaceState to DWORD

Change-Id: Ic6d02e53fd13dda881f8eb845a131bffe4deb45c
 2019-01-08 21:21:34 +01:00
Venevtsev, Igor 73a63c7689 Fix Read/WriteBuffer for unaligned offsets 
Change-Id: I08d33e80243f41174f4629c8a611e286629d2e10
 2018-12-31 14:50:07 +01:00
Pawel Wilma 5094c630f7 Force resource locking on transfer calls 
Add debug variables to force resource locking on memory transfer calls
and to call makeResident() on mapVirtualAddress() call.

Change-Id: Ifa78d951fcb81812b10a98252bd414124dec9c74
 2018-12-14 12:25:28 +01:00
Dunajski, Bartosz 3ad33bf1b8 Allow Device creating multiple CSRs [3/n] 
Add CSR from Device to CommandQueue

Change-Id: Iaccf3c73d25e357242837677777d0513e81f520e
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2018-11-23 10:51:34 +01:00
Filip Hazubski c75dc23b6e Change HWCMDTEST_F() tests to HWTEST_F() where possible 
Change-Id: Ibfe147a12b53f832723f83809770e1b203159f8f
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2018-10-02 17:29:46 +02:00
Artur Harasimiuk 40146291ad Update copyright headers 
Updating files modified in 2018 only. Older files remain with old style
copyright header

Change-Id: Ic99f2e190ad74b4b7f2bd79dd7b9fa5fbe36ec92
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
 2018-09-20 18:02:35 +02:00
Maciej Dziuban 049ba5c625 Revert "Improve build time: command_queue tests" 
This reverts commit 76c78f017e.

Change-Id: Icb7eb473a17de5c072ba1833812fa084c4873465
 2018-09-10 14:54:55 +02:00
Maciej Dziuban 76c78f017e Improve build time: command_queue tests 
Change-Id: I22f7788bacd4a36488d5b6d56bae79b1f4788625
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
 2018-09-07 13:38:22 +02:00
Artur Harasimiuk 02b8055897 Revert "Improve build time: command_queue tests" 
This reverts commit 41811852db.

Change-Id: I74d4dba4aa0d840ddd8eeacf5b40503ff54b7c5a
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
 2018-08-27 19:17:52 +02:00
Dunajski, Bartosz 41811852db Improve build time: command_queue tests 
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
Change-Id: Ia80a8bfed28789c6c7a53478cdd56f883d61adf3
 2018-08-27 14:13:06 +02:00
Maciej Dziuban b91c14f70e Delete Device::getBuiltIns() 
Change-Id: I9d1968dfb2ba4a56020fd17152119add726106e1
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
 2018-08-22 16:54:53 +02:00
Zdanowicz, Zbigniew 00170eb998 Refactor ULTs checking DSH usage 
Change-Id: I02d1aece9a13c75508feef0af7a7322dd9fc7852
 2018-08-22 10:33:38 +02:00
Maciej Dziuban e0e48203d2 Move BuiltIns to ExecutionEnvironment 
Change-Id: Ib2a1b82cc7858c898bb32820aad106a01d1325ad
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
 2018-08-21 23:15:47 +02:00
Stefanowski, Adam 623314665b Set valid "max number of threads" in MEDIA_VFE_STATE 
Change-Id: Icd55fe6b5cae5a92021d2692fe09c19535e64121
 2018-07-19 15:17:17 +02:00
Zdanowicz, Zbigniew b27eee1f7a Refactoring ULTs around HW tests 
Splitting HW tests into CMD-unrelated HW tests
and CMD-related HW tests

Change-Id: Ifbdcabdd0d6f4082e976363a3d8bcd5e7a9ce6c1
 2018-05-18 11:45:45 +02:00
Maciej Dziuban 541735d932 L3 programming refactor 3/n 
- Add L3UltHelper to be able to tell if L3 config is programmable
- Run L3 config kernel tests according to its output

Change-Id: I55b76e2da325d28f62b0bde20250b68f02154ae2
 2018-05-10 12:43:10 +02:00
Dunajski, Bartosz 82c9acddde Improve including common reg_configs header 
Change-Id: I7fa22c2caffd0004269eb0d4f4fcdfd7621572af
 2018-04-26 14:48:50 +02:00
Artur Harasimiuk 75d497a9a9 separate BuiltinDispatchInfoBuilder from built_ins.h 
We don't need BuiltinDispatchInfoBuilder in every place where built ins
are used. specifically in .cpp files generated from kernel binary.

Change-Id: Ie739951cdc93873993f78ad14cee656122af51fd
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
 2018-04-19 12:32:13 +02:00
Mrozek, Michal de315db953 [24/n] Internal 4GB allocator. 
- Refactor tests for better maintenance
- Remove duplicated code.

Change-Id: I154cad43610497d2e1cabf99217820735d3868cd
 2018-03-30 09:12:08 +02:00
Mrozek, Michal 9bdf01468e [20/n] Internal 4GB allocator. 
- Switch to internal heap for kernel ISA allocations.
- remove IH from various functions
- remove IHState from CSR , IH is never dirty
- ISA is no longer copied on enqueue calls.

Change-Id: I0099cf2a9ebab6192ea03a74dd35f7da963fd5a5
 2018-03-28 16:07:26 +02:00
Mrozek, Michal 8254d6a081 Ensure that submissions are flushed prior to csr destruction. 
Change-Id: Ie04de561d3d295f40f55a19f01274d873d259abd
 2018-03-12 12:54:47 +01:00
Mrozek, Michal 1602fa5a88 [7/n] Internal 4GB allocator 
- rename getBase to getCpuBase
- change some test names accordingly.

Change-Id: I6fb2e4714298250147ea7766a916d7f5d62edc54
 2018-03-05 22:16:14 +01:00
Zdanowicz, Zbigniew 45dedb37f3 For HostPtr surfaces of enqueue calls use GPU address 
Change-Id: I67bf5076d23d43438f5e82c5cb6cbd3b9ed2f152
 2018-02-14 15:44:27 +01:00
mplewka 4db1e3af6a Check zeroCopy flag for r/w images/buffers 
Change-Id: I7047ae8458bdf3528d6014137522a37561d15ab6
 2018-02-08 13:55:44 +01:00
mplewka 2c2bbbcdbb Add support for zero-copy r/w buffer 
Change-Id: Ie9f3f2211d107eb338bd97692d36e9c7d7a0feab
 2018-01-22 09:40:51 +01:00
Mateusz Jablonski 13ac81f465 Change pipeline select programing 
- Program one PS with gpgpu selection and media sampler
- Program PS only when media sampler requirement changed
  or when preamble was not sent

Change-Id: I85ba3f74087733e79d048e120aeb8b4b04796e00
 2018-01-18 14:39:47 +01:00
Chodor, Jaroslaw 044fd1ab81 Fixing IntDescr programing for blocked cmd and MT 
Fixing InterfaceDescriptor programming for
blocked commands when MidThread preemption is
enabled
Additionally, fixing couple of tests that block
global preemption enabling in ULTs

Change-Id: I454c9608f8606f23d7446785ac24c7c7d8701ae0
 2018-01-17 12:19:07 +01:00
Brandon Fliflet 7e9ad41290 Initial commit 
Change-Id: I4bf1707bd3dfeadf2c17b0a7daff372b1925ebbd
 2017-12-21 00:45:38 +01:00