Commit Graph

46 Commits

Author SHA1 Message Date
Mateusz Jablonski 8a9d0a81df Move temporary and reusable allocation lists to command stream receiver
Change-Id: I40df6fe39b367e243e3710c5fdeaab3c85198d9d
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2018-10-11 15:32:12 +02:00
Dunajski, Bartosz 73b2e947a5 Multiple TimestampPackets handling
Change-Id: Ia5936c3d0a34b892aa4444026a5aebc681f126c2
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2018-10-05 01:54:35 +02:00
Mrozek, Michal 070bbf4033 Optimize enqueue kernel tests.
- Switch to non param fixture for tests not requiring different params
- Add limited param set for tests requiring param fixture
- this decreases total test count by 100 while keeping the same scope.

Change-Id: Ic10a378d3eb7a2d06114435a9bd9652756945574
2018-09-20 14:56:34 +02:00
Dunajski, Bartosz b74280beb6 Check EnableTimestampPacket debug variable once and set as CSR mode
Change-Id: Ia6e7caa96f3b46b30590fb46a1fb37fa153adeb4
2018-09-06 11:19:02 +02:00
Dunajski, Bartosz 570c0843ef Handle TimestampPacketNode residency
Change-Id: I1769d67426ca704b600931b58d3f505bef0e893d
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2018-08-30 11:53:56 +02:00
Dunajski, Bartosz 41914d3058 Make enqueue blocking if parent kernel requires aux translation
Change-Id: I678e1045d84f15e30223a99438bbb7057e172cff
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2018-08-29 19:33:00 +02:00
Maciej Dziuban b91c14f70e Delete Device::getBuiltIns()
Change-Id: I9d1968dfb2ba4a56020fd17152119add726106e1
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
2018-08-22 16:54:53 +02:00
Zdanowicz, Zbigniew 00170eb998 Refactor ULTs checking DSH usage
Change-Id: I02d1aece9a13c75508feef0af7a7322dd9fc7852
2018-08-22 10:33:38 +02:00
Maciej Dziuban e0e48203d2 Move BuiltIns to ExecutionEnvironment
Change-Id: Ib2a1b82cc7858c898bb32820aad106a01d1325ad
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
2018-08-21 23:15:47 +02:00
Dunajski, Bartosz 931b462ee1 Disable NonAux to Aux translation for Parent Kernel
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
Change-Id: I863608fe3652e7e777a1e841d79b5b56e7362a3f
2018-08-21 15:12:25 +02:00
Mrozek, Michal c7c2e7b83d Limit the amount of memory allocations in tests.
Change-Id: Ia41cde4fe4a42d6a586faa265aba295e61ba7d15
2018-08-20 11:01:49 +02:00
Lukasz Towarek 95e28faca0 Fix division by zero in enqueueKernel
Change-Id: I8e7d3db39805133a5af545e65a94fb19433a2a41
2018-08-14 09:02:17 +02:00
Dunajski, Bartosz 6ca84c278a Aux translation [3/n]: Dispatch AuxTranslation builtin when required
Change-Id: I9bd0294de7980ac01ebb3c2d696eba6fd6a456ec
2018-08-13 12:15:30 +02:00
Mrozek, Michal 1f3274e3dc Refactor some tests to not create csr twice.
- There is no need to create command stream receiver twice.

Change-Id: Ic47e7460e608625c31ab0652ad269c08f45c2250
2018-08-10 16:34:27 +02:00
Mrozek, Michal 1599ea800e Pass execution environment to command stream receiver.
Change-Id: I598f67f8b005b5ce8249b638e080657eb6dc3547
2018-08-08 17:10:39 +02:00
Dunajski, Bartosz b4f53fdfa7 Pick applicable buffers for aux translation
Change-Id: I60a28cd9e0dec61120b1ae5c42dfe0cb852eb387
2018-08-08 09:23:51 +02:00
Dunajski, Bartosz ec6f0f9f86 Aux translation [1/n]
- Mark Kernel for aux translation
- Initial implementation of dispatchAuxTranslation for future use

Change-Id: Ifca1c9a893876eecc5678cdc4f564b2bfcae959a
2018-08-07 09:07:25 +02:00
Mateusz Jablonski 9ae4f390d1 Remove command queue, completion stamp and device from mem obj
Remove setCompletionStamp function from Surface

Change-Id: I25f3040a91892495e55cb4924f1538276de6264e
2018-08-01 16:17:13 +02:00
Stefanowski, Adam 623314665b Set valid "max number of threads" in MEDIA_VFE_STATE
Change-Id: Icd55fe6b5cae5a92021d2692fe09c19535e64121
2018-07-19 15:17:17 +02:00
Stefanowski, Adam 70e85be96a Refactor ThreadArbitrationPolicy definitions
Change-Id: Ia5d9d3b915b14a1ed6c8dd8d7e7c38dab674b6f2
2018-07-09 16:55:22 +02:00
Zdanowicz, Zbigniew b27eee1f7a Refactoring ULTs around HW tests
Splitting HW tests into CMD-unrelated HW tests
and CMD-related HW tests

Change-Id: Ifbdcabdd0d6f4082e976363a3d8bcd5e7a9ce6c1
2018-05-18 11:45:45 +02:00
hjnapiat eedde057ea Minor refactoring of CommandComputeKernel class
- class cannot operate without kernel object
- improved ULTs

Change-Id: I4d1a6c3685f3908ce07154605aea649cae349d27
2018-05-14 12:26:46 +02:00
Mrozek, Michal 621a2dfcd1 [34/N] Internal 4GB allocator.
- Change dirty state helpers to work on IndirectHeaps.
- Instead of comparing size in bytes and cpu pointers, compare gpu base
address and size of the heap in pages
- That allows to not have dirty flag for heaps that are coming from 4GB
allocator.

Change-Id: I0ff81e3c0945b32e4f872a100cd10b332b27ed24
2018-05-12 16:01:30 +02:00
mplewka 2bc2869fe1 Refactor ult's for preemption enabling part 2
Change-Id: If8e335e87f3a78d35cab12a17880fb1922d479f5
2018-05-10 13:12:03 +02:00
Maciej Dziuban 541735d932 L3 programming refactor 3/n
- Add L3UltHelper to be able to tell if L3 config is programmable
- Run L3 config kernel tests according to its output

Change-Id: I55b76e2da325d28f62b0bde20250b68f02154ae2
2018-05-10 12:43:10 +02:00
Mrozek, Michal 34ff5852eb Add capability to csr to allow N:1 aggregation when ooq is created.
- This allows applications to force the N:1 aggregation by creating out
of order queue.
- That switches csr to N:1 submission model where commands from multiple
command streams may be aggregated.
- That forces scenarios returning an event to be aggregated as well.

Change-Id: I8fd8d7f88bb2665234ee90870133120b206710a8
2018-04-26 15:41:20 +02:00
Dunajski, Bartosz 82c9acddde Improve including common reg_configs header
Change-Id: I7fa22c2caffd0004269eb0d4f4fcdfd7621572af
2018-04-26 14:48:50 +02:00
Mrozek, Michal 8d2df3c332 Move indirect heaps from command queues to csr.
-This is required to enable N:1 submission model.
-If heaps are coming from different command queues that always
mean that STATE_BASE_ADDRESS needs to be reloaded
-In order to not emit any non pipelined state in CSR, this change
moves the ownership of IndirectHeap to one centralized place which is
CommandStreamReceiver
-This way when there are submissions from multiple command queues then
they reuse the same heaps, therefore preventing SBA reload

Change-Id: I5caf5dc5cb05d7a2d8766883d9bc51c29062e980
2018-04-26 14:05:40 +02:00
Pawel Wilma a0c044e6d2 Extend batch buffer flattening in AubCSR to BatchedDispatch mode
- batch buffer flatening in batched mode
    - added MI_USER_INTERRUPT command
    - added GUC Work Queue Item

Change-Id: I35142da34b30d3006bb4ffc1521db7f6ebe68ebc
2018-04-26 12:45:02 +02:00
Mrozek, Michal ce8c44cae3 Add check for local work group size in clEnqueueNDRangeKernel call.
- Incoming local work group size cannot exceed device capabilities.

Change-Id: I89a7503155c71443e3ebc630debb5d5b466c6cb5
2018-04-20 08:16:16 +02:00
Artur Harasimiuk 75d497a9a9 separate BuiltinDispatchInfoBuilder from built_ins.h
We don't need BuiltinDispatchInfoBuilder in every place where built ins
are used. specifically in .cpp files generated from kernel binary.

Change-Id: Ie739951cdc93873993f78ad14cee656122af51fd
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
2018-04-19 12:32:13 +02:00
mplewka 079f94cd2d Refactor ult for preemption enabling
Refactoring in ULTs around preemption:
    -refactoring ULTS to not fail with default preemption mode
    -fixing ULT memory leaks observed after enabling preemption
    -mocking getSipKernel in ULTs (to minimize ULT execution time)

Change-Id: I194b56173d7cb23aae94eeeca60051759c817e10
2018-04-16 12:55:30 +02:00
Mrozek, Michal de315db953 [24/n] Internal 4GB allocator.
- Refactor tests for better maintenance
- Remove duplicated code.

Change-Id: I154cad43610497d2e1cabf99217820735d3868cd
2018-03-30 09:12:08 +02:00
Mrozek, Michal 9bdf01468e [20/n] Internal 4GB allocator.
- Switch to internal heap for kernel ISA allocations.
- remove IH from various functions
- remove IHState from CSR , IH is never dirty
- ISA is no longer copied on enqueue calls.

Change-Id: I0099cf2a9ebab6192ea03a74dd35f7da963fd5a5
2018-03-28 16:07:26 +02:00
Mrozek, Michal 1602fa5a88 [7/n] Internal 4GB allocator
- rename getBase to getCpuBase
- change some test names accordingly.

Change-Id: I6fb2e4714298250147ea7766a916d7f5d62edc54
2018-03-05 22:16:14 +01:00
Dunajski, Bartosz 1fce275542 Remove forced DC flush and disabled out of order execution for shared objects
Change-Id: I0de86c3d5af488a347e83858f5dddbac2ef53c17
2018-03-05 09:45:18 +01:00
Mrozek, Michal 3da9df23a9 Flush DC in case shared objects are used.
- Due to use cases where one shared buffer may be mapped to multiple CL
buffers we need to flush DC between enqueues.

Change-Id: I05d7f844afe31d52a0004f5e2e5efa776f9dadbe
2018-02-26 15:51:06 +01:00
Mrozek, Michal acb044dce3 Fix DC flush programming in non concurrent scenarios.
-If out of order flag was disabled then pipe control was not having dc flush.
-This could led to a batch buffer that doesn't end with dc flush.
-This change adds differentiation between pipe controls that may be erased and
pipe controls that are used as a part of epilogue command

Change-Id: Ic9c970c75c89ff524a0e40506eff6dd097760145
2018-02-15 09:42:11 +01:00
Mrozek, Michal b5dab07aa2 Do not allow out of order execution for shared objects.
Change-Id: I2dbbd8f09485bd894774eb2c4548326475a41221
2018-02-12 10:36:23 +01:00
Mrozek, Michal 6bb83fb95a Do not noop pipe controls if call is returning event on IOQ.
-For in order queue application can have fine grain granularity of completion
-For out of order queue application wants to execute workloads concurrently
-This change disables pipe control nooping for ioq calls when event returned.

Change-Id: Iaeaf677f768f7434b2efa1842b50653ab80777ad
2018-02-09 11:57:44 +01:00
Mateusz Jablonski ea021f8d69 Cmake refactor part 1: fix dependencies with including os_inc.h
Remove some not needed includes

Change-Id: I158ad663ccfcec4822e3768df9d05090c5e096f9
2018-02-08 09:40:40 +01:00
Mrozek, Michal d8f2142faa Enable out of order execution for all submissions.
- This change enabled multiple independent command queues to execute
concurrently without stalling pipe controls in between
- This change removes L3 flushes between kernels
- Dependencies between commands are resolved via task level mechanism
- Out of order queues are not changing task level between submissions
- In order queues are increasing task level between submissions
- Whenever task level changes there is pipe control with cs stall emitted
between GPGPU_WALKERs

Change-Id: I558653b296424e4775d060df3072e2a50684b715
2018-02-08 08:22:04 +01:00
Mrozek, Michal 28758fc336 [2/n] Optimize CPU code
-Do not inc/dec reference count for flush stamps while used only for
update
-FlushStamp doesn't need to be atomic,replace with atomic bool flag
to prevent usage while uniinitialized
-Clean not needed private new

Change-Id: Idad2b318f988de1e7af7642047c67f931e9772aa
2018-02-05 11:02:17 +01:00
Mateusz Jablonski 13ac81f465 Change pipeline select programing
- Program one PS with gpgpu selection and media sampler
- Program PS only when media sampler requirement changed
  or when preamble was not sent

Change-Id: I85ba3f74087733e79d048e120aeb8b4b04796e00
2018-01-18 14:39:47 +01:00
Chodor, Jaroslaw 044fd1ab81 Fixing IntDescr programing for blocked cmd and MT
Fixing InterfaceDescriptor programming for
blocked commands when MidThread preemption is
enabled
Additionally, fixing couple of tests that block
global preemption enabling in ULTs

Change-Id: I454c9608f8606f23d7446785ac24c7c7d8701ae0
2018-01-17 12:19:07 +01:00
Brandon Fliflet 7e9ad41290 Initial commit
Change-Id: I4bf1707bd3dfeadf2c17b0a7daff372b1925ebbd
2017-12-21 00:45:38 +01:00