Commit Graph

62 Commits

Author SHA1 Message Date
b98b51b0d9 Move ptr.h to core folder
Change-Id: Icf0db7c767b2b1ea44fccc02b135f0f6c1f78c8f
Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
2019-05-29 00:11:34 -07:00
972a79aaae Reduced a scope of the lock for AUB file stream
Related-To: NEO-2747

Change-Id: Ic164900f5898df35af74ccff9c31f8296dcf12fd
2019-05-13 08:50:04 +02:00
ee2e93c505 Add missing locks to functions operating on AUB file stream
Related-To: NEO-2747

Change-Id: I9efacbaf6d7894943f3abb6ebe2634ac34fc3d04
Signed-off-by: Milczarek, Slawomir <slawomir.milczarek@intel.com>
2019-04-19 13:15:42 +02:00
381ccfc0aa AUB capture with AubStream to support image dumps
Related-To: NEO-2717

Change-Id: I448627cc40776eadacaefaa321500a3cf5ff3593
Signed-off-by: Milczarek, Slawomir <slawomir.milczarek@intel.com>
2019-04-08 17:28:14 +02:00
4b2bb188b7 Add support for Gen11 platform
Related-To: NEO-2388

Change-Id: I4da92efe7f875f409cd62519a31ed4509b55bda7
Signed-off-by: Jacek Danecki <jacek.danecki@intel.com>
2019-04-05 14:28:55 +02:00
96db96fcb4 Add support for buffer dumps in BIN and TRE format
Change-Id: Ib7e59fd6812ca6adcb2dfc1defa74008fee17ec9
Signed-off-by: Milczarek, Slawomir <slawomir.milczarek@intel.com>
2019-03-27 13:04:30 +01:00
9e52684f5b Change namespace from OCLRT to NEO
Change-Id: If965c79d70392db26597aea4c2f3b7ae2820fe96
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2019-03-26 15:48:19 +01:00
d9d55e9a4d Avoid false-positive memory leak on reassign of global var
We can step into false-positive memory leak if we reassign global variables
which assume memory allocations, for example std::string. Our unit tests has
embedded memory leak detector which gets inited/destroyed somewhere in the
middle of the test run. Hence allocations/deallocations done before/after its
active livetime will be transparent for it.

This particular case reassigned std::string global variable to the same value.
Apperantly my version of libstdc++ (the one on CentOS 7) did not recognize
that input/output string size is actually the same.

Signed-off-by: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>

https://github.com/intel/compute-runtime/pull/144

Change-Id: Iaab42588f59691d3085a4f8879d902076dcee0fb
2019-03-20 07:49:02 +01:00
49c428d1ff AUB allocation dumps with pollForCompletion
Change-Id: I610a56d7b8d1b6f1f0d6029ce6d2e62742885698
Signed-off-by: Milczarek, Slawomir <slawomir.milczarek@intel.com>
2019-03-15 16:13:31 +01:00
669d19297c Extended criteria for writable buffer with other buffer types
Change-Id: I1911bb87b115a517938ef4d4ca5ae66d2d98e178
Signed-off-by: Milczarek, Slawomir <slawomir.milczarek@intel.com>
2019-03-14 11:07:14 +01:00
395e79fee8 Add support for many GMMs in Graphics Allocation
Change-Id: I955b8dd50b502f91700c5529d0a0a291632aa157
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2019-03-13 15:44:45 +01:00
8b57d28116 clang-format: enable sorting includes
Include files are now grouped and sorted in following order:
1. Header file of the class the current file implements
2. Project files
3. Third party files
4. Standard library

Change-Id: If31af05652184169f7fee1d7ad08f1b2ed602cf0
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2019-02-27 11:50:07 +01:00
63ebe252eb Aubstream header update
Change-Id: I68573223715e5cbb6a308b88d9bae35741ef9984
2019-02-26 19:27:36 +01:00
278bb83c56 Enable AUB sub-capture in AubStream captures (1/n)
Change-Id: I6bd0605d06cf4dc3937e2dbeba7ed7037ae91476
2019-02-21 22:40:40 +01:00
802eb37394 Revert "Pass HardwareInfo to AubHelper::checkPTEAddress()"
Delete AubHelper::checkPTEAddress()

This reverts commit aa587b3bc5.

Change-Id: I32b90ce7dddfd2347586b2c47b9114b45cced8ab
2019-02-19 11:51:35 +01:00
aa587b3bc5 Pass HardwareInfo to AubHelper::checkPTEAddress()
Change-Id: Ie5370b52eb79a8d118bd8033a335dc1319e93be1
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
2019-02-19 08:37:58 +01:00
947794f166 Fix for setting context flags in AubDump
Change-Id: Ia5fba17aac19fbcbfa6676557d1af0889f538b90
2019-02-07 16:28:53 +01:00
4943c102cd Add streamMode parameter passed to AubManager
Change-Id: If074579fdf17c7709c33d08ccdfbf9dc80e3adc8
2019-02-05 18:31:16 +01:00
758d91f406 Set TbxServerIp and TbxServerPort from DebugVariables
Change-Id: Ib9ba3efb3a196c1bdf5f4345b36fe35da159c29c
2019-02-01 09:07:47 +01:00
b11e0825c9 AUB capture with support for allocation dumps
Change-Id: I90a2b75043c33af92e4557be37cde4b9699582c6
2019-01-28 21:20:08 +01:00
21f855b719 AubStream update (1/n)
Change-Id: I6579e7af2015493490c5edcc413dcb2e6c804b9f
2019-01-22 12:19:21 +01:00
9036882d11 Refactoring of additional MMIO registers in AubDump
Change-Id: I97c0cc25aa24c6abcff4ba7469d6a6e3f0c12b86
2019-01-16 11:16:54 +01:00
ba2b8f05fc AubManager to accept memory bank size in bytes
Change-Id: Ie98cb7c0c0eaf93c9a2312aa87428173421609a9
2019-01-02 15:56:36 +01:00
38fb8cd9c3 Refactor mmio programming.
Change-Id: I2ec9294b800adcd537f03d69fd4ba4e015e8db7a
2018-12-03 14:40:00 +01:00
cd5f85052e AUB CSR with a separate function to submit batch buffer
Move code related to batch buffer submission from flush to dedicated function
Add parameter to pass aub file name from AubCenter to AubManager

Change-Id: I20abb3c8bd92114b3bc9caa2a6291dc1bbddad2a
2018-11-25 18:02:25 -08:00
ac15e7f3ac Unify expectMemory in Aubs and introduce expectMemoryNotEqual
Change-Id: Ifd52f2d3ad3badf6ea9dac2c2b9873a40efa8482
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2018-11-19 10:39:45 +01:00
9345b25352 AUB services update
Change-Id: I451794f78fa0379c3f5f8cd7a913f350d0decb3c
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2018-11-16 11:08:47 +01:00
0942edd6af Update aub_stream headers
- pass hwInfo and localMemoryEnabled to AubCenter ctor
- initialize AubCenter in Platform:intialize() when Device is
 created - only when CSR is not CsrHw
- move aub_center files to runtime/aub directory

Change-Id: Iceb4bf1cb2bb55b42d438502cca667a449f11411
2018-11-13 18:09:30 +01:00
aa18a62d70 A partial unification of AUB and TBX CSR classes
This commit moves initialization of global MMIOs from AUB CSR to Simulated CSR

Change-Id: I93a612d4f0c82e7135287f6508870190790141bc
2018-11-10 13:12:22 -08:00
ce75767ca3 Add AUB registry key to override MMIO offset value
Change-Id: Iac3bf9074e544a03e38fc437d7b21ea478d9cc5d
2018-11-03 00:33:50 +01:00
e6b93941ee Add aub_stream headers
Change-Id: I4d9420210e2a06d8a36abc0cf272901514ff3547
2018-11-02 14:29:45 +01:00
7319023b0f Add capability to use malloc for Heap32 base.
- shift page tables to lower bits

Change-Id: I54dcba72255215cf5be75ba425fc27727b0bfd98
2018-10-25 16:20:00 +02:00
d44507708c Context creation flags in AubDump
Change-Id: Ia9651d37fa716351728633f0bee5b0eae98e758f
2018-10-24 15:56:22 +02:00
eb9d720788 Add PTE address check
Change-Id: I00cdf828009a347a93eb0448bf678b670d287304
2018-10-15 13:06:20 +02:00
130a7ac8b8 Delete TypeSelector helper
Change-Id: Iff5fe62d31fa7b07658cfcf81ebd2c12d47e2b3b
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
2018-10-08 13:18:36 +02:00
a73801097f Change LRCA initialization
- program Debug register

Change-Id: I9993263b94fac0c56126f550fe174792dba6744b
2018-10-04 03:43:40 +02:00
ee797c2f14 Multiple AUB CSRs to operate on a single file stream
This commit introduces AUB stream provider class to produce
a single file stream in multi device scenarios with multiple AUB CSRs.

Change-Id: Id70e0d680459d34f4291b9e56aa39d960f025ac6
2018-09-23 05:41:00 +02:00
a470aa2072 Get AddressSpace to expectMemory from page table entry bits
Change-Id: I1aacdf98f436261b523765e0ca591e8d8333274e
2018-09-21 16:44:55 +02:00
40146291ad Update copyright headers
Updating files modified in 2018 only. Older files remain with old style
copyright header

Change-Id: Ic99f2e190ad74b4b7f2bd79dd7b9fa5fbe36ec92
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
2018-09-20 18:02:35 +02:00
c39f9c0c66 Add addressSpace to AubFileStream::expectMemory
- addressSpace can be passed as argument from layers above
where address space is known

Change-Id: If9075dde4e207296df91b46eccecd0b5fa183aa9
2018-09-20 15:23:15 +02:00
619d2217cb Pass AubHelper to reserveAddressPPGTT().
- get PageTable entry data hints and address space from AubHelper
based on local memory flag
- add enableLocalMemory flag in CSR HW

Change-Id: I061bda62be8da55d52cff48ecddcf26c4212dc67
2018-09-17 18:48:06 +02:00
be4c2cca60 AUBDump: Move PPGGT entries to lower physical memory (starting BIT31)
- 1GB remaining for regular allocations in AubDump

Change-Id: I9dcc7a6f0c495ed95622cf6d5ec366af06bbf350
2018-09-12 12:48:33 +02:00
991bbddeba Add function to get Page Table entry bits
This commit adds a helper function to get Page Table entry bits
and control a configuration of first levels page walks (non-PTE).

Change-Id: I85666ffae8e89a193d1ac4a065c2b84b814d47ec
2018-09-11 14:10:42 +02:00
23d66b6984 Add dedicated method for getting hint for AubDump memory write
Change-Id: I5282d3004e61dde4bda1fd0e0c1acf9fe94caca0
2018-08-21 10:28:59 +02:00
16d04fd276 AUB subcapture to read file name from outside and write into several files
Add a capability for AUB subcapture feature to dump into several files
and read file name from the outside (via regkey and env variable).

Change-Id: I2d5f7945cfbc740b0316fe23b8c5ae9fd698ac57
2018-07-14 13:10:35 +02:00
1fda1331c0 AUB CSR to flush file stream on every enqueue call
This commit adds an explicit flush on AUB file stream to CSR flush method.

Change-Id: Ib491718dba6c7b4a5b1e173111830bd3ab72a3d0
2018-07-05 16:12:42 +02:00
c238a4d31e Add support for Cannon Lake (Gen10) platform
Change-Id: I0e63960887cdae9ba74c1ba91ad27101e22b458a
2018-06-25 15:48:12 +02:00
fb10f666e9 AUB CSR: Ensured PTE bits be set correctly for Global GTT
This commit fixes the issue with setting reserved bits in PTE for GGTT.

Change-Id: I08582e20914419a3363c9e61085dcf03ba355a61
2018-06-21 22:23:01 +02:00
75ab0c6fe1 Switch clang-format to 6.0
Change-Id: Id96d1f47fb3d479d10d1022f1259dc030a148192
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
2018-06-14 09:45:00 +02:00
36621b2488 Use product aub device id and make it configurable by using debug flag
Change-Id: Ie65eea0f72497ef68e805ad438f4f53df731d304
2018-06-06 17:09:21 +02:00