Commit Graph

5924 Commits

Author SHA1 Message Date
293858320e Revert "performance: Fill reusable allocation list on xe and later"
This reverts commit 15934ceb43.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2024-03-02 07:09:45 +01:00
52430762ac fix: cl_cache L0 env vars + refactor code structure
Added support for new Compiler Cache
environment variables in Level Zero.

Moved
`opencl/source/compiler_interface/default_cache_config.cpp`
`level_zero/core/source/compiler_interface/default_cache_config.cpp`
to shared directory
`source/compiler_interface/default_cache_config.cpp`

Switched enabling cache by default from per OS to per API.
Changed default state of cl_cache in Level Zero to disabled.

Related-To: NEO-10045
Signed-off-by: Fabian Zwolinski <fabian.zwolinski@intel.com>
2024-03-01 17:35:08 +01:00
51ae76a25f refactor: improve handling of in-order atomic signaling
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2024-03-01 15:59:25 +01:00
bd6925d51a refactor: Exclude thread dispatch algorithm for overdispatch to function
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2024-03-01 15:04:04 +01:00
a8fbed6120 feature: enable dummy blit WA for PVC
Related-To: NEO-9996
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2024-03-01 14:04:46 +01:00
ea2ad550a1 refactor: improve handling duplicated in-order host storage
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2024-03-01 13:54:28 +01:00
80aa55a3cb fix: don't program dummy blit prior to MI_FLUSH_DW without postsync
add missing dummy blits before MI_FLUSH_DW with postsync

Related-To: NEO-9996
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2024-03-01 12:36:13 +01:00
6751d19c19 fix: decanonize pointer to match GPU heap address space
* `zeVirtualMemReserve` `pStart` address may be passed in a canonizated form.

Resolves: NEO-10086

Signed-off-by: Kozlowski, Marek <marek.kozlowski@intel.com>
2024-03-01 12:18:11 +01:00
bbe1043f08 feature: initial support for pooling in-order counter allocations
Related-To: NEO-10507

Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2024-03-01 12:08:02 +01:00
4baee71974 refactor: add out cmd argument to semaphore wait encoder
Related-To: NEO-10065

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2024-03-01 11:43:36 +01:00
15934ceb43 performance: Fill reusable allocation list on xe and later
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2024-03-01 09:41:19 +01:00
5fce046877 Revert "fix: don't program dummy blit prior to MI_FLUSH_DW without postsync"
This reverts commit d796fb559d.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2024-03-01 01:43:35 +01:00
e5db84f370 performance: Use GEMCreateExt when allocate by KMD
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2024-02-29 18:01:55 +01:00
409e19a832 performance: Enable cmd buffer preallocation per CmdQ on xe and later
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2024-02-29 17:41:58 +01:00
00964275fb fix: create preemption allocation for Root Csr
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2024-02-29 16:46:24 +01:00
06e9c7f79f Revert "fix: Add ATS-M device id"
This reverts commit 588921ed9b.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2024-02-29 14:34:40 +01:00
d796fb559d fix: don't program dummy blit prior to MI_FLUSH_DW without postsync
add missing dummy blits before MI_FLUSH_DW with postsync

Related-To: NEO-9996
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2024-02-29 13:30:09 +01:00
a27dafd2e1 fix: cl_cache store binary and debug data in one file
Related-To: NEO-10045
Signed-off-by: Fabian Zwolinski <fabian.zwolinski@intel.com>
2024-02-29 10:13:15 +01:00
676644bc50 performance: Enable internal heap preallocation on xe and later
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2024-02-28 17:58:52 +01:00
0fcc67fba9 refactor: Change scope of product helper test
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2024-02-28 15:52:25 +01:00
39a44628a3 performance: Enable timestamp wait for queues on xe and later
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2024-02-28 14:26:59 +01:00
d1dd34d0c7 performance: Enable timestamp wait for events on xe and later
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2024-02-28 14:18:14 +01:00
64232ec370 fix: choose proper csr for low priority immediate command lists
Resolves: NEO-10168

Signed-off-by: Michal Mrozek <michal.mrozek@intel.com>
Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
2024-02-28 12:45:02 +01:00
588921ed9b fix: Add ATS-M device id
Add device id 0x56C2

Signed-off-by: Hazubski, Filip <filip.hazubski@intel.com>
2024-02-28 11:46:55 +01:00
ffecca86ac feature: brand string update
Related-To: NEO-7929

Updating device brand strings
Based on public support in Windows driver 31.0.101.5252
https://www.intel.com/content/www/us/en/download/785597/

Signed-off-by: ocldev <ocldev@intel.com>
2024-02-28 10:52:27 +01:00
bf9805b0bb fix: override reset_stat IOCTL macro for prelim
Modified to return DRM_IOCTL_I915_GET_RESET_STATS of prelim headers
as the macro values used for non-prelim is different from the prelim
value due to sizeof() embedded in _IOWR()

Related-To: GSD-5673
Signed-off-by: Young Jin Yoon <young.jin.yoon@intel.com>
2024-02-28 10:09:27 +01:00
c3d884e548 test: improve test timeout configuration
Allow custom values for different test types, i.e. ULT, AUB, etc. can
have custom timeout by using e.g.: NEO_{ULT,AUB,...}_ITERATION_MAX_TIME.
Old behavior with reading NEO_ULT_ITERATION_MAX_TIME for each test type
is preserved but new envirnoment variable has precedence.

Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
2024-02-28 09:05:29 +01:00
fa4b737326 feature: Implement metadata attaching for vm_bind in xe
Related-to: NEO-9674

Signed-off-by: Brandon Yates <brandon.yates@intel.com>
2024-02-28 01:36:20 +01:00
8483a922a7 feature: simplify in-order allocation overflow
Related-To: NEO-10507

Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2024-02-27 18:25:26 +01:00
219470f60d build: remove static_assert for drm header change
Removed static_assert for reset_stats before updating
drm header to v2.0-r23.

Related-To: GSD-5673
Signed-off-by: Young Jin Yoon <young.jin.yoon@intel.com>
2024-02-27 17:42:01 +01:00
b6b53daa3f fix: don't program dummy blit prior to MI ARB CHECK
Related-To: NEO-9996
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2024-02-27 15:46:46 +01:00
9f01a831a2 fix: correct command for dummy blit on PVC
use MEM_SET command

Related-To: NEO-9996

Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2024-02-27 14:27:47 +01:00
0bf8e8727e refactor: add output buffer argument to store register to memory encoder
Related-To: NEO-10064

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2024-02-27 13:31:55 +01:00
9cbc33e23d fix: setup correct render/display core family for gmmlib initialization
pass values got from adapter info

Related-To: NEO-10482
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2024-02-26 14:49:04 +01:00
cfd3edfb2c fix: Align IOH entry
Related-To: NEO-10036

Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2024-02-26 14:36:31 +01:00
459da6a482 refactor: cleanup xe hpg logic related to dummy blit wa
Related-To: NEO-9996
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2024-02-26 13:32:18 +01:00
3e65e7bdba fix: correct number of max work group count for concurrent kernel on PVC
for single-CCS mode use all EUs

Related-To: NEO-8377
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2024-02-26 10:42:50 +01:00
7729eb8127 refactor: move flush task submission to a function
Related-To: NEO-7824
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
2024-02-23 18:11:57 +01:00
6cdd2d5dca fix: add missing gt_id when creating XE context
Related-To: GSD-8046

Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2024-02-23 16:50:32 +01:00
1995e6aa40 feature: store cpu pointer of command buffer pointing to post sync command
Related-To: NEO-10064

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2024-02-23 13:12:15 +01:00
55f2b31f2a refactor: adjust device page fault state print
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2024-02-23 12:50:40 +01:00
ef2d3b538b performance: move timestampPacketTagBuffer to local memory
Signed-off-by: Michal Mrozek <michal.mrozek@intel.com>
Resolves: NEO-7765
2024-02-23 09:55:48 +01:00
10d610d163 refactor: move process barrier with post sync to a function
Related-To: NEO-7824
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
2024-02-23 09:32:48 +01:00
01a721df3e refactor: move preparing flush task batch buffer to a function
Related-To: NEO-7824
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
2024-02-23 09:18:58 +01:00
0fa730e524 build: Update debugger uapi headers to latest
Signed-off-by: Brandon Yates <brandon.yates@intel.com>
2024-02-22 16:07:06 +01:00
a4ed483238 refactor: move update task count and completion stamp to function
Related-To: NEO-7824
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
2024-02-22 14:56:25 +01:00
7b689aa464 refactor: move handle batched dispatch implicit flush code to function
Related-To: NEO-7824
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
2024-02-22 14:56:10 +01:00
d795a66f81 fix: Add new DG1 and RPL-S device IDs
Added DG1 device ID: 0x4909
Added RPL-S device ID: 0x468B

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2024-02-21 13:58:05 +01:00
b44729771c fix: Extend MTL's overridePatIndex to XE LPG
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2024-02-21 13:21:30 +01:00
964f0166d7 fix: Reuse freed chunk from left even if not aligned
Related-To: NEO-10416, NEO-10418, NEO-10437

Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2024-02-21 12:31:54 +01:00