Commit Graph

9 Commits

Author SHA1 Message Date
25b3a3dbfa fix: user proper settings for caches.
Signed-off-by: Michal Mrozek <michal.mrozek@intel.com>
2024-02-15 11:38:34 +01:00
b224ec947e Cleanup includes 50
Cleaned up files:
shared/source/helpers/hw_info.h

Related-To: NEO-5548
Signed-off-by: Warchulski, Jaroslaw <jaroslaw.warchulski@intel.com>
2023-02-10 20:26:13 +01:00
8cc0177f1c Change DG2 l1 cache policy to WB
With compiler LSC WAs this gives better performance.

If debugger is active, policy will not be changed ie.
will be WBP.

Related-To: NEO-7003

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-08-31 14:31:23 +02:00
2621460e80 Revert "Change DG2 l1 cache policy to WB"
This reverts commit a820e73dd7.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2022-08-27 08:04:19 +02:00
a820e73dd7 Change DG2 l1 cache policy to WB
With compiler LSC WAs this gives better performance.

If debugger is active, policy will not be changed ie.
will be WBP.

Related-To: NEO-7003

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-08-26 12:58:45 +02:00
aa3a4765b9 Respect ForceAllResourcesUncached flag
Respect debug flag ForceAllResourcesUncached even when
Override L1 Policy flags are also set

Related-To: NEO-7003

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-08-18 11:46:33 +02:00
b3078cfbae Revert "Change DG2 l1 cache policy to WB"
This reverts commit 9a5e619c42.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2022-07-28 07:27:13 +02:00
9a5e619c42 Change DG2 l1 cache policy to WB
With compiler LSC WAs this gives better performance.

Related-To: NEO-7003

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-07-27 10:20:36 +02:00
76e023b941 Link build option with L1 cache policy helper
Related-To: NEO-7003

Add L1CachePolicyHelper struct.
This struct is resposible for L1 cache policy
in build option, Surface State and stateless
caching. Currently default option for all
platforms is WBP (write by-pass)


Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2022-07-04 11:49:55 +02:00