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2275f8df0e36394f1c67a166481d1632c8bee365
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2141 Commits

Author SHA1 Message Date
Dunajski, Bartosz
2275f8df0e Rename CommandMarker to CommandWithoutKernel 
Change-Id: Ie19c510465a36ea517a79db9eeac5b5993e44c81
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-09-02 12:53:58 +02:00
Krzysztof Gibala
6a221bc7fc Refactor flags validation 
-create masks for buffer and image flags
-create common file for mem_obj_helper
-refactor parseMemoryProperties
-remove:
 checkUsedFlagsForBuffer, checkUsedFlagsForImage,
 addCommonMemoryProperties, addBufferMemoryProperties,
 addExtraMemoryProperties, addImageMemoryProperties

Related-To: NEO-3132
Change-Id: I3c147799de7b104d10d25b2f5262aeda58241d84
Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
 2019-09-02 12:42:02 +02:00
Dunajski, Bartosz
93aeb1f29a Dont call mapAuxGpuVA() when PTManager is not supported 
Change-Id: I8ead56c289a83a720f150d89cdbfd4d44dfea1ee
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-09-02 10:39:53 +02:00
Maciej Dziuban
7e6ef7c208 Add helpers for MI_ATOMIC address 
Setter in HardwareCommandsHelper
Getter in UnitTestHelper

Change-Id: I26610d0ccf0113b2b3d3c8ba2d1edd5bf8b41175
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
 2019-09-02 08:52:59 +02:00
Maciej Plewka
7827501b91 Add returned status to MemoryOperationsHandler 
Change-Id: Ic8685e3711cec03d8f83d371fa7152ee095a47a0
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2019-09-02 08:42:50 +02:00
Dunajski, Bartosz
77e22bd81b Refactor dispatching blit enqueue 
Change-Id: Ibe499e4815a16d5884510c6804221d2b74dbffd4
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
Related-To: NEO-3020
 2019-09-02 07:56:50 +02:00
Mrozek, Michal
094068807e Change default value of flushL3cache to true. 
Change-Id: Ibaf682fcbe54ebb97a01575b1891ccfe3f60fc4a
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
 2019-08-30 14:42:21 +02:00
Mrozek, Michal
0666da693e Improve uncached flag. 
- When resource is uncached for surface state and not used in stateless manner
then it doesn't need to flush cache
- Minor cleanup

Change-Id: I4cfe5a6fe3e666200407d9acdd89e6f64b2b3eed
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
 2019-08-30 12:17:27 +02:00
Mrozek, Michal
ae201a47d3 Improve uncached resources handling. 
- Change kernel to properly detect true stateless resources
- do not turn of stateless l3 if arg is used in pure stateful manner
- refactor variable names to better reflect what they do
- improve mock kernel with internal to have setKernelArg capabilties

Change-Id: I2cdde04f2144d9b86dc1486126632db0fd7cad49
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
 2019-08-30 10:51:28 +02:00
Mrozek, Michal
33f6c7f0da Add new flag to disable L3 for stateful accesses. 
- With this flag resource will not be cached in L3 for stateful accesses.

Change-Id: Icf9a393ab92d55c2cdf30444420ea40da0d5630c
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
 2019-08-29 23:38:26 -07:00
Sebastian Sanchez
08a3046e4d Add isL3Configurable() method to HwHelper 
Add isL3Configurable() method to HwHelper to query if L3 is
configurable using an HwHelper instance.

Change-Id: I0f350ae292f12980611a250301293378dbd8dd91
Signed-off-by: Sebastian Sanchez <sebastian.sanchez@intel.com>
 2019-08-30 07:19:40 +02:00
Mrozek, Michal
81b055024e Change the offset calculation to use CCS. 
Change-Id: I07a878dd6861883e47062b89b5af57fcb7f5aa9b
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
 2019-08-29 14:16:07 +02:00
Jobczyk, Lukasz
10795c716f Move DebugSettingsReader to a core dir 
Related-To: NEO-3677

Change-Id: I3374abde6717be20c064ec6d65c0751a783f5138
Signed-off-by: Jobczyk, Lukasz <lukasz.jobczyk@intel.com>
 2019-08-29 13:49:40 +02:00
Mrozek, Michal
1ec794286f Remove not used global variable. 
Change-Id: I3cc5cd6099331b186f6f3ee6324b058f2125aecb
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
 2019-08-29 13:12:17 +02:00
Jobczyk, Lukasz
0528c6803c Enhance enqueue SVM tests 
Change-Id: Ie3b99ee596a0795814c566deb9e3c37ea57c92c5
Signed-off-by: Jobczyk, Lukasz <lukasz.jobczyk@intel.com>
 2019-08-29 10:54:46 +02:00
Mrozek, Michal
817e62e01c Limit redundancy in main.cpp 
- Some functions were called twice, this commit limits this.

Change-Id: Ib362cc038a2f0669dbfbb62f0c00b67cf980d316
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
 2019-08-29 09:55:48 +02:00
Dunajski, Bartosz
386fa40241 Rename HWTEST_F_T to HWTEST_TEMPLATED_F 
Change-Id: I2db1eca61f180a3986e58a36fde7d8a523109303
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-08-29 08:32:51 +02:00
Andrzej Swierczynski
91af33d825 Update images to work in media compression scenarios 
Related-To: NEO-3613
Change-Id: I338f465435207400156d42a45e5d5b5915489715
Signed-off-by: Andrzej Swierczynski <andrzej.swierczynski@intel.com>
 2019-08-28 14:15:52 +02:00
Mrozek, Michal
a54dcd98b3 Register cache flushes when ISA allocation is destroyed. 
- when ISA is being destroyed , check what are the users of it and register
instruction cache flushes there.
- For subsequent enqueue commands this would result in properly flushed
instruction cache.

Change-Id: I3791cd77ee42da9f87508c64a65cdc6238950858
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
 2019-08-28 14:15:19 +02:00
Dongwon Kim
25d9e4533d DRM Graphic allocation assigns original hostPtr as cpuPtr 
Change-Id: I9ba282b130b5fb9b674e1ceb2f87183f218ab140
Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
 2019-08-28 13:35:18 +02:00
Dunajski, Bartosz
04c45967b9 Change BcsBufferTests to HWTEST_F_T and start using HwHelperHw in Setup 
Change-Id: Iaccad06e854c5321d1f5907ae136d50ce64057e4
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-08-28 13:17:04 +02:00
Igor Venevtsev
3371ed12f6 Refactor DrmMemoryManager::freeGraphicsMemoryImpl 
- remove default value from synchronousDestroy param in
  DrmMemoryManager::unreference
- unreference BufferObject in synchronous mode  before release
  GPU and CPU memory
- add ULTs

Related-To: NEO-2877

Change-Id: I8065c27923cf4259a0fcd0f6d8d6d5b7c4b810c0
Signed-off-by: Igor Venevtsev <igor.venevtsev@intel.com>
 2019-08-28 12:30:20 +02:00
Mateusz Jablonski
18982bd016 Move memory for slm window to memory manager 
remove redundant methods from MockDevice

Related-To: NEO-3007

Change-Id: I9cc819b9c9118dbb667f5bf87d1bf15787f9b67f
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2019-08-28 12:09:17 +02:00
Dunajski, Bartosz
89824aa848 Update TimestampPacketTests to use HwHelperHw for low priority engine 
Change-Id: I4c7bb2c48daa245224ccdc084f152f98197b908c
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-08-28 11:46:11 +02:00
Dunajski, Bartosz
6a5c89c9f7 Remove redundant test 
Change-Id: Ie8aa1aeca169fcbe23edd1712143cfed437c95c5
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-08-28 11:26:08 +02:00
Jobczyk, Lukasz
c7ad27d430 Add a HostToHost copy type in the Memcpy 
Related-To: NEO-3570, NEO-3610

Change-Id: I84f8e2150b2d3760d968e94ae85638d91cb77a54
Signed-off-by: Jobczyk, Lukasz <lukasz.jobczyk@intel.com>
 2019-08-28 10:55:07 +02:00
Dunajski, Bartosz
40d4314670 Templated SetUp and TearDown in fixtures 
Change-Id: I86b0e88db1ed52966ed5f0a6474deda09a415768
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-08-28 10:43:42 +02:00
Mrozek, Michal
e7a4635dd6 Add mechanism to register instruction cache flushes. 
- With this mechanism csr with add pipe control with instruction cache flush
prior to enqueue, to make sure that this cache is flushed.

Change-Id: I664f212427686e9957027c7cf6c0dab17d2a3cac
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
 2019-08-28 07:56:41 +02:00
Krzysztof Gibala
84c801e28b Remove OCL object from MemoryProperties 8/n 
Refactor MemoryPropertiesFlags to bitfield

Related-To: NEO-3132
Change-Id: I7092b16d15cec962e94c992696bd9845ce86f642
Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
 2019-08-27 17:28:47 +02:00
Mrozek, Michal
be17471f8a Wire in L1 MOCS index for stateless accesses to csr. 
Change-Id: I1712a696e9c02ef042a08c80bfa87e80e82ada5f
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
 2019-08-27 15:48:12 +02:00
Mateusz Jablonski
c7c6068d1f Add classes for sub devices concept 
Related-To: NEO-3007

Change-Id: I27dd4b91e286ba1b75f4b50bec96d98df37983e1
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2019-08-27 15:38:10 +02:00
Jobczyk, Lukasz
4503e04083 Align a unified memory pointer during memcpy 
Related-To: NEO-3570, NEO-3610

Change-Id: Id4d41da17a28ef512ba4c90bd71f419a24608d88
Signed-off-by: Jobczyk, Lukasz <lukasz.jobczyk@intel.com>
 2019-08-27 15:37:41 +02:00
Mrozek, Michal
bd8405aa3d Fix revision id setting. 
Change-Id: I510ae6a497a9233e4fdd1dcd2a22f2dbd47b247b
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
 2019-08-27 14:29:11 +02:00
Dunajski, Bartosz
b218c7fa16 Add helper for low priority engine type 
Change-Id: I1d46e73f94d2827ba44de86a752d03830ff2b7e3
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-08-27 14:13:53 +02:00
Mrozek, Michal
bd6c2b0f1e Revert "Flush instruction cache." 
This reverts commit 3d062620a7.

Change-Id: I615d6d7e4298588cffd8f543e1c56045278c8c98
 2019-08-27 13:40:03 +02:00
Mateusz Jablonski
7749f28f70 Remove not needed methods from Device. 
Change-Id: I179089a4b248ba1ebd6502e001fda18238c4767b
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2019-08-27 09:07:10 +02:00
Maciej Plewka
7a5bc461eb Add residency handler for TBX 
Change-Id: I6c01d065ff3372fe7583ed50ed51595ebeb53e54
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2019-08-27 07:59:47 +02:00
Mrozek, Michal
cb4e5576cb Pass proper dispatch flags. 
- add new policy to select L1 caching
- this is when kernel doesn't have any stateless writes

Change-Id: I3948e652797420976159bbfec2c2a154eb9e18ee
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
 2019-08-26 18:15:54 +02:00
Mrozek, Michal
ea095418ad Stop using cache policy defines. 
- Replaced by Hardware Helper code.

Change-Id: I55026ee33fcaaffbfb529e1878ae4f7033f62ee5
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
 2019-08-26 17:36:50 +02:00
Daria Hinz
6566eb3193 Move Linear Stream to core folder 
Change-Id: I962ebd6e9075fcab9d7b6211524093109e62d382
Signed-off-by: Daria Hinz <daria.hinz@intel.com>
 2019-08-26 17:00:53 +02:00
Mrozek, Michal
e851359e32 Start using real mocs index to call state base address programming. 
- After this change we start using real MOCS index as an argument to sba
programming
- We also start tracking real MOCS index in Command Stream Receiver.

Change-Id: Id34cffd7e58cb7363df02ac76f82bf377f4bbd77
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
 2019-08-26 16:14:36 +02:00
Dunajski, Bartosz
aeb84b3e20 y-tiling interface cleanup 
Change-Id: If7e5ab7135eaa71d9215c87c2fc46188ffd42b02
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-08-26 15:00:26 +02:00
Dunajski, Bartosz
8135babfc4 Dont use default engine tag address in DeviceQueue 
Change-Id: I84b9ecd9a9e7c1ffe620af8ad54fd5d48532fa5b
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-08-26 13:30:18 +02:00
Mrozek, Michal
3d062620a7 Flush instruction cache. 
Change-Id: I2ae0c40ae99cd8e0c126c8588e6df293e29d3db3
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
 2019-08-26 11:25:51 +02:00
Mrozek, Michal
918711c865 Add helper function to return proper mocs index basing on inputs. 
Change-Id: I062891d02607fec932e0cb9ae84fe858e9d9e098
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
 2019-08-26 09:17:09 +02:00
Maciej Dziuban
f86bbd99d2 Include hw_cmds for specific gen when possible 
Change-Id: I3fc55321f92d02419c4c04e6d1bc28b09b306c0f
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
 2019-08-24 11:09:26 +02:00
Igor Venevtsev
ffe2bd359a Add ULTs for OsAgnosticMemoryManager 
Related-To: NEO-2877

Change-Id: Id80fd66ced9d711ff74d85fa48741c95f9f750bb
Signed-off-by: Igor Venevtsev <igor.venevtsev@intel.com>
 2019-08-23 15:26:27 +02:00
Mrozek, Michal
c24bbac25f Refactor scratch offset programming. 
- no need for virtual functions and helpers, this is just a constant that
is the same everywhere.

Change-Id: Id0ebfd2eed26e26f90f104ec456dcc997be70211
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
 2019-08-23 13:42:58 +02:00
Chodor, Jaroslaw
84d1461ccc Fixing execution model tests 
Tests were reliyng on order of kernels within device binary

Change-Id: Ic66430ce76d44556f579e9d1217b25caf448aa72
 2019-08-23 12:31:15 +02:00
Dunajski, Bartosz
4692bc1289 Update GMM H/V alignment API 
Change-Id: I2713b912cd93ae28de6c7ef6a8348107f0902368
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-08-23 12:15:33 +02:00