Commit Graph

21 Commits

Author SHA1 Message Date
Mrozek, Michal 78f828fcd1 Make residency in graphics allocation OsContext dependent.
- Graphics Allocation now holds residency control per OsContext.

Change-Id: Ie0a0d3aa9fdaf542fdd42dee3aba236a5af635c7
2018-09-20 16:44:04 +02:00
Hoppe, Mateusz 4af432ae10 Store page entry bits in PageTable entries
- set Present bit when entry is allocated regardless entry bits passed.

Change-Id: Ib1393927f66c4ed0b577a4df58d2760fbff86df7
2018-09-20 09:25:34 +02:00
Hoppe, Mateusz 619d2217cb Pass AubHelper to reserveAddressPPGTT().
- get PageTable entry data hints and address space from AubHelper
based on local memory flag
- add enableLocalMemory flag in CSR HW

Change-Id: I061bda62be8da55d52cff48ecddcf26c4212dc67
2018-09-17 18:48:06 +02:00
Maciej Dziuban ac1d2b9901 Change processResidency argument to a reference
Change-Id: Ie313a8cc4e479a314bcf170917397c13fbb70d14
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
2018-09-14 13:36:20 +02:00
Hoppe, Mateusz 610eda5ad1 Add PhysicalAddressAllocator to PageTables
- Allocator is responsible for physical pages allocation

Change-Id: I3a9034c87292484da8f4f0eb1d1e0cc5122a4d8a
2018-09-14 13:23:07 +02:00
Maciej Dziuban 4da2dd471d Get rid of processResidency() calls with null ResidencyContainer 2/n
Change-Id: Ic2495cd21304710825727177a1d90889e22808d8
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
2018-09-11 15:01:01 +02:00
Milczarek, Slawomir 991bbddeba Add function to get Page Table entry bits
This commit adds a helper function to get Page Table entry bits
and control a configuration of first levels page walks (non-PTE).

Change-Id: I85666ffae8e89a193d1ac4a065c2b84b814d47ec
2018-09-11 14:10:42 +02:00
Hoppe, Mateusz 2315403542 Refactor AUB & TBX CSRs
- add method for getting addressSpace

Change-Id: I12d466e358db1d21c038bd9e0201cae433a5ec1a
2018-09-10 09:42:35 +02:00
Stefanowski, Adam 8a005434f4 [1/n] Initialize WDDM only once
- remove Wddm parameter from WddmCommandStreamReceiver
and pass it via ExecutionEnvironment
- remove drm parameter from DrmCommandStreamReceiver
and pass it via ExecutionEnvironment
- remove void parametr from TbxCommandStreamReceiverHw

Change-Id: Ib76332f1341339426e86e0ce2b6ce96919219881
2018-09-06 14:14:29 +02:00
Mateusz Jablonski 92bfd2e3d2 Move OsContext to Device
Change-Id: I030b65372fbdc075423d22720e9da34ac65b8e68
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2018-09-03 10:42:26 +02:00
Mrozek, Michal 1599ea800e Pass execution environment to command stream receiver.
Change-Id: I598f67f8b005b5ce8249b638e080657eb6dc3547
2018-08-08 17:10:39 +02:00
Mrozek, Michal 6f251f5ea1 Fix TBX completion loop.
- resources are dumped in make non resident call
- in order to dump correct data we need to be sure that GPU is done processing
- waiting needs to be unconditional to handle all cases
- remove not needed parameter to makeSurfacePackNonResident

Change-Id: Ib2b065d486cd3a5d86e599c51b24f3c958c3a10b
2018-08-03 09:32:24 +02:00
Hoppe, Mateusz 64277ee849 TBX CommandStreamReceiver fix for makeCoherent
- makeCoherent should be called after TBX finished processing
 - this is when tagAddress is updated with taskCount
makeCoherent is called from makeNonResident which is invoked just
after flush and may happen before TBX server finished processing
leading to invalid data to be read back to CPU accessible memory

- this fix adds waiting for taskCount to blocking calls for TBX CSR
before calling makeNonResident on surfaces to guarantee correct data
from TBX server is ready.

Change-Id: I498a5454e0826eec2a5413a08880af40268550e1
2018-07-04 12:04:32 +02:00
Milczarek, Slawomir fb10f666e9 AUB CSR: Ensured PTE bits be set correctly for Global GTT
This commit fixes the issue with setting reserved bits in PTE for GGTT.

Change-Id: I08582e20914419a3363c9e61085dcf03ba355a61
2018-06-21 22:23:01 +02:00
Zdanowicz, Zbigniew 36621b2488 Use product aub device id and make it configurable by using debug flag
Change-Id: Ie65eea0f72497ef68e805ad438f4f53df731d304
2018-06-06 17:09:21 +02:00
Zdanowicz, Zbigniew f94844305f Add new arguments to aub dumping interface
Change-Id: I226ec04a919f4ca6ae5c237cf189e043f8286d5e
2018-05-10 13:33:54 +02:00
Hoppe, Mateusz 4703417813 Use correct virtual addresses in TBX CSR makeCoherent method
- cpu virtual address was used instead of gpu va
- this caused incorrect behaviour of TBX server when
special heap allocator assigning GPU addresses was used

Change-Id: I2328cf2441be797311fd6a3c7b331b0fff79d4fc
2018-04-03 15:54:07 +02:00
Milczarek, Slawomir fcb9a591b0 Add AUB generation in parallel to execution on TBX
This commit adds support for AUB capturing with simultaneous execution on TBX

Change-Id: I046bac6b953708007c525050fbf9357120a310b6
2018-03-08 16:52:52 +01:00
Milczarek, Slawomir 3e84c4df7a Introduced a new graphics allocation type of ALLOCATION_TYPE_NON_AUB_WRITABLE.
This commit moves the allocation's aubfile write permission property
from OS agnostic MemoryAllocation to general GraphicsAllocation class.

Change-Id: I82ca2716d6b65d314460bd9f5d33e1113f9d7c07
2018-01-18 18:36:14 +01:00
Zdanowicz, Zbigniew 602474f868 Command streamers should use device default engine type
Change-Id: I7286f15ba78001729ea489a43576d96f109d44f0
2018-01-16 22:37:44 +01:00
Brandon Fliflet 7e9ad41290 Initial commit
Change-Id: I4bf1707bd3dfeadf2c17b0a7daff372b1925ebbd
2017-12-21 00:45:38 +01:00