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28 Commits

Author SHA1 Message Date
Mateusz Hoppe 01b324953e L0Debug - allocate per-tile ISA when tileAttach is enabled 
Related-To: NEO-5784

Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
 2022-08-18 15:48:31 +02:00
Milczarek, Slawomir 6a9fcd38b1 Create KMD-migrated unified shared memory with multiple local memory regions 
Remove the restriction on USM allocation created in a single local memory region
with latest KMD fix for cross tile migration thrashing b/t lmem (dii-3516)

Related-To: NEO-6909

Signed-off-by: Milczarek, Slawomir <slawomir.milczarek@intel.com>
 2022-07-04 13:33:23 +02:00
Milczarek, Slawomir 9d31d36491 Disable cross-tile kmd migration for usm allocations 
Ensure KMD migrations for USM allocations to occur between smem and lmem only

Related-To: NEO-6969

Signed-off-by: Milczarek, Slawomir <slawomir.milczarek@intel.com>
 2022-05-16 15:23:34 +02:00
Mateusz Hoppe c9d61840a2 Allocate SBA buffers per HW context 
- different physical storage for every HW context
- adds support for debugging with implicit scaling on
- reorganize tests

Relates-To: NEO-6883

Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
 2022-04-15 10:01:28 +02:00
Mateusz Jablonski 8a8b4866cb XeHPC: force local memory for command/ring/semaphore buffer 
require 48bit resource for ring/semaphore buffer
for multi tile allocations select first tile
for single tile allocation select preferred tile

Related-To: NEO-6698
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2022-03-24 10:54:26 +01:00
Mateusz Jablonski 3792481d33 XeHPC Implicit scaling: put command/ring/semaphore buffer to first memory bank 
In direct submission scenario command/ring/semaphore buffer allocations
are placed in the same memory bank to ensure that their memory is updated in
correct order

Related-To: NEO-6698
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2022-03-21 08:10:50 +01:00
Aravind Gopalakrishnan e4a93f9870 Set page table cloning on for event device allocs 
Related-To: NEO-5968

Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@intel.com>
 2022-02-24 22:35:03 +01:00
Bartosz Dunajski 61ca84e94b Pass memory placement info to StorageInfo 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2022-02-09 16:55:32 +01:00
Bartosz Dunajski 4b0d986876 Move AllocationType enum out of GraphicsAllocation class 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2022-02-04 17:49:09 +01:00
Kamil Diedrich 1b7949432f Add shareable allocation on windows dGPUs 
Add default initialization for object members

Related-To: LOCI-2665

Signed-off-by: Kamil Diedrich <kamil.diedrich@intel.com>
 2022-01-19 19:03:18 +01:00
Bartosz Dunajski dfdd3c597a Remove redundant BUFFER_COMPRESSED allocation type 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2021-12-07 13:35:49 +01:00
Lukasz Jobczyk 71ed3eba16 Add mapping based colouring 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2021-10-25 09:51:54 +02:00
Lukasz Jobczyk 7392b5fb8d Add new colouring policy 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2021-10-07 23:33:26 +02:00
Mateusz Hoppe 8d3438a5fb Allocate single Isa instance when debugging enabled 
- Related-To: NEO-6221

Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
 2021-09-08 11:49:50 +02:00
Michal Mrozek bf1180753d Improve private memory allocation. 
-allocate from single bank when only one sub device passed

Signed-off-by: Michal Mrozek <michal.mrozek@intel.com>
 2021-08-26 07:46:23 +02:00
Compute-Runtime-Validation f1264c19dc Revert "Improve private allocation storage." 
This reverts commit be3ca800bb.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2021-08-20 02:54:09 +02:00
Michal Mrozek be3ca800bb Improve private allocation storage. 
- Do not allocate on multi tile if device limits scope.

Signed-off-by: Michal Mrozek <michal.mrozek@intel.com>
 2021-08-18 15:02:14 +02:00
Lukasz Jobczyk 49cf6f79f5 Validate host ptr on VM it will be used 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2021-08-16 08:15:53 +02:00
Bartosz Dunajski ab73b61b77 Fix multitile ISA placement 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2021-08-02 15:16:13 +02:00
Lukasz Jobczyk 890eec6105 Separate local memory usage tracking for internal and external 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2021-07-22 07:52:43 +02:00
Bartosz Dunajski e939e97384 Dont replicate GPU_TIMESTAMP_DEVICE_BUFFER 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2021-07-16 15:23:50 +02:00
Bartosz Dunajski c7a936d1f4 Add memory banks to Simulated CSR 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2021-07-05 12:19:58 +02:00
Bartosz Dunajski 96d14967ac Partial support for XE_HP_SDV 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2021-06-24 18:35:54 +02:00
Mateusz Jablonski ed31aaedb8 Make BUFFER allocation lockable on DG1 
Related-To: NEO-5733
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2021-05-21 17:05:51 +02:00
lgotszal 3bd4bca911 Copyright header update 
Dates corrected in copyright headers to reflect original publication date
(2018 for OpenCL, 2020 for Level Zero).

Signed-off-by: lgotszal <lukasz.gotszald@intel.com>
 2021-05-17 20:38:19 +02:00
Igor Venevtsev 3859e13322 Split large allocations on Windows due to Wddm limitation 
Resolves: NEO-4479

Change-Id: Iffb862a93570a60c2126620d9e5106359acba64a
Signed-off-by: Igor Venevtsev <igor.venevtsev@intel.com>
 2020-06-17 12:47:54 +02:00
Mateusz Jablonski 7df9945ebe Add absolute include paths 
Change-Id: I67a6919bbbff1d30c7d6cdb257b41c87bad51e7f
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2020-02-23 23:49:12 +01:00
kamdiedrich e072275ae6 Reorganization directory structure [3/n] 
Change-Id: If3dfa3f6007f8810a6a1ae1a4f0c7da38544648d
 2020-02-23 23:48:28 +01:00