Commit Graph

213 Commits

Author SHA1 Message Date
Dominik Dabek 6e8cabdce5 Split wait for timestamps to queue and event
On PVC both enabled.
On DG2 only for events.

Related-To: NEO-6948

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-05-06 15:34:47 +02:00
Bartosz Dunajski f8ce86b116 XE_HPC: Fallback path to fix PAT_INDEX programming
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2022-05-05 15:06:21 +02:00
Dominik Dabek 8d1ad5a4f3 Refactor: use stack vector for root device indices
Stack vector will not cause dynamic allocations in most circumstances
ie. number of root device indices not more than 16

Related-To: NEO-6837

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-04-14 14:05:42 +02:00
Krystian Chmielewski ee0d183cf9 Handle legacy hasBarriers properly
Previous change regarding NEO-6785 added encoding of number of barriers
to specific value representation depending on hardware that we program for.

In patch token format encoding of number of barriers is sent via
hasBarriers field in a token.
In zebin true number of barriers is sent via barrier_count field in
zeInfo.

To remove this discrepancy, translate encoded number of barriers into
true number of barriers in legacy format.

Resolves: NEO-6785

Signed-off-by: Krystian Chmielewski <krystian.chmielewski@intel.com>
2022-04-12 09:44:10 +02:00
Bartosz Dunajski 884d729e4e Improve pat index programming on linux
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2022-04-12 08:18:20 +02:00
Krystian Chmielewski 2c1bfbb5b2 Encode number barriers
When programming number of barriers use BARRIER_SIZE enumeration.
Resolves: NEO-6785

Signed-off-by: Krystian Chmielewski <krystian.chmielewski@intel.com>
2022-04-08 10:32:23 +02:00
Bartosz Dunajski 08e3853982 Debug flag to add extra MI_MEM_FENCE for DirectSubmission
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2022-03-30 16:07:25 +02:00
Compute-Runtime-Validation 91cfd3cd1a Revert "Unify command/ring/semaphore buffers placement"
This reverts commit e035199de4.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2022-03-30 14:05:47 +02:00
Mateusz Jablonski e035199de4 Unify command/ring/semaphore buffers placement
put them all to the same memory location

Related-To: NEO-6698
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-03-29 17:55:48 +02:00
Zbigniew Zdanowicz 9858438121 Limit multiple partition count to compute command lists
Related-To: NEO-6811

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-03-29 07:29:08 +02:00
Konstanty Misiak 174c27eb31 Fix CFEFusedEUDispatch debug flag
Signed-off-by: Konstanty Misiak <konstanty.misiak@intel.com>
2022-03-28 12:32:05 +02:00
Jobczyk, Lukasz d77a6cbe4b Enable task count update from wait
Signed-off-by: Jobczyk, Lukasz <lukasz.jobczyk@intel.com>
2022-03-28 11:09:55 +02:00
Filip Hazubski 586e8510de Remove unneeded include
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2022-03-26 09:55:25 +01:00
Compute-Runtime-Validation 0c064ccf4c Revert "Enable task count update from wait"
This reverts commit 5118a5d3a6.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2022-03-25 00:09:52 +01:00
Lukasz Jobczyk 5118a5d3a6 Enable task count update from wait
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2022-03-23 11:38:50 +01:00
Jitendra Sharma f52f3df274 Add platform specific getter of debug surface size
For different platforms based on number of available threads
and debug surface layout, calculate max debug surface size.

Related-To: NEO-6676
Signed-off-by: Jitendra Sharma <jitendra.sharma@intel.com>
2022-03-22 12:18:40 +01:00
Filip Hazubski 80b520bc9b Change ThreadArbitrationPolicy enum type to int32_t
Change ThreadArbitrationPolicy::NotPresent value to -1
Update initial values to ThreadArbitrationPolicy::NotPresent

Related-To: NEO-6728

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2022-03-07 20:04:24 +01:00
Aravind Gopalakrishnan 16f2fbbc37 [9/n] L0 immediate commandlist improvements
Add HwInfo utility for more fine-grained flush task enablement
Related-To: LOCI-1988

Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@intel.com>
2022-02-18 19:51:28 +01:00
Aravind Gopalakrishnan 74cdd60255 [7/n] L0 immediate commandlist improvements
Enable flushTask only for specific families for now

Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@intel.com>
2022-02-15 18:43:30 +01:00
Maciej Plewka 9d8ce7aace Command container appends BB_END on cmd buffer allocation end
When linear stream created for command container has not enough space
for command and BB_END it will program BB_END and allocate new command
buffer allocation. Pointer returned from getSpace in this case will
return storage from new command buffer allocation.

Related-To: NEO-5707

Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2022-01-31 16:15:37 +01:00
Zbigniew Zdanowicz a7455b5767 Add tweaks and control flags to linux completion fence
Related-To: NEO-6575

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-01-21 13:41:23 +01:00
Michal Mrozek 27c43b27f3 Remove not needed method.
Signed-off-by: Michal Mrozek <michal.mrozek@intel.com>
2022-01-20 15:02:19 +01:00
Zbigniew Zdanowicz 4238679078 Refactor implicit scaling device support
Related-To: NEO-6589

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-01-18 13:08:43 +01:00
Igor Venevtsev d9aae805c7 Do not apply L0 debugger WA (Disable L3 cache) for highest DG2 steppings
Related-To: NEO-6320

Signed-off-by: Igor Venevtsev <igor.venevtsev@intel.com>
2022-01-17 13:46:40 +01:00
Filip Hazubski 5be4d89b73 Rename function
Rename MemorySynchronizationCommands::isDcFlushAllowed
to MemorySynchronizationCommands::getDcFlushEnable

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-12-30 17:03:22 +01:00
Maciej Plewka 615688336f Program all fields in SCM
Related-To: NEO-6432

This change applies WA that always programs all fields in SCM for
gen12lp. Also for those platforms Force Non-Coherent is set to 0x2.

Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2021-12-28 16:30:47 +01:00
Mateusz Jablonski 896e01c1cb Require exact revision when getting binary builtin for PVC
this change also implements logic for recompilation of builtin from spv in L0
in case when binary resource is not available


Related-To: NEO-6170
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2021-12-22 19:56:54 +01:00
Filip Hazubski 0fd685541d Add isDcFlushAllowed function to HwInfoConfig
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-12-21 18:29:43 +01:00
Filip Hazubski 6d439f88bb Explicitly set dcFlushEnable value
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-12-21 12:21:11 +01:00
Lukasz Jobczyk bc58172075 Revert "Enable task count update from wait"
This reverts commit 8db36ddf28d0b85516e0adf77dbfc78000d22146.

Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2021-12-20 16:53:16 +01:00
Lukasz Jobczyk 6e5bc0d5ee Enable task count update from wait
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2021-12-17 15:21:51 +01:00
Lukasz Jobczyk 1f0c58d0bf Refactor timestamp wait mechanism
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2021-12-16 13:22:19 +01:00
Igor Venevtsev fe250d99b1 Disable L3 caches for debug on ATS and DG2
Resolves: NEO-6320

Signed-off-by: Igor Venevtsev <igor.venevtsev@intel.com>
2021-12-14 13:59:09 +01:00
Bartosz Dunajski d07c76c237 unTypedDataPortCacheFlush pipe_control helper support
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2021-12-09 13:00:10 +01:00
Bartosz Dunajski 7c610ed5bb Add new Engine Group types
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2021-12-07 15:28:15 +01:00
Bartosz Dunajski 2b1aa8b331 Compilation fix: Add missing LrcaHelper types
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2021-12-07 13:19:36 +01:00
Bartosz Dunajski 68aea5bf62 Rename compression flags and helpers
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2021-12-03 18:09:02 +01:00
Zbigniew Zdanowicz 3e1023fa1a Unify memory layout for all multi tile post sync operations
Related-To: NEO-6262

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-12-02 18:00:40 +01:00
Lukasz Jobczyk fb376639ee Refactor isDirectSubmissionSupported
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2021-11-25 13:40:41 +01:00
Lukasz Jobczyk e8cc34d7b0 Add infrastructure to assign engine to command queue with round robin
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2021-11-15 13:13:40 +01:00
Zbigniew Zdanowicz 78609cd9f5 Optimize number of calls for pipe control post syncs
Related-To: NEO-6262

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-11-10 18:36:21 +01:00
Zbigniew Zdanowicz 36fd163837 Refactor pipe control post sync operations
Related-To: NEO-6262

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-11-10 08:53:03 +01:00
Compute-Runtime-Validation 908a7721b2 Revert "Assign engine to command queue using round robin algorithm"
This reverts commit 2fff0f9059.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2021-11-10 07:25:44 +01:00
Lukasz Jobczyk 2fff0f9059 Assign engine to command queue using round robin algorithm
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2021-11-09 11:05:16 +01:00
Compute-Runtime-Validation 9058de77cc Revert "Assign engine to command queue using round robin algorithm"
This reverts commit 1c68ac1cbc.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2021-11-08 16:36:18 +01:00
Mateusz Hoppe ee418efadf Per-thread scratch offset calculation
Related-To: NEO-6404

Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
2021-11-05 11:03:17 +01:00
Zbigniew Zdanowicz 23a7ab7593 Refactor implicit scaling barriers to add more cache flush options
Related-To: NEO-6262

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-11-04 17:56:12 +01:00
Lukasz Jobczyk 1c68ac1cbc Assign engine to command queue using round robin algorithm
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2021-11-03 17:16:54 +01:00
Zbigniew Zdanowicz a7747fece5 Refactor creation of buffer surface state 2/n
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-10-21 16:09:54 +02:00
Katarzyna Cencelewska 1c8a6d895a Use hwInfoConfig to check blitter support for image
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
2021-10-13 17:51:00 +02:00