Commit Graph

104 Commits

Author SHA1 Message Date
Naklicki, Mateusz 914939c377 Fix execution of cooperative kernels on multi-tile device
Add flag for forcing execution of kernels on single tile
Force cooperative kernels to use only single tile

Related-to: NEO-6729
Signed-off-by: Naklicki, Mateusz <mateusz.naklicki@intel.com>
2022-11-28 14:36:21 +01:00
Dunajski, Bartosz 6f4e7b98dc Unify IDD DenormMode programming
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-11-15 20:06:45 +01:00
Dunajski, Bartosz 62db166cee Debug flag to force ComputeWalker->PostSync flushing bits
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-11-15 01:34:50 +01:00
Kamil Kopryk 4aa1697e3c Move hwInfoConfig ownership to RootDeviceEnvironment 2/n
Related-To: NEO-6853
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>

Use RootDeviceEnvironment getHelper<ProductHelper> for
- adjustSamplerState
- adjustPlatformForProductFamily.
2022-11-14 13:04:31 +01:00
Compute-Runtime-Validation 77b6918f30 Revert "LOCI-3365: Cleanup MediaInterfaceDescriptorLoad logic in command enco...
This reverts commit cb3f7234f0.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2022-11-12 16:05:11 +01:00
Tratnack, Geoffrey cb3f7234f0 LOCI-3365: Cleanup MediaInterfaceDescriptorLoad logic in command encoder
Add a patch to command encoder for samplers when DSH is dirty.

Signed-off-by: Tratnack, Geoffrey <geoffrey.tratnack@intel.com>
Related-To: LOCI-3365
2022-11-10 23:28:58 +01:00
Compute-Runtime-Validation ddbaa5e8c9 Revert "Cleanup MediaInterfaceDescriptorLoad logic in command encoder"
This reverts commit 349af0bd5e.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2022-11-07 02:20:27 +01:00
Tratnack, Geoffrey 349af0bd5e Cleanup MediaInterfaceDescriptorLoad logic in command encoder
Add a patch to command encoder for samplers when DSH is dirty.

Signed-off-by: Tratnack, Geoffrey <geoffrey.tratnack@intel.com>
Related-To: LOCI-3365
2022-11-06 03:27:23 +01:00
Dominik Dabek 6cf8b4daca Correct tg dispatch size heuristic
Multiply available thread count by tile count
if implicit scaling is used

Related-To: NEO-6989

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-10-27 17:24:53 +02:00
Zbigniew Zdanowicz 565d820933 Replace virtual method call for DC flush with stored bool value 3/n
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-10-18 15:04:02 +02:00
Compute-Runtime-Validation 945897cf55 Revert "Replace virtual method call for DC flush with stored bool value 3/n"
This reverts commit 9d94089a95.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2022-10-13 04:46:10 +02:00
Zbigniew Zdanowicz 9d94089a95 Replace virtual method call for DC flush with stored bool value 3/n
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-10-12 14:38:47 +02:00
Zbigniew Zdanowicz 87822f94e2 Replace virtual method call for DC flush with stored bool value 2/n
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-10-12 09:43:01 +02:00
Szymon Morek 3f5ac0b4d0 Reuse heaps for immediate cmd lists
Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2022-10-11 13:02:13 +02:00
Zbigniew Zdanowicz 322719e7a2 prepare tests to enable heap sharing feature
Related-To: NEO-7142

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-10-05 11:54:16 +02:00
Dunajski, Bartosz 52b63be026 Remove isCleanLeftoverMemoryRequired() + refactor sampler support path
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-10-04 16:24:03 +02:00
Zbigniew Zdanowicz 3d92186362 Add heap sharing to immediate command lists
This change is intended to be used in immediate command lists that are
using flush task functionality.
With this change all immediate command list using the same csr will consume
shared allocations for dsh and ssh heaps. This will decrease number of SBA
commands dispatched when multiple command lists coexists and dispatch kernels.
With this change new SBA command should be dispatched only when current heap
allocation is exhausted.
Functionality is currently disabled and available under debug key.
Functionality will be enabled by default for all immediate command lists
with flush task functionality enabled.

Related-To: NEO-7142

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-10-03 18:50:10 +02:00
Dunajski, Bartosz 48824acab2 Improve SBA programming
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-09-30 12:07:16 +02:00
Maciej Bielski 56cb1f757b programStateBaseAddress: improve code reuse
Another step towards cleaner callers of
StateBaseAddressHelper<>::programStateBaseAddress.

Export programming state base address into a separate function to
improve code reuse and reduce copy-pasted fragments, which make code
modifications or maintenance more and more difficult over time. Use
specialization for gen-specific variations.

Related-To: NEO-6774
Signed-off-by: Maciej Bielski <maciej.bielski@intel.com>
2022-09-21 11:54:57 +02:00
Zbigniew Zdanowicz 218a98f7f7 Refactor of pipeline select programming
Adding new interface to cooperate with hw context state
Simplify programming removing unnecessary functions
Code optimization that stop using expensive call and instead
stores configuration parameter

Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-09-15 15:38:10 +02:00
Kamil Kopryk 410fd7d909 Correct binding table prefetch
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
Related-To: NEO-6075

Binding table entry count was zeroed even when
ForceBtpPrefetchMode debug flag was enabled
2022-09-13 14:34:30 +02:00
Zbigniew Zdanowicz c3f7e40a8d Rename special pipeline select mode to systolic
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-31 22:16:26 +02:00
Dominik Dabek 8cc0177f1c Change DG2 l1 cache policy to WB
With compiler LSC WAs this gives better performance.

If debugger is active, policy will not be changed ie.
will be WBP.

Related-To: NEO-7003

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-08-31 14:31:23 +02:00
Compute-Runtime-Validation 2621460e80 Revert "Change DG2 l1 cache policy to WB"
This reverts commit a820e73dd7.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2022-08-27 08:04:19 +02:00
Naklicki, Mateusz 54042a191e Implement PauseOnEnqueue for L0
Allow pausing execution before and after enqueuing kernel
using the PauseOnEnqueue and PauseOnGpuMode debug flags.

Related-To: NEO-6570
Signed-off-by: Naklicki, Mateusz <mateusz.naklicki@intel.com>
2022-08-26 14:48:58 +02:00
Dominik Dabek a820e73dd7 Change DG2 l1 cache policy to WB
With compiler LSC WAs this gives better performance.

If debugger is active, policy will not be changed ie.
will be WBP.

Related-To: NEO-7003

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-08-26 12:58:45 +02:00
Krystian Chmielewski 18adbed233 feat(zebin): add thread scheduling mode support
Resolves: NEO-7197

Signed-off-by: Krystian Chmielewski <krystian.chmielewski@intel.com>
2022-08-18 16:10:18 +02:00
Zbigniew Zdanowicz 0011368775 Add parameter to set surface state base address value
This change introduces capability to set surface state base address
when surface state heap or global base address are not available

Related-To: NEO-7187

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-18 15:36:43 +02:00
Zbigniew Zdanowicz acac5ea0d5 Use correct engine group type when programming state base address
Command lists and their helper classes should use engine group type
assigned to the particular command list to check if it is RCS group
and not use default CSR class assigned to the device, since default
and current in command list might be different.

Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-17 20:38:23 +02:00
Zbigniew Zdanowicz 6c38b36251 Unify getting state base address command space from command buffer
Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-17 11:49:02 +02:00
Zbigniew Zdanowicz ceb9d81f87 Add struct argument for input/output in StateBaseAddressHelper
This refactor makes future interface changes easier

Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-17 10:28:49 +02:00
Zbigniew Zdanowicz 1b9d50660a Unify programming of binding table base address command
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-10 14:35:02 +02:00
Rafal Maziejuk ed0c36117e Apply heuristics when setting TG dispatch size on XE_HPC_CORE
The default TG dispatch size can be changed
to a better value based on number of threads in TG or
currently available amount of threads on GPU.
Decision on what TG dispatch size should be are based on
implemented heuristics.

Signed-off-by: Rafal Maziejuk <rafal.maziejuk@intel.com>
Related-To: NEO-6989
2022-08-08 16:43:10 +02:00
Dunajski, Bartosz 98d776867f Add initial support for KernelArgsBuffer allocation
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-08-03 20:28:21 +02:00
Dunajski, Bartosz c200c6e2dd Pass LSH to EncodeDispatchKernel
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-07-26 15:37:28 +02:00
Dunajski, Bartosz a3903c385e Remove HW types from synchronization interface
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-07-25 13:59:26 +02:00
Zbigniew Zdanowicz 82a6f9e7b2 Use compute walker system fence for system memory or events in use
Related-To: NEO-6959

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-07-13 11:55:32 +02:00
Kamil Kopryk 0b26ee3664 Add surface state programming for kernels with images and stateless buffers
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
2022-07-04 12:24:11 +02:00
Bartosz Dunajski 76d905b1f2 Pass LogicalStateHelper to SBA helper
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2022-07-01 14:52:20 +02:00
Zbigniew Zdanowicz 3ed8b4319f Use primary buffer start when immediate command list using flush task
Related-To: NEO-7091

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-06-29 10:52:43 +02:00
Bartosz Dunajski 2c853adac3 Use LogicalStateHelper to program ComputeMode
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2022-06-27 15:25:55 +02:00
Zbigniew Zdanowicz 5bce1eceb1 Remove self cleanup section when using immediate command list
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-06-27 13:29:52 +02:00
Katarzyna Cencelewska 615fd4c37a Add programming of Dispatch Walk Order in COMPUTE_WALKER for xe_hpg
- update xe_hpg generated commands
- add method isAdjustWalkOrderAvailable

Related-To: NEO-7065
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
2022-06-17 10:42:15 +02:00
Zbigniew Zdanowicz f5b1a0e45b Use internal event object in command lists methods
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-06-14 21:23:43 +02:00
Maciej Bielski 8de043b71f Stop redundant SBA programming due to global atomics
For all platforms different than XE_HP_SDV (ATS) stop considering the
`useGlobalAtomics` flag as a decisive factor for trigerring the SBA
(StateBaseAddress) programming on the HW. Only XE_HP_SDV supports such
flag.

For consistency of the implementation, keep the related logic in one
place only, that is a helper in `command_encoder` and then just reuse it
in different places (`command_stream_receiver`).

Related-To: NEO-6953
Signed-off-by: Maciej Bielski <maciej.bielski@intel.com>
2022-06-08 10:39:56 +02:00
Katarzyna Cencelewska e07bf76f8c Move adjustWalkOrder in encodeThreadData
-include case when localIdsGenarationByRuntime

Related-To: NEO-6964
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
2022-06-07 16:57:02 +02:00
Krzysztof Gibala dc1fe7d59a Change MemoryPool to enum class
Use enum class for MemoryPool in GraphicsAllocation
This change will ensure that GA is constructed in the proper way

- Rename namespace for isSystemMemoryPool method
- Add method getMemoryPoolString for logging actual pool which is in used
- Remove wrong pattern in GraphicsAllocation constructor

Related-To: NEO-6523
Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
2022-06-02 12:46:15 +02:00
Zbigniew Zdanowicz afceaa6e19 Use system fence only when using system allocations or system scope event
Related-To: NEO-6959

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-05-31 12:55:30 +02:00
Katarzyna Cencelewska b2021498e2 Create method adjustWalkOrder
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
2022-05-27 16:05:31 +02:00
Filip Hazubski 35d1f2e341 Add debug flag to control programming of thread arbitration policy with SCM
Related-To: NEO-6801

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2022-05-27 11:35:41 +02:00