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623 Commits

Author SHA1 Message Date
Krzysztof Gibala 2fcda0a528 Refactor: Change decanonize method accessing point 
Accessing decanonize method as a member of GmmHelper class object

Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
 2022-05-11 12:57:02 +02:00
Compute-Runtime-Validation 5507633d15 Revert "Enable update task count from wait on DG2" 
This reverts commit 99c424b6ff.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2022-05-10 14:26:24 +02:00
Daniel Chabrowski b42a49eb4b Limit pipeline selection to Xe 
Related-To: NEO-6624
Signed-off-by: Daniel Chabrowski <daniel.chabrowski@intel.com>
 2022-05-09 13:16:43 +02:00
Daria Hinz 5ba56690f5 Revert "Set only base values in GT_SYSTEM_INFO for AOT" 
This reverts commit b1f622d700.

Signed-off-by: Daria Hinz <daria.hinz@intel.com>
 2022-05-09 12:42:09 +02:00
Dominik Dabek 99c424b6ff Enable update task count from wait on DG2 
Related-To: NEO-6948

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
 2022-05-06 16:01:30 +02:00
Dominik Dabek 6e8cabdce5 Split wait for timestamps to queue and event 
On PVC both enabled.
On DG2 only for events.

Related-To: NEO-6948

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
 2022-05-06 15:34:47 +02:00
Lukasz Jobczyk 0b4ea8d2eb Do not enable engines round robin on all xe_hp and later products 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2022-05-06 12:30:53 +02:00
Bartosz Dunajski f8ce86b116 XE_HPC: Fallback path to fix PAT_INDEX programming 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2022-05-05 15:06:21 +02:00
Bartosz Dunajski 85b47476b6 Add MemorySynchronizationCommand to Blit commands estimation 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2022-05-04 12:25:56 +02:00
Daria Hinz b1f622d700 Set only base values in GT_SYSTEM_INFO for AOT 
In most cases, there was code redundancy, which was minimized in this change.
The setupHardwareInfoBase extraction will also be used in ocloc.

Signed-off-by: Daria Hinz <daria.hinz@intel.com>
Related-To: NEO-6910
 2022-05-04 10:36:26 +02:00
Compute-Runtime-Validation ebe8d051dc Revert "Enable task count from wait on DG2 and later" 
This reverts commit bd6c9a222b.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2022-05-01 09:35:38 +02:00
Trojanowski, Karol bd6c9a222b Enable task count from wait on DG2 and later 
Signed-off-by: Karol Trojanowski <karol.trojanowski@intel.com>
 2022-04-29 14:27:54 +02:00
Mateusz Jablonski ac01f74924 style: fix gcc12 compilation errors 
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2022-04-28 18:07:15 +02:00
Filip Hazubski 55dcca993c Apply getPaddingForISAAllocation PVC implementation to PVC and later platforms 
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2022-04-27 15:55:39 +02:00
Lukasz Jobczyk 7eb70775ea Flush caches for cross CSR dependencies 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2022-04-27 15:03:27 +02:00
Compute-Runtime-Validation 903cf766b3 Revert "Move shared helper files to shared directory" 
This reverts commit 459524f129.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2022-04-27 13:12:16 +02:00
Filip Hazubski 459524f129 Move shared helper files to shared directory 
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2022-04-27 10:34:42 +02:00
Bartosz Dunajski 192ffa4c26 Add support for allocating RT globals 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2022-04-25 17:56:09 +02:00
Filip Hazubski 944319b3d9 Correct media compression format for blitter operations on planar images 
Set most significant bit for chroma planes.
Move common logic to helper function.

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2022-04-22 17:02:16 +02:00
Bartosz Dunajski 06fa316a75 Assign pat_index to BO during creation 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2022-04-21 13:25:13 +02:00
Kamil Kopryk 7f08a9d993 Remove adjustHwInfoForIgc helper 
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
Related-To: NEO-6738
 2022-04-20 10:04:36 +02:00
Mateusz Jablonski b5b8762faf refactor direct submission: Pass command stream receiver to ctor 
Related-To: NEO-6643

Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2022-04-19 23:02:55 +02:00
Rafal Maziejuk a970622cc1 Print slice index in printImageBlitBlockCopyCommand function 
Signed-off-by: Rafal Maziejuk <rafal.maziejuk@intel.com>
 2022-04-19 12:04:50 +02:00
Lukasz Jobczyk b15c8e971c Move isTimestampWaitSupported method to different file 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2022-04-15 13:20:02 +02:00
Dominik Dabek 8d1ad5a4f3 Refactor: use stack vector for root device indices 
Stack vector will not cause dynamic allocations in most circumstances
ie. number of root device indices not more than 16

Related-To: NEO-6837

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
 2022-04-14 14:05:42 +02:00
Brandon Yates d70b1a2e2a Filter L0 Debugger support by platfom 
Related-To: NEO-6678
Signed-off-by: Brandon Yates <brandon.yates@intel.com>
 2022-04-13 13:03:40 +02:00
Krystian Chmielewski ee0d183cf9 Handle legacy hasBarriers properly 
Previous change regarding NEO-6785 added encoding of number of barriers
to specific value representation depending on hardware that we program for.

In patch token format encoding of number of barriers is sent via
hasBarriers field in a token.
In zebin true number of barriers is sent via barrier_count field in
zeInfo.

To remove this discrepancy, translate encoded number of barriers into
true number of barriers in legacy format.

Resolves: NEO-6785

Signed-off-by: Krystian Chmielewski <krystian.chmielewski@intel.com>
 2022-04-12 09:44:10 +02:00
Bartosz Dunajski 884d729e4e Improve pat index programming on linux 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2022-04-12 08:18:20 +02:00
Daria Hinz ce645f13b7 Encode PRODUCT_CONFIG value into fatbinary 
Change modifies the encoding entry in fatbinary for platforms.
If numbering in -device is used, the value PRODUCT_CONFIG will be encoded.
The functionality that returns the correct product config values has
also been added.

Related-To: NEO-6744
Signed-off-by: Daria Hinz <daria.hinz@intel.com>
 2022-04-11 15:09:17 +02:00
Krystian Chmielewski 2c1bfbb5b2 Encode number barriers 
When programming number of barriers use BARRIER_SIZE enumeration.
Resolves: NEO-6785

Signed-off-by: Krystian Chmielewski <krystian.chmielewski@intel.com>
 2022-04-08 10:32:23 +02:00
Daniel Chabrowski 3c4b442c79 Virtual engines for BCS 
Signed-off-by: Daniel Chabrowski daniel.chabrowski@intel.com
Related-To: NEO-6591
 2022-04-07 11:52:29 +02:00
Zbigniew Zdanowicz f4407064a4 Refactor store register mem encoder to include partition parameter 
Related-To: NEO-6811

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2022-04-06 14:00:56 +02:00
Daniel Chabrowski eaba246464 Test prelim command stream and clos cache 
Signed-off-by: Daniel Chabrowski daniel.chabrowski@intel.com
Related-To: NEO-6591
 2022-04-05 16:48:00 +02:00
Filip Hazubski d2462ff8fb Add debug flag to control ISA allocation padding 
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2022-04-04 15:12:30 +02:00
Bartosz Dunajski 08e3853982 Debug flag to add extra MI_MEM_FENCE for DirectSubmission 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2022-03-30 16:07:25 +02:00
Compute-Runtime-Validation 91cfd3cd1a Revert "Unify command/ring/semaphore buffers placement" 
This reverts commit e035199de4.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2022-03-30 14:05:47 +02:00
Sebastian Luzynski cf906030ac Add neon intrinsics for aarch64 
Related-To: NEO-6452

Signed-off-by: Sebastian Luzynski <sebastian.jozef.luzynski@intel.com>
 2022-03-29 18:22:32 +02:00
Rafal Maziejuk c7d8915dd4 Add debug variable to print XY_BLOCK_COPY_BLT command details 
Signed-off-by: Rafal Maziejuk <rafal.maziejuk@intel.com>
 2022-03-29 18:15:13 +02:00
Mateusz Jablonski e035199de4 Unify command/ring/semaphore buffers placement 
put them all to the same memory location

Related-To: NEO-6698
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2022-03-29 17:55:48 +02:00
Zbigniew Zdanowicz 9858438121 Limit multiple partition count to compute command lists 
Related-To: NEO-6811

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2022-03-29 07:29:08 +02:00
Konstanty Misiak 174c27eb31 Fix CFEFusedEUDispatch debug flag 
Signed-off-by: Konstanty Misiak <konstanty.misiak@intel.com>
 2022-03-28 12:32:05 +02:00
Jobczyk, Lukasz d77a6cbe4b Enable task count update from wait 
Signed-off-by: Jobczyk, Lukasz <lukasz.jobczyk@intel.com>
 2022-03-28 11:09:55 +02:00
Filip Hazubski 586e8510de Remove unneeded include 
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2022-03-26 09:55:25 +01:00
Lukasz Jobczyk a230f267e1 Poll task count indefinitely on high throttle command queue 
Resolves: NEO-6781

Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2022-03-25 10:06:16 +01:00
Compute-Runtime-Validation 0c064ccf4c Revert "Enable task count update from wait" 
This reverts commit 5118a5d3a6.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2022-03-25 00:09:52 +01:00
Kacper Nowak 5477cb6b8c Correct typo 
- Replace "aligMent" with correct "aligNMent"
Signed-off-by: Kacper Nowak <kacper.nowak@intel.com>
 2022-03-24 17:46:49 +01:00
Lukasz Jobczyk 5118a5d3a6 Enable task count update from wait 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2022-03-23 11:38:50 +01:00
Jitendra Sharma f52f3df274 Add platform specific getter of debug surface size 
For different platforms based on number of available threads
and debug surface layout, calculate max debug surface size.

Related-To: NEO-6676
Signed-off-by: Jitendra Sharma <jitendra.sharma@intel.com>
 2022-03-22 12:18:40 +01:00
Rafal Maziejuk 6ee5c0f677 Add appendBaseAddressOffset function to BlitCommandsHelper 
Signed-off-by: Rafal Maziejuk <rafal.maziejuk@intel.com>
 2022-03-18 16:46:15 +01:00
Zbigniew Zdanowicz 1540d06c25 Correct infinite timeout argument for event synchronization 
Related-To: NEO-6242

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2022-03-18 13:07:09 +01:00