Commit Graph

1991 Commits

Author SHA1 Message Date
25d9e4533d DRM Graphic allocation assigns original hostPtr as cpuPtr
Change-Id: I9ba282b130b5fb9b674e1ceb2f87183f218ab140
Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
2019-08-28 13:35:18 +02:00
3371ed12f6 Refactor DrmMemoryManager::freeGraphicsMemoryImpl
- remove default value from synchronousDestroy param in
  DrmMemoryManager::unreference
- unreference BufferObject in synchronous mode  before release
  GPU and CPU memory
- add ULTs

Related-To: NEO-2877

Change-Id: I8065c27923cf4259a0fcd0f6d8d6d5b7c4b810c0
Signed-off-by: Igor Venevtsev <igor.venevtsev@intel.com>
2019-08-28 12:30:20 +02:00
18982bd016 Move memory for slm window to memory manager
remove redundant methods from MockDevice

Related-To: NEO-3007

Change-Id: I9cc819b9c9118dbb667f5bf87d1bf15787f9b67f
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2019-08-28 12:09:17 +02:00
c7ad27d430 Add a HostToHost copy type in the Memcpy
Related-To: NEO-3570, NEO-3610

Change-Id: I84f8e2150b2d3760d968e94ae85638d91cb77a54
Signed-off-by: Jobczyk, Lukasz <lukasz.jobczyk@intel.com>
2019-08-28 10:55:07 +02:00
e7a4635dd6 Add mechanism to register instruction cache flushes.
- With this mechanism csr with add pipe control with instruction cache flush
prior to enqueue, to make sure that this cache is flushed.

Change-Id: I664f212427686e9957027c7cf6c0dab17d2a3cac
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
2019-08-28 07:56:41 +02:00
84c801e28b Remove OCL object from MemoryProperties 8/n
Refactor MemoryPropertiesFlags to bitfield

Related-To: NEO-3132
Change-Id: I7092b16d15cec962e94c992696bd9845ce86f642
Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
2019-08-27 17:28:47 +02:00
90266b4a37 Move autogenerated files to core directory
Change-Id: Ie23411f9cfce068390f116c557000a665a62a337
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2019-08-27 17:19:39 +02:00
be17471f8a Wire in L1 MOCS index for stateless accesses to csr.
Change-Id: I1712a696e9c02ef042a08c80bfa87e80e82ada5f
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
2019-08-27 15:48:12 +02:00
c7c6068d1f Add classes for sub devices concept
Related-To: NEO-3007

Change-Id: I27dd4b91e286ba1b75f4b50bec96d98df37983e1
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2019-08-27 15:38:10 +02:00
4503e04083 Align a unified memory pointer during memcpy
Related-To: NEO-3570, NEO-3610

Change-Id: Id4d41da17a28ef512ba4c90bd71f419a24608d88
Signed-off-by: Jobczyk, Lukasz <lukasz.jobczyk@intel.com>
2019-08-27 15:37:41 +02:00
b218c7fa16 Add helper for low priority engine type
Change-Id: I1d46e73f94d2827ba44de86a752d03830ff2b7e3
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2019-08-27 14:13:53 +02:00
bd6c2b0f1e Revert "Flush instruction cache."
This reverts commit 3d062620a7.

Change-Id: I615d6d7e4298588cffd8f543e1c56045278c8c98
2019-08-27 13:40:03 +02:00
7749f28f70 Remove not needed methods from Device.
Change-Id: I179089a4b248ba1ebd6502e001fda18238c4767b
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2019-08-27 09:07:10 +02:00
7a5bc461eb Add residency handler for TBX
Change-Id: I6c01d065ff3372fe7583ed50ed51595ebeb53e54
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2019-08-27 07:59:47 +02:00
cb4e5576cb Pass proper dispatch flags.
- add new policy to select L1 caching
- this is when kernel doesn't have any stateless writes

Change-Id: I3948e652797420976159bbfec2c2a154eb9e18ee
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
2019-08-26 18:15:54 +02:00
ea095418ad Stop using cache policy defines.
- Replaced by Hardware Helper code.

Change-Id: I55026ee33fcaaffbfb529e1878ae4f7033f62ee5
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
2019-08-26 17:36:50 +02:00
6566eb3193 Move Linear Stream to core folder
Change-Id: I962ebd6e9075fcab9d7b6211524093109e62d382
Signed-off-by: Daria Hinz <daria.hinz@intel.com>
2019-08-26 17:00:53 +02:00
e851359e32 Start using real mocs index to call state base address programming.
- After this change we start using real MOCS index as an argument to sba
programming
- We also start tracking real MOCS index in Command Stream Receiver.

Change-Id: Id34cffd7e58cb7363df02ac76f82bf377f4bbd77
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
2019-08-26 16:14:36 +02:00
aeb84b3e20 y-tiling interface cleanup
Change-Id: If7e5ab7135eaa71d9215c87c2fc46188ffd42b02
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2019-08-26 15:00:26 +02:00
ba2233dc6a Move getMocsIndex to BDW plus file.
Change-Id: I0b169981a293e86446d0cfe563ec73db26c83a62
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
2019-08-26 14:09:11 +02:00
8135babfc4 Dont use default engine tag address in DeviceQueue
Change-Id: I84b9ecd9a9e7c1ffe620af8ad54fd5d48532fa5b
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2019-08-26 13:30:18 +02:00
3d062620a7 Flush instruction cache.
Change-Id: I2ae0c40ae99cd8e0c126c8588e6df293e29d3db3
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
2019-08-26 11:25:51 +02:00
b0f662a148 Remove bitwise operations on bools from os_interface/linux
Change-Id: Id92840417824dc0b95d5d8b4ab8cda940f8fa8f4
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2019-08-26 09:42:05 +02:00
a3f5e70e6a Remove not needed virtual.
Change-Id: Ifb335a67753bc99a74d4c991d48c8d83e9e3d826
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
2019-08-26 09:25:59 +02:00
918711c865 Add helper function to return proper mocs index basing on inputs.
Change-Id: I062891d02607fec932e0cb9ae84fe858e9d9e098
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
2019-08-26 09:17:09 +02:00
f86bbd99d2 Include hw_cmds for specific gen when possible
Change-Id: I3fc55321f92d02419c4c04e6d1bc28b09b306c0f
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
2019-08-24 11:09:26 +02:00
c24bbac25f Refactor scratch offset programming.
- no need for virtual functions and helpers, this is just a constant that
is the same everywhere.

Change-Id: Id0ebfd2eed26e26f90f104ec456dcc997be70211
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
2019-08-23 13:42:58 +02:00
4692bc1289 Update GMM H/V alignment API
Change-Id: I2713b912cd93ae28de6c7ef6a8348107f0902368
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2019-08-23 12:15:33 +02:00
9a67b2d784 Add flag to kernel that specifies whether stateless writes are used.
- currently no compiler support yet, hence it returns true.
- minor cleanup of kernel tests.

Change-Id: Ic153810b1a6062d0bae22d6faab5db601764dd98
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
2019-08-23 11:56:04 +02:00
51d0219f65 Add helper method for ForceOtherHVALIGN4 flag
Change-Id: I3823792b44459fabd3b4576ba80b6e5c6d7a3887
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2019-08-23 10:36:00 +02:00
7912b9fa94 Remove OCL object from MemoryProperties 7/n
Wire in MemoryPropertiesFlags support to:
-isLinearStorageForced

Related-To: NEO-3132
Change-Id: Ib29c4b1c8a30f2449d7fcb2778cb827baf61915e
Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
2019-08-23 10:08:23 +02:00
bd63618190 Remove OCL object from MemoryProperties 6/n
Wire in MemoryPropertiesFlags support to:
Image functions:
-validate
-validatePackedYUV
-validateImageTraits

Related-To: NEO-3132
Change-Id: I4d71d4170704d2117d6d17602f5f2ad0f30ab1f8
Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
2019-08-23 09:28:23 +02:00
f362739521 Refactor L3 programming.
- Do not do it via member setting.
- Utilize DispatchFlags

Change-Id: I75d4c8ea6c1e10ca0edeeb0d1c3883a549c1cb1f
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
2019-08-23 08:46:27 +02:00
3528179434 Add preview to Unified Shared Memory extension name.
Change-Id: I1fba3b275a280823abc9f57ed76c130bfa5f44a9
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
2019-08-23 08:37:00 +02:00
026f06cc50 Add function getPitchAlignmentForImage
Related-To: NEO-3207
Change-Id: I39ef8624ad7172a3e2acf9072e1e3d5d1b6fcc34
Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
2019-08-23 00:59:13 +02:00
d566267025 Revert "Update GMM H/V alignment API"
This reverts commit 5edd2af916.

Change-Id: I4ad950229f14b44a9b56a4b4d52c3b294c2c7088
2019-08-22 16:36:00 +02:00
3507f027d4 Add per platform toggle for integer 64bit atomic extensions
Related-To: NEO-3649

Change-Id: Ic97566a91d50911c006e24a23d448281a8d2df64
Signed-off-by: Cencelewska <katarzyna.cencelewska@intel.com>
2019-08-22 15:24:13 +02:00
5edd2af916 Update GMM H/V alignment API
Change-Id: Iceda9befa200ccfac0343921c24cb4a7d36fa68a
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2019-08-22 11:32:50 +02:00
9b198a113d Refactor getCmdSizeForPipelineSelect
Change-Id: Ib601974250d4a3576bf90d74ba36c4216c3cb1af
Related-To: NEO-3457
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
2019-08-22 09:01:20 +02:00
a103ce177e Add support for testing if L3 is configurable
Change-Id: I639e28171d0009566d7a2f04cac679d14f0340b1
Signed-off-by: Sebastian Sanchez <sebastian.sanchez@intel.com>
2019-08-21 11:40:42 -07:00
cb73ea7361 Add debug variable to override state less mocs index.
Change-Id: If1f37e56dd62927f96999d35530f210f577996b1
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
2019-08-21 16:18:29 +02:00
5c6517b6b5 Add PipeControl prior to PipelineSelect WA
Change-Id: Id793ef5b6e7ef771b5b7a1d0fde1fb6aef6e7a5a
Related-To: NEO-3457
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
2019-08-20 10:24:49 +02:00
cb93dd8d06 Remove OCL object from MemoryProperties 5/n
Wire in MemoryPropertiesFlags support to isReadOnlyMemoryPermittedByFlags

Related-To: NEO-3132
Change-Id: I3b14d0a49d78ad9d29e055e85f8ab7e584af60d2
Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
2019-08-20 10:15:50 +02:00
ea47f9745d Remove OCL object from MemoryProperties 4/n
Wire in MemoryPropertiesFlags support to:
-getAllocationPropertiesWithImageInfo
-getAllocationProperties
-fillPoliciesInProperties

Related-To: NEO-3132
Change-Id: I70d7c2d2ebb4814f4d36518b9098a97c88b88f46
Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
2019-08-20 09:46:31 +02:00
c2a0031a9b Fix includes related issues
Related-To: NEO-3241

Change-Id: I1715e3e0dcc37ad29759cc03a2b4b894843b5bbb
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2019-08-19 21:57:18 +02:00
55ca12ea92 Do not set hostPtr in case of CL_MEM_COPY_HOST_PTR.
Change-Id: If2356125e36fb08221d0758020c17341808fa7dd
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
2019-08-19 17:32:25 +02:00
68134974c5 Expose unified shared memory extension.
-Available only when device already supports OpenCL 2.0

Related-To: NEO-3148
Change-Id: Ie2bce908c5e49666d5a18c4b0eb21ff39a3e5a68
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
2019-08-19 13:49:02 +02:00
ba9c21cf82 Refactor functions
Use unified access pattern in obtainPipeControlAndProgramPostSyncOperation
Rename getExecutionEnvironment to peekExecutionEnvironment

Related-To: NEO-3210
Change-Id: Iedf30833704e2fc4b8822f5d19d36a230f140f27
Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
2019-08-19 12:19:18 +02:00
62b0f0a220 Refactor addPipeControlWA, PipeControlWArequired
Related-To: NEO-3210
Change-Id: I0516154b323e29eeb697bf2253ca08ae1ce150d8
Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
2019-08-19 10:47:28 +02:00
ced22ffaf2 Enhance the list of one time AUB writable types.
Change-Id: I1eba658aa83e0d3e44009e7eca928f5916d6f9ce
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
2019-08-14 15:23:31 +02:00