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749 Commits

Author SHA1 Message Date
Jaime Arteaga
6614698997 Add multi-device support to events 
Change-Id: I544d2409fa5ad7c2b64f7bfd081469e80d4f9c73
Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
 2020-10-15 12:54:51 -07:00
Artur Harasimiuk
51c25adc85 fix single-sku builds 
Change-Id: Ib1aef5f27148203b808ffb698878c89a410193c4
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
 2020-10-15 19:45:56 +02:00
Mateusz Hoppe
067ae67954 Introduce FRONT_WINDOW heaps inside INTERNAL heaps 
Related-To: NEO-4550

Change-Id: I1979afb20881bcad7999af3ac5fd4f407b85ccc7
Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
 2020-10-15 17:18:31 +02:00
Mateusz Jablonski
97154f7f98 Use ProgramInfo instead of Program in sip kernel 
Related-To: NEO-5001
Change-Id: I58eda3ecc52fe1215ea8bbc35f97eea3a9d848e0
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2020-10-15 16:41:18 +02:00
Lukasz Jobczyk
2d781e5934 Add missing USM host allocation flag 
Change-Id: I5658d5574fd522cff072adcc679f04805daabf12
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2020-10-15 12:12:55 +02:00
Mateusz Jablonski
fd492f28b0 Correct useSystemMemoryPlacementForISA 
Related-To: NEO-5156
Change-Id: Iee6df3e06eea5707b3b6cb45ac50e9880ee4dfb4
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2020-10-15 10:22:30 +02:00
Maciej Dziuban
21988a81e1 Enhance debug flag for post blit commands 
Change-Id: Ia5dccd083d84ab1b7a1e772f7fd1d5344aa3c6b1
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
 2020-10-15 09:46:22 +02:00
Maciej Plewka
971969ba15 Link shared mocks to shared tests 
Change-Id: Id3bd943e8f0a430cd672b08a5f088027005e36a6
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2020-10-14 18:39:58 +02:00
Lukasz Jobczyk
f825364770 Unprotect memory after migration to CPU 
Change-Id: I280296422ec30583752a0b62c7c1c8777aa84c32
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2020-10-14 11:14:32 +02:00
Lukasz Jobczyk
e34ba2a233 Create internal BOs with mmap by default 
Change-Id: I34f79ae2e44cf087c3fe4ec6ab673e04db04e65e
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2020-10-14 10:37:36 +02:00
Lukasz Jobczyk
d7df1ee5dd Rename createAllocWithAlignment parameter 
Change-Id: If1b43f3fada0f85323d67ff6b43a6165d5b578ca
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2020-10-13 15:47:58 +02:00
Lukasz Jobczyk
8892ee3f1f Align mmaped bo address properly 
Change-Id: I010f6619821ad715bb6f0e9640be19943a45abd8
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2020-10-13 14:11:08 +02:00
Slawomir Milczarek
eb8f5fa301 Get CL Device Name with device ID appended at the end 
Related-To: NEO-4744

Change-Id: I8a9a791a634f9c0c444695036d96e3c959c90de0
Signed-off-by: Slawomir Milczarek <slawomir.milczarek@intel.com>
 2020-10-13 14:00:33 +02:00
Michal Mrozek
324150dd37 Do not track Kernel ISA as new resources. 
Change-Id: Ib112952071b76ba471d046c13c556422c415ba96
Signed-off-by: Michal Mrozek <michal.mrozek@intel.com>
 2020-10-13 13:34:35 +02:00
kvladimi
72d3cd50d7 Adding information about -help and reformatting VC options to 80 symbols 
Change-Id: Id9498c51d723f5b5583466bd6f1b2f62833f0902
 2020-10-13 12:51:29 +02:00
Pawel Wilma
0c3d430f50 W/A for disabling RCC RHWO for compressed media surfaces on gen12lp 
Whenever media compressed surface is used, the RCC Read-Hit-Write optimization
disable bit (14) has to be set in Common Slice Chicken1 register (7010h).

Related-To: NEO-4982

Change-Id: I71b91b52692252459da05b737838eb4854575974
Signed-off-by: Pawel Wilma <pawel.wilma@intel.com>
 2020-10-13 11:52:15 +02:00
Zbigniew Zdanowicz
ca023fa532 Fix L3 and Math programming 
Change-Id: I4ffd729beeed95b0806dd284665c72fb424b0ffc
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-10-13 11:41:38 +02:00
Mateusz Jablonski
b77f9bf8d1 Remove Program::setDevice 
device should be passed to constructor

Related-To: NEO-5001
Change-Id: If4c64ec405bdd3beaccc7c09644e22fc98a02249
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2020-10-12 20:22:45 +02:00
Spruit, Neil R
976dad2e17 Updated BaseSurfaceStateAddressAlignment to PageSize to handle Block R/W in L0 
- Block R/W in kernels requires a minimum of 16B alignment/OWORD
alignment to properly work without data corruption.
- Level Zero currently writes Base Surface State addresses alignment to
4B vs OpenCL writes Base Surface State addresses aligned to PageSize for
4KB.
- Added a function in encode buffer to verify that at a minimum the size
being encoded has the minumum alignment of 4B which is supported, but
will not support Block R/W

Change-Id: I6486c2cbbb0008834c779bf54918388d79c193bb
Signed-off-by: Spruit, Neil R <neil.r.spruit@intel.com>
 2020-10-12 19:14:25 +02:00
Bartosz Dunajski
27f9a95af2 Refactor: Common helper for Blit and CPU memory transfers 
Change-Id: Icc61f82517e75e3066e441494af3bf9a7ffbbeef
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-10-12 18:29:42 +02:00
Lukasz Jobczyk
99f0d2b1db Add debug flag for BO mmap creation 
Change-Id: I1b0dc8b9328bf3aab64ceeaf9f1c5aeb4199eb08
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2020-10-12 12:36:28 +02:00
Kamil Diedrich
9e463ab45f Track all ssh in cmdList 
Change-Id: Ibffb7b7b406e5e17d4ffb971fd0789557c879367
 2020-10-12 12:12:12 +02:00
Maciej Dziuban
38ca6e9862 Disable L1 for Gen12lp 
Change-Id: I3b0ec2a6ea9a3bb72507ff66d314bfb1ad7a6a81
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
 2020-10-12 11:18:55 +02:00
Mateusz Hoppe
0e935b0e10 Add allowCapture flag to BufferObject 
Related-To: NEO-5026

Change-Id: I69a9f270272a13fccdd1d8dd8b13ad03ef93cb79
Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
 2020-10-09 17:04:43 +02:00
Lukasz Jobczyk
a939c89d91 Create internal BOs with map offset 
Resolves: NEO-5097

Change-Id: I842f3d482420373cc630d5bfc034e229fa2cb30c
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2020-10-09 16:38:03 +02:00
Filip Hazubski
da524fa03d Correct Intermediate Language related implementation 
Change-Id: Ib2bdd21c255245767df787797bb5cfe05482e489
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2020-10-09 16:00:56 +02:00
Filip Hazubski
410e3c0ced Add ULT for Linker::patchDataSegments 
Verify blitter usage.

Change-Id: Ic6dc10df967b8b22a86c29dee6a8df0d357ddf65
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2020-10-09 15:35:12 +02:00
Maciej Plewka
2ebee73e4b Unify bindless debug flags 
Change-Id: I6a9313722eed01b935707e93cad532adddcc78af
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2020-10-09 14:49:50 +02:00
Zbigniew Zdanowicz
bf32740f97 Move BTI programming to shared code 
Change-Id: Ie9d67c1d883f24cfec13ea1618d834d746c0d5be
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-10-09 13:56:44 +02:00
Bartosz Dunajski
fb0651521d Linker: Fix incremental patching for local memory allocations 
Change-Id: Ib85e4a2abc8a62477003853aa0c35f8107444f4e
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-10-09 09:13:42 +02:00
Mateusz Jablonski
fc090f74c6 Store device binary per root device in program 
Related-To: NEO-5001
Change-Id: I9834f6894625031c734c68ebf210e6042c470ec7
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2020-10-08 19:05:04 +02:00
Jaroslaw Chodor
91a36bf277 ocloc - preserve input spirv in output elf 
Change-Id: I1205a5c655d643e0d6150f9dc7edaae30ad15225
 2020-10-08 15:37:57 +02:00
Zbigniew Zdanowicz
4e3679b8ae Move local ids generation code to shared directory 
Change-Id: I5b0486ceae8d67d0c1d1be56a756c102226d7e2a
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-10-08 15:02:36 +02:00
Maciej Dziuban
8fcd51c2c8 Do not obtain command stream if it will not be needed 
Change-Id: Id7fa1c6b78e71a085084f8fcb66a7b8e873ad2bc
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
Related-To: NEO-5120
 2020-10-08 12:24:03 +02:00
Kamil Diedrich
960860e4cb Fix reservation size 
Change-Id: I1cc3d4405b00365908c5915c9d2a1c512d572530
 2020-10-08 10:57:08 +02:00
Bartosz Dunajski
d07362c992 Use blitter to initialize Global surface if required 
Change-Id: I53cc532a5b5edd16a32deaf987f85db4224b9945
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-10-07 17:11:48 +02:00
Bartosz Dunajski
595f374634 Dont use blitter for local memory transfer if not available 
Change-Id: I5f43113498b59e3f1b8cb280c9feeccae8ff6140
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-10-07 15:55:22 +02:00
Kamil Diedrich
67e2853857 Add missing mockable_virtual in code 
Change-Id: Ia8d041b68163a99cf4e9e399e825d39798425544
 2020-10-07 14:25:04 +02:00
Mateusz Hoppe
5fd113dcb3 CommandContainer.reset() clears lastSentNumGrfRequired 
RelatedTo: NEO-5137

Change-Id: Icaad8224ee24f8c927b75e2efb17585a8b79918a
Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
 2020-10-07 12:24:04 +02:00
Kamil Diedrich
ce7e293a99 Extend scratch implementation 
Change-Id: I1bbc0c9be287b1411276b1e61a7ec1c8db238f3f
 2020-10-07 11:39:04 +02:00
Igor Venevtsev
bd9695a19a Get rid of UNRECOVERABLE_IF in MemoryManager constructor 
Related-To: NEO-5053

Change-Id: Ibf955c760e61e34c4d38cbb5071ef712bae1c518
Signed-off-by: Igor Venevtsev <igor.venevtsev@intel.com>
 2020-10-07 11:18:56 +02:00
Zbigniew Zdanowicz
47f5867e8f Move common code to shared directory 
Change-Id: I5f604de01e06d35cc1e045fffdd4a26d88ffca8c
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-10-07 10:55:39 +02:00
Filip Hazubski
3f9d95fe46 Add ULT for allocateGlobalsSurface 
Verify blitter usage.

Change-Id: Ib0a726479097bb662a571f904ed04a832f426752
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2020-10-06 17:25:24 +02:00
Maciej Plewka
4dc3827b8e Prepare object lib for precompiled builtins in bindless mode 
Releated-To: NEO-5138

Change-Id: I18e564a9e32041fba5e887bc18d2195a1c4ddda8
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2020-10-06 16:57:11 +02:00
Andrzej Swierczynski
bdf8c5fc90 Extend UnifiedMemoryProperties constructor to take device bitfield 
Related-To: NEO-4722

Change-Id: Ice185f1792635922e9bb89cd7329e6501bc585e0
Signed-off-by: Andrzej Swierczynski <andrzej.swierczynski@intel.com>
 2020-10-06 16:35:08 +02:00
Zbigniew Zdanowicz
820efffdd0 Switch default CPU cache flush to disabled in direct submission 
Change-Id: I1a5e5f67d3e6af129aeb611f203c243d892321bb
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-10-06 15:19:32 +02:00
Zbigniew Zdanowicz
28ef5fa709 Move pipecontrol w/a estimation to dedicated class 
Change-Id: I8ceaa2dff94dd7148daf921568fd30f098e5dae4
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-10-06 15:02:37 +02:00
Zbigniew Zdanowicz
ce1b669cda Use single class to program load register command 
Change-Id: I90fe084409588cb32f0ac43a3db5082047d7a68b
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-10-06 13:45:35 +02:00
Maciej Dziuban
138f04bdcd Enable L1 cache for Tigerlake 
Change-Id: I33513ed084f9d06ceca11315cac03f1b682db535
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
Related-To: NEO-4832
 2020-10-06 13:26:54 +02:00
Konstanty Misiak
ec054a87da Fix builtin compiling with ZEBin 
Related-To: NEO-5020

Change-Id: I2698db921e8b6c61ee592a0d6611dc38173a1688
Signed-off-by: Konstanty Misiak <konstanty.misiak@intel.com>
 2020-10-06 13:04:45 +02:00