Performs minor renaming (mostly capitalization) in order to align with
specification.
Renames L1_CACHE_POLICY to L1_CACHE_CONTROL.
Related-To: NEO-13147
Signed-off-by: Vysochyn, Illia <illia.vysochyn@intel.com>
This modification serves to simplify the integration of generated
compute walker structures.
Related-To: NEO-13147
Signed-off-by: Vysochyn, Illia <illia.vysochyn@intel.com>
- move various methods from specialization in cpp into correct inl files
- EncodeAtomic, EncodeMiFlushDW, EncodeMemoryPrefetch, EncodeDispatchKernel
- move methods from generic inl files that are used on single platform to cpp
- EncodeMiFlushDW
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
- share xe hpc methods in generic way
- move gen12lp and xe hpg methods into dedicated inl
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
- shift xe hpg inl file methods into specialization and generic inl files
- remove gen12lp specific implementation from main inl file
- remove not needed xe hpg inl file
- remove not needed compression inl files
- remove not used raytracing inl file
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
- remove obsolete file
- move methods from redundant compute mode file into dedicated platform files
- group same implementation into platform specific inl files
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
- move compute dispatch all walker into dedicated encoder
- group same implementations into single file
Related-To: NEO-12639
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
Finalized the implementation of the 2d block
load/store extension query. Namely, this adds
the extension info to the `DriverHandleImp`.
Also fixed support matrix in the current
implementation that incorrectly includes
MTL and ARL in the supported products. ULTs
and the implementation have both been changed
to match the true support matrix.
Related-To: NEO-11592
Signed-off-by: Jack Myers <jack.myers@intel.com>
mid thread preemption can be enabled only by ftrWalkerMTP flag
pre-Xe2 devices doesn't support MTP
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
Check indirect detection version from igc header for JIT.
Move required version to its own method.
This allows for different required versions per platform.
Related-To: NEO-12491
Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
add helper for matching all platforms except selected ones
add matchers for clos support
Related-To: NEO-10158
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
Future HW will not support cache reservation uniquely for the whole
platform. Implementation of some functions may vary between products.
Related-To: NEO-10158
Signed-off-by: Maciej Bielski <maciej.bielski@intel.com>
Implemented the product helper specializations for querying device
support for 2D block load/store operations.
The desired support matrix is both load and store is supported for PVC
and up, and unsupported forall else.
The interface for querying 2d block load/storecapabilities was
implemented in a previous PR.
Related-To: NEO-11592
Signed-off-by: Jack Myers <jack.myers@intel.com>
computeMaxNeededSubSliceSpace is no longer needed as getHighestEnabledSubSlice
already determines maximum index from all enabled subslices
Related-To: NEO-12073
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
- this feature is part of making compute walker command view
- compute walker is programed for implicit scaling but not dispatched
- together with new flag, comes the refactor to reduce number of arguments
Related-To: NEO-11972
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
When BCS3 is not available, use last available copy engine as internal.
Related-To: HSD-18039263936
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
Dominik Dabek