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53 Commits

Author SHA1 Message Date
Maciej Plewka 689ceacfe6 Fix set allocation adress in SS when offset is patched 
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2021-06-08 13:05:38 +02:00
Zbigniew Zdanowicz 8f91fcdd73 Add new atomic operation 
Related-To: NEO-5244

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2021-06-04 09:00:11 +02:00
Maciej Plewka 159404f38e Revert "Program border color once per dsh" 
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2021-05-18 12:26:58 +02:00
Maciej Plewka b943ad078f Program border color once per dsh 
Related-To: NEO-4928

Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2021-04-30 13:31:58 +02:00
Milczarek, Slawomir e5eba8be53 Add setters and getters for coherency type in render surface state 
Signed-off-by: Milczarek, Slawomir <slawomir.milczarek@intel.com>
 2021-04-13 16:12:46 +02:00
Mateusz Jablonski 8215395401 Simplify Context method 
return if context has multiple sub devices related to a given root device

Related-To: NEO-3691
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2021-03-30 10:22:15 +02:00
Zbigniew Zdanowicz e36941b171 Change argument type in EncodeMemoryPrefetch class 
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2021-03-25 18:27:07 +01:00
Bartosz Dunajski f9197d4e0d Improve memoryPrefetch method 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2021-03-24 15:12:05 +01:00
Igor Venevtsev 3df6110a17 Add extra parameters to setArgStateful() 
Signed-off-by: Igor Venevtsev <igor.venevtsev@intel.com>
 2021-02-05 12:24:27 +01:00
Bartosz Dunajski 580fdd757c Improve buffer surface state programming 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2021-02-02 14:42:18 +01:00
Bartosz Dunajski c2e333fe38 Update compression encoding interface + test traits 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2021-01-29 13:57:15 +01:00
Maciej Plewka 3ca77a6cbe Program sba for global bindless heaps 
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2021-01-04 14:23:47 +01:00
Young Jin Yoon e09ac446c4 Mask bit 0 of timestamp for event profiling 
Related-to: LOCI-1161
Signed-off-by: Young Jin Yoon <young.jin.yoon@intel.com>
 2020-12-31 23:51:12 +01:00
Young Jin Yoon da779d067f Support the AND operation in EncodeMathMMIO 
Related-to: LOCI-1161
Signed-off-by: Young Jin Yoon <young.jin.yoon@intel.com>
 2020-12-03 01:56:22 +01:00
Maciej Plewka 7a5c9d39b5 Encode dispatch kernel with global bindless heaps 
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2020-12-02 17:30:15 +01:00
Bartosz Dunajski 93ba4e646b Improve EncodeDispatchKernel 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-11-27 16:39:34 +01:00
Bartosz Dunajski 8a703c082e Add encodeExtraCacheSettings method 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-11-25 12:27:20 +01:00
Bartosz Dunajski ae3ad3e8bc Add method to adjust TimestampPacket 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-11-24 17:35:22 +01:00
Kamil Kopryk b59aa2f928 Rename command_encoder_base.inl file 
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
Related-To: NEO-4750
 2020-11-17 13:22:00 +01:00
Bartosz Dunajski 39e6548ef6 Add mi_arb_check between blit commands 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-11-17 13:07:50 +01:00
Mateusz Hoppe 65690ccb21 Fix indirect dispatch programming 
Related-To: NEO-5195

Change-Id: I82975abaa6323d27d3718ce1619748f7d83b55b4
Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
 2020-10-28 01:06:08 +01:00
Pawel Wilma 7f8b0c5b3f Global l3 invaldate for blitter engine 
Related-To: NEO-5175

Change-Id: I88b3c9333398c91a7dd799f5e52cfd9182316960
Signed-off-by: Pawel Wilma <pawel.wilma@intel.com>
 2020-10-19 16:40:03 +02:00
Zbigniew Zdanowicz ca023fa532 Fix L3 and Math programming 
Change-Id: I4ffd729beeed95b0806dd284665c72fb424b0ffc
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-10-13 11:41:38 +02:00
Spruit, Neil R 976dad2e17 Updated BaseSurfaceStateAddressAlignment to PageSize to handle Block R/W in L0 
- Block R/W in kernels requires a minimum of 16B alignment/OWORD
alignment to properly work without data corruption.
- Level Zero currently writes Base Surface State addresses alignment to
4B vs OpenCL writes Base Surface State addresses aligned to PageSize for
4KB.
- Added a function in encode buffer to verify that at a minimum the size
being encoded has the minumum alignment of 4B which is supported, but
will not support Block R/W

Change-Id: I6486c2cbbb0008834c779bf54918388d79c193bb
Signed-off-by: Spruit, Neil R <neil.r.spruit@intel.com>
 2020-10-12 19:14:25 +02:00
Zbigniew Zdanowicz bf32740f97 Move BTI programming to shared code 
Change-Id: Ie9d67c1d883f24cfec13ea1618d834d746c0d5be
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-10-09 13:56:44 +02:00
Zbigniew Zdanowicz 47f5867e8f Move common code to shared directory 
Change-Id: I5f604de01e06d35cc1e045fffdd4a26d88ffca8c
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-10-07 10:55:39 +02:00
Zbigniew Zdanowicz ce1b669cda Use single class to program load register command 
Change-Id: I90fe084409588cb32f0ac43a3db5082047d7a68b
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-10-06 13:45:35 +02:00
Maciej Dziuban 138f04bdcd Enable L1 cache for Tigerlake 
Change-Id: I33513ed084f9d06ceca11315cac03f1b682db535
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
Related-To: NEO-4832
 2020-10-06 13:26:54 +02:00
Zbigniew Zdanowicz 2717fcae54 Unify programming of atomic command 
Change-Id: I13afdb44fb83beaa8673eb6456d2a8edcb6ac047
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-10-05 13:37:52 +02:00
Zbigniew Zdanowicz 394e626db9 Refactor programming of surface states 
Related-To: NEO-5069

Change-Id: Id7442fcdcc8c7df57f00e8dc383c11869bf1a677
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-09-16 11:54:00 +02:00
Zbigniew Zdanowicz 7d506e3608 Add debug flag to enable compression in L0 USM allocations 
Related-To: NEO-5069

Change-Id: Icbfeb8d72cd764bb3c90d5c699998455f81dd3ee
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-09-14 12:47:33 +02:00
Bartosz Dunajski f6c893a801 Pass HardwareInfo to programMemoryPrefetch 
Change-Id: I5ed0ae35143ef244e08bc88ba8817ce1cb17369c
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-07-24 12:43:21 +02:00
Zbigniew Zdanowicz bac5506b62 Modify function dispatching cross and per-thread data 
Related-To: NEO-4585

Change-Id: Ia6b54b8d0c868cab5403332411655dc8c9ef4c8d
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-07-08 19:30:23 +02:00
Maciej Plewka a822503b41 Use encoder to program buffer surface state 
Change-Id: Ibe66bd9906743b021a04f1d9aad1aae4127a4f71
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2020-06-25 12:32:29 +02:00
Lukasz Jobczyk 02f2f22045 Add profiling support for blitter 
Resolves: NEO-4121

Change-Id: I29dfcf07d48100c578cbc432fee4d87dfa18e8f4
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2020-05-29 13:43:14 +02:00
Mateusz Hoppe 77e4ac0a18 Bindless addressing support in EncodeDispatchKernel 
Related-To: NEO-4607

Change-Id: Ib89b07f71f32c3a623f86212b5305b4aa02e1fb7
Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
 2020-05-12 21:02:06 +02:00
Lukasz Jobczyk 536c50234f Pass linear stream to encode MMIO 
Change-Id: I07bafc49676e31fb457a63f4655a98fd0c793389
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2020-05-04 14:48:49 +02:00
Zbigniew Zdanowicz 048c90e3b1 Remove RMW access patterns from gfx memory 
Related-To: NEO-4338

Change-Id: I8dcfca9a11f499fde44ca9754dec67fe5a5e3d46
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-04-28 15:26:22 +02:00
Zbigniew Zdanowicz 5e98368dad Remove RMW access patterns from functions programming on gfx memory 
Related-To: NEO-4338

Change-Id: I8fe555525f937e75c5439702b328c734af9af1f9
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2020-04-09 18:49:30 +02:00
Maciej Plewka 691a4ea823 Add blit copy implementation for L0 
Change-Id: I327a4cf977e166cb648ee9f3a79374f7cefa7b1b
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2020-04-09 13:36:09 +02:00
Bartosz Dunajski 3ce0450a9c Update interface for memory prefetch 
Change-Id: I1dfbbd93b97dae100de489319dcfd7d19fe1fc65
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-04-09 13:15:56 +02:00
Jaroslaw Chodor 2c25777f3c DispatchKernelEncoder refactor 
Replacing parts of DispatchKernelEncoder with KernelDescriptor

Change-Id: I1c780b04a2d3d1de0fb75d5413a0dde8b41bbe07
 2020-04-08 16:19:21 +02:00
Bartosz Dunajski 32e1b7d1a7 Add helper for encoding memory prefetch 
Change-Id: I481ec11b66ad392ba9748bb5bbb6fd0ad3ce7f12
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-04-03 18:34:39 +02:00
Maciej Plewka 5de8f3ac3d Unify setting compute mode 
Change-Id: I8fd5a0cf1a121498efbbf1edb332920578d91598
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2020-03-26 16:08:29 +01:00
Bartosz Dunajski 24c6a1ed96 Add MI_FLUSH_DW command estimation 
Change-Id: I71d966209ce1a9996bfe3f48f3d8da00156211a3
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2020-03-13 14:11:24 +01:00
Sebastian Luzynski 6eae7fc3c7 Altered unit tests to suit new MiFlushDwWA() workaround. 
Related-To: NEO-4426
Change-Id: Ib13719a711adda6fb3da3c2893898f0f31418508
 2020-03-12 14:45:44 +01:00
Sebastian Luzynski 9fadc918c7 Added empty programMiFlushDwWA() workaround. 
Related-To: NEO-3940
Change-Id: Ibc0978557004ed599a6698d76dc0f55bd26f8999
 2020-03-05 11:01:46 +01:00
Sebastian Sanchez 61ba7a838f Define MI_MATH greaterThan() function 
Define MI_MATH "greater than" function and simplify code
in encodeGreaterThanPredicate().

Change-Id: Ib1d0a3f712e672f105d0697a105e4d9b14301172
Signed-off-by: Sebastian Sanchez <sebastian.sanchez@intel.com>
 2020-02-27 10:07:53 +01:00
Sebastian Sanchez 54b2763466 Enforce ALU register type for EncodeMath interface 
General purpose register cannot be used for MI_MATH
calculations. ALU registers must be used.

To prevent passing general purpose register into the
EncodeMath interface, enforce a ALU register type
at compile time.

Change-Id: I98aa8605cde27e7003029d33b3ef3bcfb2306878
Signed-off-by: Sebastian Sanchez <sebastian.sanchez@intel.com>
 2020-02-27 08:33:04 +01:00
Sebastian Sanchez 1187eb0375 Fix encodeMulRegVal() calculation 
encodeMulRegVal() makes extensive use of encodeAluAdd().

The following problems are addressed:

* encodeAluAdd() performs an addition and saves the
  calculated result to the first register. Saving the
  result to the first register clears the calculated result.

* An array of MI_MATH buffers is setup prior to performing a
  series of encodeAluAdd()'s where the same registers are
  reused for the calculations. For calculated results to be
  carried over from one encodeAluAdd() operation to subsequent
  encodeAluAdd() operations, the MI_MATH buffer needs to be
  setup per encodeAluAdd().

Create EncodeMath<Family>::addition() to reserve a MI_MATH buffer
and performs the addition by calling encodeAluAdd().
Modify encodeAluAdd() to save calculated result to a third
register. Then, after EncodeMath<Family>::addition() is called
in encodeMulRegVal(), copy the calculated result from the result
register to the first register from the EncodeMath<Family>::addition()
operation. This will allow the calculated value to be carried over
to subsequent addition operations.

Change-Id: I9c6f8362a1ca2f7e3361aaa48d8748dd6ff0f4c8
Signed-off-by: Sebastian Sanchez <sebastian.sanchez@intel.com>
 2020-02-25 14:13:35 -08:00