don't build aub tests when aubstream is not available
use only mock aub manager in ULTs
Related-To: NEO-4446
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
Related-To: NEO-6853
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
- Added HwInfoConfig getter in RootDeviceEnvironment,
which temporarily takes HwInfoConfig from the global array
- use HwInfoConfig from RootDeviceEnvironment to
call ConfigureHardwareCustom function
- Added getHwInfoConfig in DeviceFixture
- ConfigureHardwareCustom function and few others changed to const
- Small code cleanup
This change makes that drm file is opened in nonblocking mode for prelim
kernels. In such case when calling exec buffer ioctl and get
EAGAIN (aka EWOULDBLOCK) we may return error to API level
Related-To: NEO-7144
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
With compiler LSC WAs this gives better performance.
If debugger is active, policy will not be changed ie.
will be WBP.
Related-To: NEO-7003
Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
With compiler LSC WAs this gives better performance.
If debugger is active, policy will not be changed ie.
will be WBP.
Related-To: NEO-7003
Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
This change is a baseline for tight control over
when dispatch pipeline state commands and which
pipeline state properties can be changed for a
given hardware platform
Related-To: NEO-5019
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
Certain platforms might not require prefetcher to
be disabled in direct submission. This change
provides a way to control that behaviour.
Signed-off-by: Rafal Maziejuk <rafal.maziejuk@intel.com>
Related-To: NEO-7218
This commit adds support for ZEX_NUMBER_OF_CCS flag which can be used
for limiting number of CCS engines
Format is as follows:
ZEX_NUMBER_OF_CCS=RootDeviceIndex:NumberOfCCS;RootDeviceIndex:NumberOfCCS...
i.e. setting Root Device Index 0 to 4 CCS, and Root Device Index 1 To 1 CCS
ZEX_NUMBER_OF_CCS=0:4,1:1
Related-To: NEO-7195
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
This PR includes:
- Move product config implementation from
ocloc arg helper to product config helper.
- Add default device id setting for each platform configuration.
- Add & move hw info config tests from opencl to shared
Signed-off-by: Daria Hinz <daria.hinz@intel.com>
Related-To: NEO-7112
The new regkey is EnableUsmConcurrentAccessSupport that takes a bitmask
with usm capabilities to enable concurrent access for (bit0: host, bit1: device,
bit2: shared single-device, bit3: shared cross-device, bit4: shared system)
Related-To: NEO-6733
Signed-off-by: Milczarek, Slawomir <slawomir.milczarek@intel.com>
Related-To: NEO-7003
Add L1CachePolicyHelper struct.
This struct is resposible for L1 cache policy
in build option, Surface State and stateless
caching. Currently default option for all
platforms is WBP (write by-pass)
Signed-off-by: Szymon Morek <szymon.morek@intel.com>
Related-To: NEO-7003
Add function to control l1 policy for both
stateless and surface state cache.
Signed-off-by: Szymon Morek <szymon.morek@intel.com>
Ocloc will handle any new values that may be
passed to the -device argument.
Supported acronyms are available under cmd:
ocloc compile --help
Supported patterns:
- device acronym
- release acronym
- family acronym
- version (major.minor.revision)
Fatbinary will no longer handle major.minor.revision variances,
only acronyms allowed.
Signed-off-by: Daria Hinz <daria.hinz@intel.com>
With this commit on DG2 32bit driver will check if passed host ptr for
clEnqueueReadBuffer is write combined memory. If check will be true copy
will be make on CPU.
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
Ocloc will handle any new values that may be
passed to the -device argument.
Supported acronyms are available under cmd:
ocloc compile --help
Supported patterns:
- device acronym
- release acronym
- family acronym
- version (major.minor.revision)
Fatbinary will no longer handle major.minor.revision variances,
only acronyms allowed.
Signed-off-by: Daria Hinz <daria.hinz@intel.com>