Commit Graph

39 Commits

Author SHA1 Message Date
595cfebaef Refactor PIPE_CONTROL programming
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-08-23 13:55:25 +02:00
a3903c385e Remove HW types from synchronization interface
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-07-25 13:59:26 +02:00
d4d54f5093 Cleanup includes
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
2022-07-25 09:58:38 +02:00
a9ebb49fb5 Remove device enqueue part 1
Remove:
-tests with matcher for device enqueue
-classes: MockDeviceQueueHw, DeviceQueueHw, SchedulerSimulation,
DeviceQueueHwTest, KernelArgDevQueueTest
-functions: forceDispatchScheduler, processDeviceEnqueue, dispatchScheduler

Related-To: NEO-6559
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
2022-01-11 15:29:49 +01:00
f4c151cce5 Refactor PipeControlArgs struct
Remove struct PipeControlArgsBase

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-12-22 17:13:16 +01:00
01348451db Add multi tile barrier to marker command on multi tile device
Related-To: NEO-6262

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-12-13 18:14:39 +01:00
b1df167632 Move enable_product.inl to shared
extract api agnostic validators to shared
remove not needed opencl includes from neo shared


Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2021-10-12 22:02:16 +02:00
a63b9b1273 move common files to shared/
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
2021-09-27 11:10:20 +02:00
dfe578754b Fix add pipe controll before marker profiling
Resolves: NEO-6065

Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2021-07-20 16:23:57 +02:00
9fe2dddcd3 Estimate command stream size for marker profiling
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2021-06-14 21:36:07 +02:00
3bd4bca911 Copyright header update
Dates corrected in copyright headers to reflect original publication date
(2018 for OpenCL, 2020 for Level Zero).

Signed-off-by: lgotszal <lukasz.gotszald@intel.com>
2021-05-17 20:38:19 +02:00
b01b8ba5ac Use MI_SEMAPHORE_WAIT command for event synchronization
Related-To: NEO-5508
Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
2021-04-19 11:34:52 +02:00
5a50ad098c Refactor TagAllocator
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2021-03-26 15:16:56 +01:00
7098e9c5f2 Store single KernelInfo in Kernel
remove root device index from Kernel's methods

Related-To: NEO-5001
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2021-03-22 21:30:03 +01:00
1350aa52fb Pass DispatchInfo to estimation functions
Related-To: NEO-5546

Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
2021-03-05 12:47:55 +01:00
da5f7b9216 Add debug keys to scratch register write after walker
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2021-02-26 16:13:57 +01:00
55f3c8f134 Add resolve capability for compressed USM device allocations
Related-To: NEO-5107

Signed-off-by: Slawomir Milczarek <slawomir.milczarek@intel.com>
2021-01-08 12:16:26 +01:00
b85a8ace68 Pass root device index to Kernel's methods
Related-To: NEO-5001
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2020-11-25 12:49:15 +01:00
0c3d430f50 W/A for disabling RCC RHWO for compressed media surfaces on gen12lp
Whenever media compressed surface is used, the RCC Read-Hit-Write optimization
disable bit (14) has to be set in Common Slice Chicken1 register (7010h).

Related-To: NEO-4982

Change-Id: I71b91b52692252459da05b737838eb4854575974
Signed-off-by: Pawel Wilma <pawel.wilma@intel.com>
2020-10-13 11:52:15 +02:00
4e3679b8ae Move local ids generation code to shared directory
Change-Id: I5b0486ceae8d67d0c1d1be56a756c102226d7e2a
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2020-10-08 15:02:36 +02:00
ce1b669cda Use single class to program load register command
Change-Id: I90fe084409588cb32f0ac43a3db5082047d7a68b
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2020-10-06 13:45:35 +02:00
b6cad3c206 Add estimation for cache flush commands after walker
Change-Id: I91e645be228153e99a511efd6edc4cc1f5032db6
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2020-08-19 13:09:29 +02:00
5eb047238f Move profiling methods implementation
Change-Id: I9e11cae2a264c0726770a4a4d6bc71891ce0d270
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2020-07-14 14:38:30 +02:00
def3931d0a Move adjustMiStoreRegMemMode method
Change-Id: I11395374242ac43719208157b6fa324961683f7a
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2020-07-13 17:51:47 +02:00
5a2bff7706 Debug functionality to pause before and after specified GPGPU_WALKER.
Resolves: NEO-3961

Change-Id: If797858c0f6a9758f9c1bc5472841dcfff93884b
Signed-off-by: Piotr Zdunowski <piotr.zdunowski@intel.com>
2020-05-20 11:54:54 +02:00
048c90e3b1 Remove RMW access patterns from gfx memory
Related-To: NEO-4338

Change-Id: I8dcfca9a11f499fde44ca9754dec67fe5a5e3d46
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2020-04-28 15:26:22 +02:00
b2210fa5bb Refactor MemorySynchronizationCommands class
Related-To: NEO-4338

Change-Id: Id0ae9c73293fd99f53fccc11a69ca14fa9a6d119
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2020-04-27 17:33:31 +02:00
0fdaadc505 Add blocking semaphore after N enqueue.
Change-Id: I3f0a636ed67137c3bfce6345725d3b898952e4b7
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2020-04-23 09:33:31 +02:00
e1381f89d7 Move DeviceInfo to a separate file
Related-To: NEO-3938

Change-Id: Ia255bd41a5dc8e521fe6aca3924b90be003ff93b
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2020-03-18 18:12:22 +01:00
1399e55df7 Flush cache for blit aux translation
Change-Id: I108273bee286cdeed06e0c287945099cea481a73
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2020-03-11 08:40:06 +01:00
4c781c1b98 Check if cache flush for BCS is required
Change-Id: Ia36856c46fe7da7a72dae14e2543456fb30ec409
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2020-02-28 13:45:46 +01:00
db012c9d5c Add cache flush for blit enqueues
Change-Id: I31dbeed9973c5077bf79ea7c7534b2430bca5083
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2020-02-27 16:16:20 +01:00
54b2763466 Enforce ALU register type for EncodeMath interface
General purpose register cannot be used for MI_MATH
calculations. ALU registers must be used.

To prevent passing general purpose register into the
EncodeMath interface, enforce a ALU register type
at compile time.

Change-Id: I98aa8605cde27e7003029d33b3ef3bcfb2306878
Signed-off-by: Sebastian Sanchez <sebastian.sanchez@intel.com>
2020-02-27 08:33:04 +01:00
750036742d Create only available engines
Change-Id: If7880db0dd7aa76b578d0e4e300f510ca686b825
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2020-02-24 14:06:36 +01:00
9dbeeea18f Clang-format: restore sorting includes
Change-Id: I34eb993b562c77f56d8fbd51a02ee266c1f76678
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2020-02-24 10:22:30 +01:00
7df9945ebe Add absolute include paths
Change-Id: I67a6919bbbff1d30c7d6cdb257b41c87bad51e7f
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2020-02-23 23:49:12 +01:00
370424a1e0 Change core inlcudes
Change-Id: Iaec903af420f0a92f7d86e484c83300fb9c531ad
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2020-02-23 18:46:50 +01:00
d015d3633f Add absolute path to include
Change-Id: Ib0782b4ab8d9a26ec358ecfb57721f4fe8d51b06
2020-02-23 08:47:49 +01:00
fa8e720f9e Reorganization directory structure [1/n]
Change-Id: Id1a94577437a4826a32411869f516fec20314ec0
2020-02-22 21:56:09 +01:00