- Add Indirect Heap function that will be used to program State Base Address.
- This is to allow indirect heaps to work in 2 modes, either heap will service
as whole indirect allocation OR offsets in 4GB space will be used.
Change-Id: Ic4ca1e907c1b30d2f98dc39e8ab945ce35ed6ad0
- Internal allocations may now coexists with non internal on reusable list.
- Caller now specifies if internal allocation is needed.
- If criteria are not met , then allocation is not returned.
Change-Id: I7da3a4f944768b7c8a873e44fd47248f1d76bf9e
- Allow indirect heap to work in 2 modes:
first mode is when it will be used as an allocation from 4GB allocator.
In such scenario driver will return offset from base of the allocator region.
Second mode is the legacy mode which will be used by device enqueue, this
will results in heap CPU base address being programmed in State Base Address
commands and during programming heap offset base of 0 will be returned.
Change-Id: Ica098f3278b6b6ed5036b4c5ab7461dc61d8ee86
There are differences in qPitch programming between Gen8 vs Gen9+
devices and this requires special operation when image is zero-copy.
For Gen8 qPitch is distance in rows while Gen9+ it is in pixels.
Minimum value of qPitch is 4 and this causes slicePitch = 4*rowPitch on
Gen8.
To allow zero-copy we have to tell what is correct value rowPitch which
should equal to slicePitch.
Change-Id: I58dea004e3c7f9f4dfabd154d02749c15b6b0246
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
Refactoring in ULTs around preemption:
-refactoring ULTS to not fail with default preemption mode
-fixing ULT memory leaks observed after enabling preemption
-mocking getSipKernel in ULTs (to minimize ULT execution time)
Change-Id: I194b56173d7cb23aae94eeeca60051759c817e10
- program SIP_STATE when either MidThread preemption is enabled
or kernel debugging is active
- device creates correct sip based on preemption mode and
active kernel debugging
Change-Id: I3e43b66ad00d24c2389fa4fc766dd47044b6af80
these tests should be executed after unit_tests target is complete to
ensure everything is ready in environment and to avoid sporadic failures
Change-Id: Ib9f9fdb9f4135441d17761c8dbee0868f1be404b
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
- This is to improve battery usage while waiting in busy loop on CPU
- New Kmd Notify helper to maintain dynamic parameters
- Ask OS about battery status on longer waits
- Pick different timeout when using battery and optimization is disabled
Change-Id: I5f9c8c5a9c635652aac27c707f2b55933947a7fb
there is problem with Clang 4.0 and Debug builds when bit field
initialization is used. depending on structure size we may get some bits
still set.
this bitfield comes from external component, so we don't have full
control over them. use of memset to clear structure is workaround
Change-Id: I35062517107fde37e503f1bf8909db856d566254
- On gen8 devices we are not using index to control caching, but we program
caches directly
- In such case we need to rely on values reported from GMM instead of using
Kernel Mocs indexes.
Change-Id: I6c030847509d8f39f63ac98ebd3ebd0b0907e625
- Decission about timeout enabling and value moved out of CSR
- Timeout multiplier is no longer Linux specific
Change-Id: I6858fe2f811ef13802b95e0470e310210a9dea8b
When inheriting task count from parent events,
don't take into account externally synchronized events
Change-Id: I52d861e482669a18e2aca499c813716bb4951b74
- allow creating image 2d from non NV12 image 2d
- validate image descriptor and format when create image from image
Change-Id: Ie7887e75f1450fc723dc1d1ae9ff5639d88835fc
- change the way we handle blocked commands.
- instead of allocating CPU pointer and populating it with commands, create
real IndirectHeap that may be later submitted to the GPU
- that removes a lot of copy operations that were happening on submit time
- for device enqueue, this requires dsh & shh to be passed directly to the
underlying commands, in that scenario device queue buffers are not used
Change-Id: I1124a8edbb46777ea7f7d3a5946f302e7fdf9665
