Commit Graph

1248 Commits

Author SHA1 Message Date
Milczarek, Slawomir ea028d2a9b Moved TBX and AUB CSR members to SimulatedCommonHw CSR
Change-Id: I4b49b0cf886c70127a9983dd1c9d7b15f7a45b7a
2019-01-08 09:39:28 +01:00
Mrozek, Michal 5c9f8eee23 Change the type for CL_MEM_ALLOC_HOST_PTR buffers in 64 bit.
Change-Id: Ic70d8bb3e172b80b7c20b570e5e307be460defce
2019-01-08 09:08:00 +01:00
Cetnerowski, Adam 639c14581c ULT renaming: Copy image tests
Change-Id: Id5eadd013c023dce9ba7e8e95100391fbc276db9
2019-01-08 08:48:08 +01:00
Filip Hazubski 2540e37c60 Update test cases for clEnqueueVerifyMemory
Change-Id: Ie166bb11e6e9ea385e94e9c98c8aa871e1c9148b
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2019-01-07 16:27:23 +01:00
Mateusz Jablonski aee69779fa Minor renaming in a scope of multi os context allocations:
shareable -> multiOsContextCapable
resetTaskCount -> releaseUsageInOsContext
resetResidencyTaskCount -> releaseResidencyInOsContext
isUsedByContext -> isUsedByOsContext

Change-Id: If824246a0e393b962bd12f8c63d429a0fcfcda25
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2019-01-07 11:42:43 +01:00
Milczarek, Slawomir 9083761dce Add AUBFillBuffer test with concurrent execution on CS
Change-Id: Ia01614a9763ff67d27ed68c46a5ae1b9f7dd0ee8
2019-01-04 17:04:55 +01:00
Zdanowicz, Zbigniew 767f27a483 Add calculation of default SSH size in ULTs
Change-Id: I682f7cc671ab18de7a9976e0034842df0f6134bf
2019-01-04 09:28:21 +01:00
Filip Hazubski 7e3884e22d Add clEnqueueVerifyMemory API
Change-Id: I15a514b14b9efdaeb182c7abd98b8e236932d50f
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2019-01-04 08:30:02 +01:00
Cetnerowski, Adam 7c5ec09a07 ULT renaming: Copy Buffer to Image tests
Change-Id: I685cadffed27866e6b253cd72a329ff03ffbb8ff
2019-01-03 14:31:19 +01:00
Napiatek, Henryk J f7e0decf44 Improve capturing profiling timestamps
Change-Id: I3a568afb664cae5c871e53de2c36fc8be65a4bdf
2019-01-03 12:35:56 +01:00
Milczarek, Slawomir ba2b8f05fc AubManager to accept memory bank size in bytes
Change-Id: Ie98cb7c0c0eaf93c9a2312aa87428173421609a9
2019-01-02 15:56:36 +01:00
Filip Hazubski 9d9b11734d Enhance processing Queue properties
Change-Id: I53ab00bdbfb6b11a7d9fdcaec816eead625ae737
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2019-01-02 14:52:02 +01:00
Venevtsev, Igor 73a63c7689 Fix Read/WriteBuffer for unaligned offsets
Change-Id: I08d33e80243f41174f4629c8a611e286629d2e10
2018-12-31 14:50:07 +01:00
Hoppe, Mateusz a31c446d9f Allocate non USE_HOST_PTR and non-buffer images in preferred pool.
Change-Id: Ia486c7b32932202162d6587d06dc61023e38fff6
2018-12-31 14:37:44 +01:00
Hoppe, Mateusz e195b0e380 Initialize TBX stream only when hardwareContext is not created
Change-Id: I05d8c5c395cc342ea699333dd59966913f9a98df
2018-12-31 12:14:55 +01:00
Mateusz Jablonski 56eced2faa Don't allow 32bit allocation for SVM allocation type
Change-Id: I2fbae4ce3be956a386bdc22c9b129f37d75c8e8f
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2018-12-31 10:43:08 +01:00
Kamil Diedrich fad2f8dbd1 Change auxTranslationDirectory
Change-Id: I5d433d340e945b799dbec25a22fd610312f00c0a
2018-12-28 16:46:42 +01:00
Adam Cetnerowski e8fc87b7dc ULT renaming: EnqueueCopyBufferRect
Change-Id: I95de3b07d76b973018ac384797484c902b1d5b62
2018-12-28 14:54:28 +01:00
Hoppe, Mateusz 694b643df1 Add useLocalMemory flag to ImageInfo
Change-Id: I664f9e17c0c480c2b7b2b34dcfaefa7929b9ddfe
2018-12-28 13:53:53 +01:00
Hoppe, Mateusz 20fd137437 Fix & refactor AUBCreateImageArray
- verify memory on GPU when non-system MemoryPool is used
- set correct region for IMAGE1D_ARRAY

Change-Id: I0f50d40520d2a99f124ec87b91be0c8b5f3d48be
2018-12-28 13:36:02 +01:00
Zdunowski, Piotr 7ce72bef85 Source level debugger support test improvement.
Change-Id: I14680cd4784396c788a4c0d5e38bfcfccc94fdfb
2018-12-27 12:44:29 +01:00
Adam Cetnerowski a2a4bcc33d Correct extension string typo
Change-Id: I1305a0251b06e8601e78a9b8774c285e035ff28d
2018-12-27 12:36:49 +01:00
Hoppe, Mateusz d7f498c58a Enable LocalMemory and AubStream in AubTestsWithTbx mode
Change-Id: I7958cc76be823b02782e1cb92eeacacdf35f8cc1
2018-12-27 09:48:31 +01:00
Dunajski, Bartosz 8029639898 Pin allocation with specific DrmContextId at creation time
Change-Id: Ic132fb70b1da2cf3b7c70ab899822705adb83edc
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2018-12-27 09:35:58 +01:00
Artur Harasimiuk b5f443edc0 Revert commit cc1f4bed60.
This reverts commit cc1f4bed60.
Revert "Revert "Use GPU instead of CPU address in programming commands
for HwTim(...)""

Change-Id: Iff122612bb46ba80bcc70b07b2609bfd5f0b9653
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
2018-12-21 13:25:49 +01:00
Artur Harasimiuk b2c1d68a91 Revert "Revert "Revert "Fix Read/WriteBuffer for unaligned offsets"""
This reverts commit f6757c02a4.

Change-Id: I239528e7588dc9766b10a7ce7e517d6b2cdd6375
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
2018-12-21 08:57:45 +01:00
Katarzyna Cencelewska 154917a979 Add ULTs for DriverInfoWindows
Change-Id: Id2b4456bdc33e625569eaef6e197101ba63cea7b
2018-12-21 08:45:21 +01:00
Kai Chen 1251ccc3c6 Allocate CPU address for Linux internal 32bit allocator base
The internal 32bit allocator sometimes need CPU address to access
or store data when it is in reduced address space scenario.

Change-Id: I6c0b3f9703ae3e124249b41ad7d81f03ad93ad17
Signed-off-by: Kai Chen <kai.chen@intel.com>
2018-12-21 07:11:48 +01:00
Pawel Wilma cc1f4bed60 Revert "Use GPU instead of CPU address in programming commands for HwTim(...)"
This reverts commit 6202b2222b.
"Use GPU instead of CPU address in programming commands for HwTimeStamps"

Change-Id: I085382d95538ae41068a21c628d606039bf9cdf0
2018-12-21 01:16:46 +01:00
Mateusz Jablonski 1e011f9a08 Allow to allocate shareable graphics allocation
Change-Id: I284b03b001e5b67c344d46f34048803ef9a57314
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2018-12-20 20:14:57 +01:00
Venevtsev, Igor f6757c02a4 Revert "Revert "Fix Read/WriteBuffer for unaligned offsets""
This reverts commit 71f6524197.

Change-Id: I4f31fb6fa14fb5e3b8d8bf0a1745429bcdacd5af
2018-12-20 14:16:07 +01:00
Milczarek, Slawomir 541ab5af50 TBX CSR with an option to create and operate on hardware context
Change-Id: Ib5febc8e36e61195a5fcce91e1783117717ff6cb
2018-12-20 10:59:53 +01:00
Kamil Diedrich 4b1871bf0e Add pipe control before and after buffer translation
Change-Id: I4ee32c410e1ac2bcdb3ceae203cd461de79146a5
2018-12-20 09:30:53 +01:00
Mateusz Jablonski c9e667d601 Simplify Memory Manager API [4/4]
- fill AllocationData in one place
- remove allocateGraphicsMemoryForSVM function
- refactor SVM manager tests

Change-Id: I6f4ecd70503da8031cced50ea98a54162fd8e5d3
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2018-12-20 09:01:33 +01:00
Mrozek, Michal b99cf6c3ff Image / Buffer refactor.
- do not use redescribe flag for image/buffer from other image/buffer.
- use redescribe flag only when image is redescribed via redescribe interface
- remove image specific functions from mem object
- remove redundant fields
- add new implementation of isImageFromBuffer/isImageFromImage basing
on associated mem object.
- pass associated mem object to redescrbed images.
- remove redundant setters

Change-Id: I267637a48fbc2afdad9a9f5e5e9ccd6bd0c09972
2018-12-19 21:21:44 +01:00
Cetnerowski, Adam c17d0d11d0 ULT renaming: Enqueue Barrier With Waitlist
Change-Id: Ifa889d08345001371fae4a96854878b0b413deaf
Signed-off-by: Cetnerowski, Adam <adam.cetnerowski@intel.com>
2018-12-19 14:57:20 +01:00
Hoppe, Mateusz f6790c42cf Refactor Graphics Allocation paths for Images
Change-Id: Ifa3084b18cac95289bbceeaf3669dd31567fbd3e
2018-12-19 13:49:53 +01:00
Zdanowicz, Zbigniew 3dca095ccf Add cache flush command after WALKER command
Change-Id: I3983dc6c0797047e17cc8189655a22a22e85892b
2018-12-19 13:15:33 +01:00
Maciej Plewka 9e81469d9f Disable debug keys for ults
Change-Id: I7f69a770b21a741b5ff79e735c26d988d2b83aab
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2018-12-19 12:30:03 +01:00
Woloszyn, Wojciech 3efff97d19 Modify one of cmake files in ULTs
Change-Id: I2e097e37f587694c3dd5b9a42672d2028a04ad94
Signed-off-by: Woloszyn, Wojciech <wojciech.woloszyn@intel.com>
2018-12-19 12:16:12 +01:00
Kowalczuk, Jakub 53fb222fe7 Unify AUB and TBX CSRs part 3
Move:
- getCsTraits
- initEngineMMIO
- submitLRCA
to common CSR

Change-Id: I8f172b017be2e8f7c54efc8420edd2671d99a927
2018-12-19 12:02:24 +01:00
Kowalczuk, Jakub ba66999f28 Add DebugFlag capability to force disabling/enabling local memory
Change-Id: Ic59780d200cc4b0e1a764b436aa7273c3ca8c728
2018-12-19 12:00:30 +01:00
Mateusz Jablonski b138ff5750 Minor refactoring related to residency task count
Change-Id: I49c9a5b37637e19fa12b7e6d91c352fb78bb117a
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2018-12-19 11:38:49 +01:00
Pawel Wilma 068582445d Move physical address allocator to CommandStreamReceiverSimulatedHw
Change-Id: Ic3c397fe1a93eccae9235f1315a26ae31a3f5b60
Signed-off-by: Pawel Wilma <pawel.wilma@intel.com>
2018-12-19 09:26:31 +01:00
Kamil Diedrich b2e0195663 Change Buffer to MemObj in BufferForAuxTranslation collection
Change-Id: Icbdb8fecaa3fd8e19e993502f59c76156fe4ad2c
2018-12-19 08:05:51 +01:00
Kamil Diedrich 2f88abfa2a Add information about image from buffer extension
- don't change allocation type when buffer is given
- add flag isImageFromBuffer to mem_obj

Change-Id: I48a0722040d8482ed3653540179d047245affa3c
2018-12-18 22:37:33 +01:00
Piotr Fusik e8a71132a4 Remove unnecessary casts.
Change-Id: I2d293d065c7efa006efe7d60a625cba0c6116c86
2018-12-18 13:42:14 +01:00
Dunajski, Bartosz 403fedfb7b Improve EngineInstance usage in Aub CSR
Change-Id: I9097f7cc8c930fcf531744af9bddfa38b2c5e1da
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2018-12-18 12:11:00 +01:00
Cetnerowski, Adam f597052117 ULT renaming: Enqueue Barrier
Change-Id: Ia156766d257dceba566dbae5fc6bc132e015359b
Signed-off-by: Cetnerowski, Adam <adam.cetnerowski@intel.com>
2018-12-18 10:56:21 +01:00
Dunajski, Bartosz 59e6a7be2a Allocate timestamp tag buffer in system memory
Change-Id: I71cb7678edc073fbb2c55e1a617b04959bcb75d7
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2018-12-18 08:54:44 +01:00